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JSS MAHAVIDYAPEETHA

JSS ACADEMY OF TECHNICAL EDUCATION, BENGALURU

DEPARTMENT OF ELECTRONICS & INSTRUMENTATION ENGG.

PEDAGOGICAL PRACTICES IN AY: 2016 – 2017

Various Pedagogical Initiatives Practiced No. of Activities

PPTs 3

Videos 4

E-Learning 3

Practical 2

Quiz 10

Collaborative Learning 6

Animations 2

Projects 1

Self learning 1

Fig: Statistics on various Pedagogical tools Practiced

PPTs 10%

Videos 13%

E-Learning 9%

Practical 6%

Quiz 31%

Collaborative Learning 19%

Animations 6%

Projects 3%

Self learning 3%

Various Pedagogical Initiatives Practiced

JSS MAHAVIDYAPEETHA



INNOVATION IN TEACHING-LEARNING ---------------------------------------------------------------------------------------------------------------------------------------------------

Course Name : Network Analysis Date: 24.11.2016

Course Code : 15EI36 Course Year : Aug-Dec 2016

Semester : 3rd

Subject Faculty Name : Mrs. Bhanumathi K S

COLLABORATIVE LEARNING

A. Solve minimum fifteen problems from each module.

B. Each group has to solve exercise problems from the previous year question papers assigned to their

respective groups.

C. Solving the problems which are already taught in the class is to be strictly avoided.

D. Solve the problems in their respective groups only.

NOTE to STUDENTS:

1. A group of five students is formed by the subject faculty.

2. Solve the problems in your respected groups.

3. The activity will be conducted in the quadrangle of the Department on the days you are free in the

afternoon session.

4. Your activity will be monitored by the subject faculty.

5. Prepare a brief report and submit to the subject faculty.

6. Also the solved problems will be corrected by the subject faculty.

7. Evaluation rubrics are as follows-

a. Participation and Involvement (03 marks)

b. Report (02 marks)

JSS MAHAVIDYAPEETHA




Course Name : Microprocessors & Peripherals Date: 10/11/2016, 11/11/2016, 12/11/2016

Course Code : 10EI53 Course Year : Aug-Dec 2016

Semester : 5th Subject Faculty Name : Ms. Harshitha S

COLLABORATIVE AND SELF LEARNING

GROUP ACTIVITY TO DEVELOP ASSEMBLY LANGUAGE PROGRAMS FOR DIFFERENT

PROBLEM STATEMENTS

Develop and execute 8086 assembly language programs to perform the following.

Sl.

No. Name of the Program

1 Solving a Quadratic Equation

2 Find the product of two 3 X 3 matrices

3 To generate MORSE code for a given alphabet

4 To search an element using linear search method

5 To find the reverse of a given string

6 To compute nCr using recursive procedure

7 To remove space in a given string

8 To find the count of a letter in a given string

9 To check the username is valid or invalid

10 To transfer a string from one memory location to another

11 To read the current time from the system and display it on the screen

12 To find the number of vowels present in a given string

13 To find whether the given 16-bit number is perfect or not

14 To generate Fibonacci series

15 To find whether the given 16-bit number is prime or not

16 To check whether the code word is valid or not

17 To check whether a string is palindrome or not

18 To compare two strings

19 To perform concatenation of two strings

20 To covert the case of the characters in a given string

21 To find the transpose of a 3 X 3 matrix

22 To search a key using binary search method

23 To interface a Logic Controller module and to develop ALP to display four digits binary up/down counter

24 To interface a Logic Controller module and to develop ALP to realize 8:1 MUX

25 To interface a Logic Controller module and to develop ALP to realize an ALU

26 To interface a DAC module and to develop ALP to generate full wave rectified wave

27 To interface a DAC module and to develop ALP to generate half wave rectified wave

NOTE to STUDENTS:

1. Form groups of two in a team and report to the subject faculty.

2. Implement the above exercise in the computer lab as per the given schedule.



a. Implementation in the lab (03 marks)


JSS MAHAVIDYAPEETHA




Course Name : Robotics & Control Date: 04/11/2016, 11/11/2016, 18/11/2016

Course Code : 10IT73 Course Year : Aug-Dec 2016



GROUP ACTIVITY TO PRESENT A SEMINAR ON DIFFERENT APPLICATIONS OF

ROBOTS

NOTE to STUDENTS:

1. Form groups of three or four in a team and report to the subject faculty.

2. Conduct a brief research on different applications of robots

3. Finalize your topic and inform the subject faculty.

4. Prepare a PPT and present in the class as per the given schedule.



a. Presentation skills (02 marks)

b. PPT Preparation (01 marks)

c. Report (02 marks)

JSS MAHAVIDYAPEETHA




Course Name : Signal Conditioning & Data Acquisition Circuits Date: 25.11.2017

Course Code : 15EI42 Course Year : Feb-May 2017

Semester : 4th Subject Faculty Name : Mrs. Bhanumathi K S

USE CREATIVE S/W TOOL (ANY CIRCUIT S/W) FOR LEARNING

E. Design the following circuits using using op-amps

1. Voltage Follower

2. Inverting Amplifier

3. Non-Inverting Amplifier

4. Adder

5. Subtractor

6. Integrator

7. Differentiator

8. Clipping Circuits

9. Clamping Circuits

F. Use the s/w tool to simulate the above circuits (Preferably ANY CIRCUIT S/W).

G. Analyze the circuits operation.

NOTE to STUDENTS:

8. Form groups of two to five in a team and report to the subject faculty.

9. Implement the above exercise and demonstrate the results to the subject faculty.



a. Implementation and demonstration (03 marks)


JSS MAHAVIDYAPEETHA



QUIZ - 1

Semester: 4 Sub Name: SCDAC Sub code: 15EI42

Date: 21.03.17 Time: 11.00-12.00 PM Duration: 1 Hour Marks: 10

Name of the Student:

USN: Signature of the Student:

COURSE OUTCOMES

COs Statements (Students will be able to) Units Covered Blooms Level

1 1. Explain basic concepts, characteristics & specifications of op-amps. Module 1 L2

2 2. Design linear & non-linear circuits using op-amps. Module 2 L3

Note: Tick √ the correct answer.

1. Which is not the internal circuit of operational amplifier? a) Differential amplifier

b) Level translator

c) Output driver

d) Clamper

2. The purpose of level shifter in Op-amp internal circuit is to

a) Adjust DC voltage

b) Increase impedance

c) Provide high gain

d) Decrease input resistance

3. How a symmetrical swing is obtained at the output of Op-amp?

a) Providing amplifier with negative supply voltage

b) Providing amplifier with positive voltage

c) Providing amplifier with positive& negative voltage

d) None of the mentioned

4. What is the purpose of differential amplifier stage in internal circuit of Op-amp? a) Low gain to differential mode signal

b) Cancel difference mode signal

c) Low gain to common mode signal

d) Cancel common mode signal

5. Which of the following is not preferred for input stage of Op-amp?

a) Dual Input Balanced Output

b) Differential Input Single ended Output

c) Cascaded DC amplifier

d) Single Input Differential Output

6. What will be the emitter current in a differential amplifier, where both the transistor are biased

and matched? (Assume current to be IQ)

a) IE = IQ/2

b) IE = IQ

c) IE = (IQ)2/2

d) IE = (IQ)2

.

7. How to improve CMRR value?

a) Increase common mode gain

b) Decrease common mode gain

c) Increase Differential mode gain

d) Decrease differential mode gain

8. Which of the following properties should an ideal op amp have?

a) Infinitely wide bandwidth, infinitely high output impedance and perfect linearity.

b) High DC gain, low input reactance and perfect linearity.

c) Infinitely high input impedance, perfect linearity and zero noise.

d) Infinitely high gain, perfect linearity and zero input impedance.

9. Refer to the given figure. What is the output voltage?

A. 2 V C. +Vsat

B. –2 V D. –Vsat

10. Refer to the given figure. This circuit is known as

A. a non-inverting amplifier. C. an integrator.

B. a differentiator. D. a summing amplifier.

HOD, E&IE SUBJECT FACULTY

JSS MAHAVIDYAPEETHA



QUIZ - 2





COURSE OUTCOMES

COs Statements (Students will be able to) Units

Covered Blooms Level

2 3. Design and implement linear & non-linear circuits using op-amps. Module 3 L1,L2,L3,L4

3 4. Build circuits for communication applications. Module 4 L2,L3,L4,L5,L6

Note: Tick √ the correct answer.

1. Op-amps used as high- and low-pass filter circuits employ which configuration?

1. Open-loop

2. Comparator

3. Inverting

4. Noninverting

2. In order for an output to swing above and below a zero reference, the op-amp circuit requires:

1. zero offset

2. a resistive feedback network

3. a wide bandwidth

4. a negative and positive supply

3.

The rate of change of the output voltage in the given circuit equals ______.

A. 40 mV/ s C. 0 V/ s

B. 5 V/ s D. 40 V/ s

4. A mathematical operation for finding the area under the curve of a graph is called __________.

A. differentiation C. curve averaging

B. integration D. linear regression

5.

The reference voltage for the comparator in the given circuit equals ______.

A. 0 V C. +16 V

B. +8.8 V D.

+7.2 V

6. Above the critical frequency (fc) of a low-pass filter, the output voltage gain _______.

A. does not change C. increases

B. doubles for every 1 kHz increase in frequency D. Decreases

7. In order to sustain oscillations in a feedback oscillator, the gain should be _________ so the Acl _______.

A. reduced, equals one C. increased, is more than one

B. reduced, is less than one D. increased, is much greater than one

8.

The given circuit is a two-pole, active ______ filter.

A. high-pass C. band-pass

B. low-pass D. band-stop

9. A mathematical operation that determines the rate of change of a curve is called __________.

A. differentiation C. curve averaging

B. integration D. linear regression

10. A Wien-bridge oscillator uses _________.

A. positive feedback C. both types of feedback

B. negative feedback D. an LC tank circuit

HOD, E&IE Subject Faculty

JSS MAHAVIDYAPEETHA



QUIZ - 3





COURSE OUTCOMES

COs Statements (Students will be able to) Units Covered Blooms Level

4 5. Develop data acquisition systems. L2,L3,L4,L5,L6 Module 5

Note: Answer all the questions.

1. What is the level of the output voltage of a ladder-network conversion?

A. The analog output voltage proportional to the digital input voltage

B. The digital output voltage proportional to the linear input voltage

C. A fixed digital value Vref

D. A fixed analog value Vref

2. What is the minimum number of conversions per second of a clock rate of 1 MHz operating a 10-stage

counter in an ADC?

A. 1000 C. 769

B. 976 D. 697

3. What is the first phase of the dual-slope method of conversion?

A. Connecting the analog voltage to the integrator for a fixed time

B. Setting the counter to zero

C. Connecting the integrator to a reference voltage

D. All of the above

4. On which of the following does the conversion depend in ladder-network conversion?

A. Comparator C. Digital counter

B. Control logic D. Clock

5. What is the function of a ladder network?

A.

Changing an analog signal to a digital

signal C. Changing a digital signal to an analog signal

B. Changing a linear signal to a digital signal D.

None of the above

6. What is (are) the level(s) of the input voltage to a ladder-network conversion?

A. 0 C. 0 V or Vref

B. Vref D. None of the above

7. This circuit is an example of a ________.

A. comparator C. D to A converter

B. 555 timer D. ladder network

8. What is the voltage resolution of an 8-stage ladder network?

A. Vref /128 C. Vref /512

B. Vref /256 D. Vref /1024

9. A 4-bit R/2R digital-to-analog (DAC) converter has a reference of 5 volts. What is the analog output for the

input code 0101.

A. 0.3125 V C. 0.78125 V

B. 3.125 V D. –3.125 V

10. In a flash analog-to-digital converter, the output of each comparator is connected to an input of a:

A. decoder C. multiplexer

B. priority encoder D. demultiplexer

JSS MAHAVIDYAPEETHA




Course Name : Process Instrumentation Date: 03/04/2017, 22/05/2017 and 25/05/2017

Course Code : 15EI45 Course Year: Feb-May 2017

Semester : 4th Subject Faculty Name: Mrs. Neela A G

GROUP ACTIVITY TO SIMULATE THE MEASUREMENT UNITS USING VIRTUAL

SOFTWARE

Design and simulate the following using virtual instrumentation software.

1. Automatic water control using buzzer.

2. Temperature measurement controller using lab view.

3. Water level controller using lab view.

4. Fuel controller using lab view.

5. Conversion of one temperature scale to other.

6. DC motor speed controller.

NOTE to STUDENTS:

12. Form groups of four/five in a team and report to the subject faculty.

13. Simulate the above circuits using the mentioned virtual instrument as per the given guidelines.



a. Simulation (03 marks)


JSS MAHAVIDYAPEETHA




Course Name : DSP Architecture Date: 25/05/2017

Course Code : 10EI64 Course Year : Feb-May 2017



GROUP ACTIVITY TO CONDUCT A BRIEF RESEARCH ON ARCHITECTURES OF DIFFERENT

TMS PROCESSORS

NOTE to STUDENTS:

16. Form groups of three or four in a team and report to the subject faculty.

17. Conduct a brief research on different TMS processors.

18. Finalize your topic and inform the subject faculty.



a. Topic Selection (01 mark)


JSS MAHAVIDYAPEETHA




Course Name : Mechatronics Date: 01.06.2017

Course Code : 1EI664 Course Year : Feb-June 2017

Semester : 6th

Subject Faculty Name : Mrs. Bhanumathi K S

LEARN THROUGH PROJECTS

H. Develop a model by applying Mechatronics principle.

I. The project should involve the following engineering sections.

a. Electronics

b. Mechanical and

c. Computer Science

NOTE to STUDENTS:

21. Form groups of two to five in a team and report to the subject faculty.

22. Implement the above exercise and demonstrate the project to the subject faculty.

23. Prepare a project report and submit to the subject faculty.


a. Implementation and demonstration (03 marks)


JSS MAHAVIDYAPEETHA



INNOVATION IN TEACHING-LEARNING ---------------------------------------------------------------------------------------------------------------------------------------

Course Name : BMDSP Date: 20.05.2017

Course Code : 10IT842 Course Year: Feb-May,2017

Semester : 8th Subject Faculty Name: Mrs. Anu H

GROUP ACTIVITY TO ANALYSE EEG SIGNALS BY CLINICAL LABORATORY

VISIT

Visit to Clinical Laboratory.

1. Students are required to visit clinical laboratory.

2. Analyze the fixization of 10-20 electrode placements for EEG recording on patient.

3. Understand the recording of EEG Signal.

4. Analyze the report taken and determine the ailment if any.

NOTE to STUDENTS:

25. Form groups of two in a team and report to the subject faculty.

26. Implement the above exercise by visiting clinical laboratory as per the given schedule.



a. Report collected from clinical laboratory (03 marks)


JSS MAHAVIDYAPEETHA



INNOVATION IN TEACHING-LEARNING ---------------------------------------------------------------------------------------------------------------------------------------

Quiz – I

USN:

Course Name : BMDSP Date: 25.03.2017 Course Code : 10IT842 Time: 02.30-03.30 PM

Course Year : Feb-May 2017 Max. Marks: 05

Semester : 8th Subject Faculty Name: Mrs. Anu H

Note: Answer all the questions. Write the correct answers in column provided. Each question carries 0.5

marks. COURSE OUTCOME

COs Statements (Students will be able to) Blooms

Level

CO2 Apply the knowledge of EEG signals in Neurological signal processing and

sleep EEG. L3

CO3 Make use of different methods for linear prediction, adaptive

interference/noise canceller and prony’s methods. L3

CO4 Analyze cardiological signal processing. L4

1. Noise cancelling is a variation of ………………………………………………….

2. Wiener filter acts like ………………………………………………………………

3. In Wiener filter primary and secondary input are ………………………………….

4. Optimal value of Wiener filter is given by …………………………………………

5. Mean square error is calculated by using ……………………………………………

6. Minimum mean square is calculated using ………………………………………….

7. LMS algorithm belongs to family of ………………………………………………..

8. In LMS algorithm, if number of tap weights is M ,………………… multiplications and ……………

additions are required.

9. In noise canceller, reference noise is ………………………………. with desired signal.

10. Adaptive noise canceling is used in heart-transplant cardiograph to obtain the desired signal

of……………….heart.

Answers:

Q1.

Q2.

Q3.

Q4.

Q5.

Q6.

Q7.

Q8.

Q9.

Q10.

Faculty In-charge HOD, E&IE

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