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IEEE Proof Web Version IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010 1 A Class-G Headphone Amplifier in 65 nm CMOS Technology Alex Lollio, Giacomino Bollati, and Rinaldo Castello, Fellow, IEEE Abstract—This paper presents a class G amplifier based on a low distortion switching principle technique called switching currents injection. The switching circuit enables a very smooth handover between the voltage supply rails obtaining both high efficiency and low distortion. An approach for the evaluation of the switching dis- tortion in a class G amplifier (and the ability of the loop to reject it) is proposed and the results obtained are used to optimize the overall distortion after compression by the feedback loop. The integrated 65 nm CMOS class G headphone driver based on the above con- cept operates from 1.4 V and 0.35 V supplies. At low power level it uses almost exclusively the low voltage supply reducing the dissipation to 1.63 mW @ 0.5 mW into 32 . At higher power level, where both supplies are used, the smooth transition between the rails allows a better than 80 dB for 16 mW into 32 . The SNR is 101 dB, quiescent power is 0.41 mW and active die area is 0.14 mm . Index Terms—Class G amplifier, audio amplifier, efficiency, lin- earity, power amplifier, headphone driver, low power consumption. I. INTRODUCTION M ODERN cellular phones incorporate hands-free oper- ation, MP3 music playback and DMB reception. The users may wish to activate these features for many hours and a low efficiency amplifier could deplete the battery in a short time. There are two classes of power amplifiers generally used for this application: Class-D and Class-AB. Class-D architectures pro- vide the benefit of power efficiency at the cost of slightly re- duced performance (especially noise and distortion) and a level of switching noise, which might, in some cases, interfere with RF functions such as mobile phone, GPS or FM radio reception. Class AB architecture has the benefit of higher audio quality and does not produce any switching noise, but its power efficiency is much lower. Notwithstanding their lower efficiency, the great majority of the headphone drivers on the market today operate in Class AB mode. A class G is an analog amplifier having an efficiency compa- rable to that of a class D (without EMI problems) and a linearity comparable to that of class AB. Fig. 1(a) shows a schematic block representation of a class G amplifier. It uses two voltage supply rails (VHV is the high voltage rail and VLV is the low Manuscript received April 21, 2010; revised July 12, 2010; accepted Au- gust 19, 2010. This paper was approved by Guest Editor Gyu-Hyeong Cho. This work was supported by the Italian National Program FIRB, under Con- tract RBAP06L4S5. A. Lollio and R. Castello are with the Dipartimento di Elettronica, Università degli Studi di Pavia, 27100 Pavia, Italy (e-mail: [email protected]). G. Bollati is with Marvell Semiconductors, Pavia 27100, Italy. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2010.2076450 voltage rail) and switches to the appropriate supply as required by the instantaneous output voltage level. In this way, it never uses the high supply voltage when a low voltage output is re- quired which would waste power [1]. The core of a class G am- plifier is the switching circuitry, which should enable a smooth handover of the load driving between the lower voltage supply and the higher one. The switching point is defined as the output voltage level where the amplifier switches from one supply to the other. In this design we define two switching point levels called VLV-VTH and , where VLV is the value of the amplifier low voltage supplies and VTH is a threshold voltage (see Fig. 1(b)). The switching strategy should satisfy two key points: first, the distortion due to the switching opera- tion must be minimized to maintain high audio quality; second, the switching point must be as close as possible to the low voltage supply (VLV) to maximize efficiency (this means that VTH must be as low as possible). This paper is organized as follows. Section II shows general design considerations about the class G amplifier design, Section III introduces the principle of the new switching technique and the class G amplifier model, Section IV highlights the switching speed restriction, Section V shows the amplifier architecture and finally Section VI gives the experimental results. Conclusions are given in Section VII. II. CLASS GDESIGN CONSIDERATIONS There are two basic ways in which class G amplifiers are re- alized [2]: the “series” implementation (shown in Fig. 2(a)) and the “parallel” implementation (shown in Fig. 2(b)). Thanks to its simplest switching circuit, the most common implementa- tion is the series one. It uses a single output stage connected to both the low voltage and to the high voltage supply rails re- spectively through diodes and switches. The main limitation of the series topology is due to the diodes in series with the low voltage supply that make this implementation unsuitable for low voltage application. In fact, the turn-on voltage of the diode puts a strong limitation both on the minimum value of VLV and on the switching point distance from VLV. On the other hand, in the parallel topology, shown in Fig. 2(b), there are two output stages working in parallel and there is nothing between the power transistors and the supplies. This fact poses no constraints on the minimum value of VLV and allows placing the switching point very close to VLV, giving higher ef- ficiency. This is shown in Fig. 3(a) in which the efficiency of a class G amplifier is plotted versus output power for different switching point levels and compared with that of a class AB able to handle the same maximum power. The core of the parallel topology is the switching circuit which must simultaneously enable low distortion and high 0018-9200/$26.00 © 2010 IEEE

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010 1

A Class-G Headphone Amplifierin 65 nm CMOS Technology

Alex Lollio, Giacomino Bollati, and Rinaldo Castello, Fellow, IEEE

Abstract—This paper presents a class G amplifier based on a lowdistortion switching principle technique called switching currentsinjection. The switching circuit enables a very smooth handoverbetween the voltage supply rails obtaining both high efficiency andlow distortion. An approach for the evaluation of the switching dis-tortion in a class G amplifier (and the ability of the loop to reject it)is proposed and the results obtained are used to optimize the overalldistortion after compression by the feedback loop. The integrated65 nm CMOS class G headphone driver based on the above con-cept operates from 1.4 V and 0.35 V supplies. At low powerlevel it uses almost exclusively the low voltage supply reducing thedissipation to 1.63 mW @ ���� � 0.5 mW into 32 �. At higherpower level, where both supplies are used, the smooth transitionbetween the rails allows a ��� � � better than 80 dB for���� 16 mW into 32 �. The SNR is 101 dB, quiescent poweris 0.41 mW and active die area is 0.14 mm�.

Index Terms—Class G amplifier, audio amplifier, efficiency, lin-earity, power amplifier, headphone driver, low power consumption.

I. INTRODUCTION

M ODERN cellular phones incorporate hands-free oper-ation, MP3 music playback and DMB reception. The

users may wish to activate these features for many hours and alow efficiency amplifier could deplete the battery in a short time.There are two classes of power amplifiers generally used for thisapplication: Class-D and Class-AB. Class-D architectures pro-vide the benefit of power efficiency at the cost of slightly re-duced performance (especially noise and distortion) and a levelof switching noise, which might, in some cases, interfere withRF functions such as mobile phone, GPS or FM radio reception.Class AB architecture has the benefit of higher audio quality anddoes not produce any switching noise, but its power efficiencyis much lower. Notwithstanding their lower efficiency, the greatmajority of the headphone drivers on the market today operatein Class AB mode.

A class G is an analog amplifier having an efficiency compa-rable to that of a class D (without EMI problems) and a linearitycomparable to that of class AB. Fig. 1(a) shows a schematicblock representation of a class G amplifier. It uses two voltagesupply rails (VHV is the high voltage rail and VLV is the low

Manuscript received April 21, 2010; revised July 12, 2010; accepted Au-gust 19, 2010. This paper was approved by Guest Editor Gyu-Hyeong Cho.This work was supported by the Italian National Program FIRB, under Con-tract RBAP06L4S5.

A. Lollio and R. Castello are with the Dipartimento di Elettronica, Universitàdegli Studi di Pavia, 27100 Pavia, Italy (e-mail: [email protected]).

G. Bollati is with Marvell Semiconductors, Pavia 27100, Italy.Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/JSSC.2010.2076450

voltage rail) and switches to the appropriate supply as requiredby the instantaneous output voltage level. In this way, it neveruses the high supply voltage when a low voltage output is re-quired which would waste power [1]. The core of a class G am-plifier is the switching circuitry, which should enable a smoothhandover of the load driving between the lower voltage supplyand the higher one. The switching point is defined as the outputvoltage level where the amplifier switches from one supply tothe other. In this design we define two switching point levelscalled VLV-VTH and , where VLV is the valueof the amplifier low voltage supplies and VTH is a thresholdvoltage (see Fig. 1(b)). The switching strategy should satisfytwo key points: first, the distortion due to the switching opera-tion must be minimized to maintain high audio quality; second,the switching point must be as close as possible to the lowvoltage supply (VLV) to maximize efficiency (this means thatVTH must be as low as possible). This paper is organized asfollows. Section II shows general design considerations aboutthe class G amplifier design, Section III introduces the principleof the new switching technique and the class G amplifier model,Section IV highlights the switching speed restriction, Section Vshows the amplifier architecture and finally Section VI gives theexperimental results. Conclusions are given in Section VII.

II. CLASS G DESIGN CONSIDERATIONS

There are two basic ways in which class G amplifiers are re-alized [2]: the “series” implementation (shown in Fig. 2(a)) andthe “parallel” implementation (shown in Fig. 2(b)). Thanks toits simplest switching circuit, the most common implementa-tion is the series one. It uses a single output stage connectedto both the low voltage and to the high voltage supply rails re-spectively through diodes and switches. The main limitation ofthe series topology is due to the diodes in series with the lowvoltage supply that make this implementation unsuitable for lowvoltage application. In fact, the turn-on voltage of the diode putsa strong limitation both on the minimum value of VLV and onthe switching point distance from VLV.

On the other hand, in the parallel topology, shown in Fig. 2(b),there are two output stages working in parallel and there isnothing between the power transistors and the supplies. This factposes no constraints on the minimum value of VLV and allowsplacing the switching point very close to VLV, giving higher ef-ficiency. This is shown in Fig. 3(a) in which the efficiency ofa class G amplifier is plotted versus output power for differentswitching point levels and compared with that of a class AB ableto handle the same maximum power.

The core of the parallel topology is the switching circuitwhich must simultaneously enable low distortion and high

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Fig. 1. Class G amplifier: simplified block diagram (a) and output voltage versus time with the supply voltages and the switching point level (b).

Fig. 2. Class G topologies: serial (a) and parallel (b).

efficiency. If the output voltage of the class G amplifier isbelow the switching point level, the ratio between the efficiencyof the class G and the class AB is approximately equal to theratio between the value of the high and low supplies:

(1)

Music has a large peak-to-average power ratio which can varyfrom 10 dB for compressed rock to 30 dB for classical music[3]. This implies that the output power is below the peak levelfor most of the time. As a consequence power efficiency canimprove significantly taking advantage of class-G operation.

Fig. 3(a) shows the strong impact of the switching point levelon the efficiency. The switching point should be set as close aspossible to the low voltage supply VLV (ideally VTH should beequal to zero). However, if VTH is too small, the power transis-tors supplied by the low voltage rail have to work in deep trioderegion for a significant portion of time affecting the total har-monic distortion (THD) of the amplifier as shown in Fig. 3(b).The value of VTH needs to be chosen as a trade off between ef-ficiency and linearity.

In this work a class G parallel topology, which implementsa novel switching principle approach based on a switching cur-rent injection, is presented. The proposed switching principleenables very low distortion (better than dB) despite the

switching point beings only 50 mV away from the low voltagesupply ( mV).

III. CLASS G SWITCHING PRINCIPLE

The goal in a class G amplifier design is to find a switchingprinciple which maximizes the efficiency and limits the dis-tortion introduced by the switching operation. In this Sectionthe switching circuit proposed and its effects on the amplifierlinearity are presented. Using a simple 2 stages model we willstudy the distortion introduced by the switching circuit andthe capability of the loop to reject it. In order to simplify thediscussion, the class G amplifier (based on a parallel topology)is derived from a class A amplifier. The obtained conclusionscan, however, be easily extended to a push-pull class AB outputstage. The following equation describes the low frequencyinput-output transfer function of the two stages class A ampli-fier shown in Fig. 4(a):

(2)

Starting from this class A amplifier we want to build a simpleclass G one which switches from one supply rail to the other one.To do this, let us start to split transistor M3 into two transistorsM3L and M3H as shown in Fig. 5(a). The input-output transferfunction is given by the following equation:

(3)

where gm3L(Vo) and gm3H(Vo) represent the transconductanceof the low and high voltage output stages as a function of theoutput voltage (as long as the load in the band of interest ispurely resistive the dependence of gm3 on output current trans-late in a dependence on the output voltage).

Let us first suppose to implement an ideal switching betweenthe output stages in such a way that the switching operation doesnot introduce any extra distortion. This is obtained if the totalequivalent transconductance of the output stages of the circuitshown at the top of Fig. 5(a) given byis equal to the transconductance gm3(Vo) shown in Fig. 4(b). Ina real implementation this condition is difficult to satisfy, how-ever, it will be used only to derive the linear model shown at theend of this section and the analysis carried out on this simplifiedmodel, will shows that the sensitivity of the switching distor-tion to variations of the gm3 value is very low. Furthermore, thetwo output stages have the same topology making not difficult

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Fig. 3. Class G efficiency (a) and the total harmonic distortion versus the output power at different switching point level (b).

Fig. 4. Simple class A amplifier (a) and plot of the output stage transconductance versus the output voltage (b).

Fig. 5. Class G output stage with the switching circuit (a) and graphical relation between gm3L, gm3H, IJL and IJH versus the output voltage.

to keep the variation of gm3 during switching smaller than thatdue to the output current variation (typically the main source of

nonlinearity in a class AB amplifier). It will be shown that thedifference between the simulated behavior of the real amplifier

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connected in unity gain configuration as shown in Fig. 7(a) andthe model is acceptably small.

A possible behavior of gm3L and gm3H as a function ofthe output voltage that satisfy the ideal condition

is described in Equations (4) and (5),shown at the bottom of the page, whereand represent two voltage levels such thatthe switching point is in the middle betweenthem. The output voltage range is where the switching oper-ation takes place. The expression defines how the valueof gm3L evolves during switching and, for our purposes, doesnot need to be explicitly known.

Fig. 5(b) shows a graphical representation of these equa-tions where it can be immediately seen that

. Unfortunately this ideal situationcannot be realized in practice because the handover betweenone stage and the other requires an additional circuit able toforce such a transition. Fig. 5(a) shows this circuit which isimplemented as a differential pair that compares the outputvoltage to the switching point voltage . Thedifferential pair sends its bias current, IBIAS, either to the gateof M3L or to the gate of M3H according to the result of thecomparison. The value of IBIAS and the transconductance ofthis differential pair determine the speed of the transition.

Let us assume that gm3L and gm3H still have the expressionwritten in (4) and (5). In a similar way we can write the equations(6)-(7), shown at the bottom of the page, representing the currentIJL injected into the gate of M3L and the current IJH injectedinto the gate of M3H: The expression defines how thevalue of gm3H evolves during switching and, as , doesnot need to be explicitly known.

Fig. 6. Amplifier model of Fig. 5(a) used to analyze the switching distortion.

Fig. 5(b) shows a graphical representation of the switchingparameters (transconductances and currents) versus the outputvoltage. From the simple class G implementation of Fig. 5(a)we obtain the following input-output characteristic:

(8)

If we combine the (4)–(8) we obtain the following relation:

(9)

where is as shown in (10) at the bottom of the page.It is interesting to note that the input-output transfer functionfor the model shown in Fig. 6 is the same as that expressedby (9). This means that it is possible to model the distortion

(4)

(5)

(6)

(7)

(10)

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Fig. 7. Class G amplifier closed in a unity gain feedback loop (a) and the simulated parameters versus time (b).

introduced by the switching circuit with a current source (con-nected to the input of the last stage of the linear circuit of Fig. 6)that injects an unwanted signal at the harmonics of the input.This is consistent with what is done in literature [4] to modelthe nonlinearity due to the last stage of a class AB amplifier.Such a model will be used to understand the dependence of theswitching distortion on the circuit parameters in order to opti-mize the overall class G amplifier performance. Fig. 7(a) showsthe real class G amplifier connected in a unity gain feedbackconfiguration while Fig. 7(b) shows the time domain represen-tation of the output voltage and some key currents all obtainedthrough simulation. A design target is to size the two outputstages to minimize the variation dueto switching as shown in Fig. 5(b), nonetheless the circuit ofFig. 7(a) has been intentionally sized to have a significant vari-ation of (as shown in Fig. 7(b)). Thiswas done to show that this is not a strict requirement for themodel to remain valid as confirmed by the simulated resultsshown later in this section.

Using the model of Fig. 8(a), the relation between the injectedcurrents and the output voltage can be computed obtaining thefollowing expression:

(11)

Assuming and (11) becomes:

(12)

Equation (12) expresses the ability of the amplifier to reject theswitching distortion. The closed loop residual distortion is in-

versely proportional to gm2 and directly proportional to IBIAS(since is proportional to IBIAS). In headphone application, theamplifier bandwidth of a two stage amplifier is approximatelygiven by gm2/CM and needs to be much higher than the signalbandwidth (20 kHz). This means that the distortion introducedby the switching circuit is, to first order, insensitive to the valueof CM, gm3 and RL. The result is quite different from the re-jection of the distortion due to the output stage (that is the mainsource of distortion in a class AB stage). In fact, in this case,the distortion can be modeled as a current source, ,connected to the output node of the amplifier [4] (see Fig. 8(b)).The transfer function from to Vo can be calculated andsimplified assuming:

The result is given in (13):

(13)

To minimize distortion in a class AB, gm3 needs to be thehighest allowed by power consumption constraints and theclosed loop bandwidth needs to be the highest allowed bystability requirements. Equation (13) does not give constraintson the absolute values of gm2 and CM but only on their ratio.Equation (12), instead, shows that the ability of the loop toreject switching distortion is directly proportional to the abso-lute value of gm2. The requirement of an high gm2 value hasnegligible effect on the power consumption but forces to usea compensation capacitor CM much bigger than the one thatcould be used in a class AB amplifier with a significant increasein silicon area.

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Fig. 8. Amplifier model of Fig. 7(a) used to analyze the amplifier rejection to the switching distortion (a), and amplifier model used to analyze the amplifierrejection to the last stage nonlinearity (b).

Fig. 9. Comparison between the simulated THD and the model of Fig. 8(a).

We have simulated the THD of the simplified class G ampli-fier for a 1 kHz input signal with 400 mV peak to peak ampli-tude centered around mV. The simulations were carriedout under the following operating conditions V,

V mV and assumingthe following parameter values A/V, cm pF,

Ohm, A, mA/V (at DCpoint).

We have chosen a switching point relatively far from the lowvoltage supply ( mV). This was done to insure thatthe overall distortion is primarily caused by the switching oper-ation. In this way we are able to validate the model of Fig. 8(a).On the other hand, if the switching point is chosen very closeto the low voltage supply (i.e., VTH close to zero), the distor-tion caused by the nonlinearity of the last stage becomes dom-inant. Fig. 9 shows the dependence of THD on various designparameter values (IBIAS, gm2, RL, CM). The plots display bothsimulated results and analytical calculation obtained using (12).The expression for the current Ij (necessary to calculate the ab-solute value of the distortion for the model of Fig. 8(a)) has notbeen analytically derived. Instead, the first calculated value ofeach plot has been taken equal to the simulation result obtainedfrom the circuit of Fig. 7(a) and the others have been calculatedstarting from these points. It can be seen how the simulation re-sults validated the equations derived from the model of Fig. 8(a).

In particular the plot of THD as a function of CM shows that,as predicted by (12) switching distortion is independent fromthe CM value. This is different from what happens to the outputstage distortion (predicted by (13)).

IV. SWITCHING SPEED LIMITATION

In the previous Section it has been shown that the distor-tion introduced by the switching circuit is proportional to theswitching current IBIAS. Therefore, to achieve high linearityIBIAS should be taken as small as possible while still insuringproper operation. The first limit to the minimum usable value forIBIAS is determined by matching requirements. For the ampli-fier of Fig. 7(a) a mismatch associated with the pMOS transis-tors in the top mirrors causes an error current which appear at thesame points as the injected switching current. If the switchingcurrent value (IBIAS) is smaller than the maximum equivalentmismatch current of the pMOS transistors, the switching circuitmay not be able to switch on and off the output stages as re-quired to implement class G operation.

The second potential limit to the minimum value of IBIASis defined by the switching speed requirements. This limit cansignificantly affect the amplifier linearity, and, for this reason, acircuit which overcomes the problem has been introduced.

The speed limitation is due to the fact that the output MOStransistor M3L is switched off by pulling down its gate with the

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Fig. 10. Class G amplifier schematic including the hard switching circuit (a) and the output currents versus time using or not the hard switching (b).

small current IBIAS. Since the capacitive load at this gate issignificant (being the sum of the gate capacitance of M3L andof the Miller capacitance CM) the switching time can be verylong.

Also, M3L needs to be switched off when the output voltageis close to the switching point i.e., when it is delivering its max-imum current and its gate voltage is close to VHV. Further-more, in order to keep M3L off even when the output voltageapproaches its gate should be pulled all the way downto . In fact, if this is not the case, the terminal of M3L,connected to the output, starts to behave as a source and a crossconduction current can flow from to .

Due to all the above constraints the required voltage variationon the gate of M3L and the corresponding switching time arerelated by the following equation:

(14)

The minimum allowable value for in which the switchingmust be completed (no cross conduction) is given by the timeduring which the output voltage at the maximum audio fre-quency (20 kHz) goes from to . Fig. 1(b)shows a graphical representation of the minimum allowablevalue for the time interval while (15) gives its value:

(15)

Combining (14) and (15) it is possible to obtain an expressionfor the minimum allowed switching current (IBIAS):

(16)

This represents the minimum value for IBIAS which still ensurea correct switching operation in the worst case condition thatcorrespond to the maximum gate voltage swing

and maximum output voltage slope (i.e., maximumsignal frequency and maximum output signal amplitude VHV).

For this design, (16) suggests a value of IBIAS of 40 A thatis much higher than the value necessary to satisfy the matchingrequirements (1 A).

In order to use a value of IBIAS smaller than the one re-quired using (16), which means less distortion, we have im-plemented a hard switching circuit which immediately switchesoff M3L when the output voltage falls below the negative lowvoltage supply . Fig. 10(a) shows the implementationof the class G amplifier including such hard switching circuitwhich is made up by a comparator and a switch (realized usingan nMOS transistor). If the output voltage Vo is higher than

the switch is open and the amplifier works as describedin the previous section. When Vo falls below the switchis turned ON hard by the comparator and the gate of M3L isimmediately connected to the output node Vo forcing the gate-source voltage of M3L to be equal to zero. The hard switchingcircuit does not introduce any additional distortion because itacts when the VDS of M3L is equal to zero i.e., when M3Lis not contributing any current to the output. The plot at thetop of Fig. 10(b) shows the output currents without the hardswitching circuit assuming a small IBIAS value (used to re-duce switching distortion). A current glitch flows between thesupplies ( and ) when the output voltage crossesthe switching point. This current means wasted power and has anegative impact on the overall distortion. The plot at the bottomof Fig. 10(b) shows that the glitches have been removed. How-ever, the limited speed with which the gate of M3L can be turnedON (that still depends only on IBIAS/ since thehard switching circuit is of no help) affects the shape of the

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Fig. 11. Amplifier architecture: a three stage opamp with a detail on the last stage compensation approach.

output currents that appear to be nonsymmetric. These nonsym-metrical output currents only slightly affect the linearity (even athigh frequency) and the efficiency and they have been acceptedin this design. As a consequence the value of IBIAS has beendefined only by matching requirements. To minimize the am-plitude of current glitches on the output node the comparatorshave been designed to have a rise/fall time smaller than 10 usand an offset smaller than 5 mV. The residual offset does notaffect significantly the linearity because the harmonics fall out-side the audio bandwidth.

V. AMPLIFIER ARCHITECTURE

The implemented class G headphone driver uses a differentialinput and single ended output topology. The number of stagesto be used depends on the linearity requirements: three stagesare enough to satisfy the target THD of dB at 1 kHz.

Fig. 11 shows the chosen architecture. The amplifier mainpath is composed of three stages compensated using the nestedMiller techniques [5]. In order to save quiescent power con-sumption, the last stage gm3 is compensated using an active-feedback compensation technique [13] as shown in Fig. 11. Thefirst stage, gm1, drives two parallel paths. One is made up by thecascade of gm2 and gm3L and the other one by the cascade ofgm2 and gm3H. The switching stage alternatively enables oneof these two parallel paths according to the output voltage levelrelative to the threshold level. Only the gm3L stage is suppliedby the low voltage rail VLV while the rest of the circuit is sup-plied by the high voltage rail VHV.

Fig. 12 shows a somewhat simplified transistor level imple-mentation of the amplifier. The first stage, gm1, is a conven-tional pMOS differential pair that also implements the differen-tial to single ended conversion. The second stage is made up bythe nMOS transistor M2 that drives a pMOS current mirror withone input and two pairs of output. The floating battery, shownin Fig. 12, is a circuit used to control the quiescent bias currentof the push-pull low voltage output stage, gm3L [6]. The com-plete output stage is composed by two push-pull class AB paths

working in parallel (for simplicity, in the previous sections onlythe pull-down part was shown). The switching principle is thesame as the one reported in the previous section. The switchingcircuit is composed by two differential pairs: one of them actson the nMOS power transistors and the other one acts on thepMOS power transistors. For simplicity the hard switching cir-cuit has not been shown: it is built with two comparators and twoswitches which rapidly switch off the nMOS and pMOS lowvoltage power transistors when the output voltage falls below

or rise above VLV.Switching Distortion Analysis: The switching distortion

analysis that was carried out in Section III for the case of atwo stages amplifier can be easily extended to a three stagetopology. Fig. 13 shows the simplified linear model corre-sponding to this case.

The transfer function from the switching current to the outputis given by

(17)

Where is the closed loop dBangular frequency of the amplifier that, in this design, is muchhigher than the signal bandwidth krad/s versusan audio bandwidth of kHz). Moreover, for stabilityreasons, has been chosentwice as high as . It follow that (17) can be approximated by(18) with very good accuracy.

(18)

The simple relation reported in (18) expresses with good ap-proximation the ability of the used three stage amplifier to rejectthe unwanted current injection Ij associated with the switchingcircuit. From (18) we can see that the amount of switching dis-tortion compression operated by the amplifier is proportional tothe value of gm2 as in the case of a two stages amplifier.

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Fig. 12. Transistor level implementation of the class G opamp.

Fig. 13. Simplified model of the class G amplifier shown in Fig. 12.

As for the simpler two stage amplifier of Section II the THDof the complete amplifier has been obtained via simulation ap-plying a 1 kHz 600 mVpp tone centered at 0 V at its input underthe following operating conditions V,V and assuming the following parameters A/V,

A/V, mA/V (simulated in DC oper-ating point), pF, pF. Again the switchingpoints have been chosen far from the low voltage supply VLV( mV) to avoid saturation effects of the low voltagestage.

Following the same procedure described in Section III themodel of Fig. 13 has been validated evaluating the distortion

sensitivity to the key circuit parameters and comparing the re-sults with the simulations on the real circuit. Fig. 14 shows thatthe comparison results validate the expression given by (18).

VI. EXPERIMENTAL RESULTS

To achieve a high integration level, placing the headphoneamplifier on the same die with the baseband processor would beadvantageous. In this case the digitally intensive nature of theprocessor forces the usage of a deeply scaled CMOS technology,such as 65 nm or below.

The prototype class G amplifier reported here (designed towork using a high voltage supply V and a lowvoltage supply V) has been realized using the 1.8V devices available in 65 nm CMOS. For reliability reasons notransistor should see (even during transients) a gate to sourceand gate to drain voltage that exceed the maximum value al-lowed by the process. Since the amplifier output voltage swingsfrom V to 1.4 V, the 1.8 V output transistors need to becascaded and the biasing circuit should be carefully designedto ensure that no device is stressed beyond its limit even duringpower on/off transients.

The die micrograph is shown in Fig. 15 and corresponds to asilicon area of 0.14 mm per channel. We have integrated bothaudio channels. Table I shows the values of gm’s in the threestages and that of the compensation capacitors. CM2 representsthe value of each compensation capacitors used across the fouroutput transistors: this means that the total capacitance is fourtimes the CM2 reported. As explained in Section III the area

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Fig. 14. Comparison between the simulated THD of the class G opamp of Fig. 12 and the model of Fig. 13.

Fig. 15. Die micrograph.

occupied is much bigger than the area necessary to compensatea class AB amplifier.

The switching point has been set only 50 mV away from thelow voltage supplies making it possible to scale VLV down to0.35 V while still having good efficiency up to an output powerof 1.5 mW on a 32 load. Fig. 16 shows the efficiency andthe Signal to Noise Distortion Ratio versus theoutput power that displays the classical nonmonotonic behaviorof class G amplifiers, measurements have been performed usingan A-weighted filter. Better than 30% efficiency is achievedfrom mW to the maximum deliverable outputpower of 30 mW, for a 1 kHz tone is better than 80 dBin the entire operating range and reaches dB just below thepower level for which class G operation begins to occur at thesignal peaks. As expected, beyond this point the plotshows a slight degradation (a step of about 6 dB occurs at the

TABLE ITABLE OF GM’S AND CURRENTS IN THREE STAGES

AND COMPENSATION CAPACITORS

output amplitude corresponding to the switching point). Fig. 17shows the power dissipation versus the delivered output power(per channel). A key target for a headphone driver is to mini-mize the power dissipation when the delivered output power is0.1 mW and 0.5 mW into a 32 load. This is because suchpower levels define the range of operation of a typical headsetspeaker used to reproduce MP3 audio signals. In those condi-tions, the proposed driver dissipates much less than today stateof the art circuits [7]–[12]. When the output power is below 1.5mW the amplifier uses only the low voltage stage thanks to thelow VTH used and the power dissipation is less than 3 mW asshown in Fig. 17. To deliver an output power exceeding 1.5 mWrequires also the use of the high voltage stage. As shown by the

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Fig. 16. Total harmonic distortion and efficiency versus the output power.

Fig. 17. Amplifier power consumption versus the delivered output power.

plot from this point on the power dissipation increases at a muchhigher rate with the delivered power.

Fig. 18 shows a plot of THD versus frequency for two dif-ferent output power levels (2 mW and 5 mW). In both casesdistortion increases with frequency up to kHz (abovethis frequency distortion appears to decrease because THD hasbeen evaluated only in the signal band integrating both noiseand harmonics up to 20 kHz). In the frequency range of interestthe maximum THD degradation with respect to low frequencyis only 10 dB and this is a very good result for a class G ampli-fier [10], [11].

In Fig. 19 the output spectra at two different output powerlevels are shown. In Fig. 19(a) the output power is 1 mW (thislevel is below the switching threshold and the amplifier worksalways in class AB) producing a very clean spectrum. On theother hand, in Fig. 19(b) the output power is 20 mW. In thiscondition the amplifier uses both the output stages (class G op-eration) and the spectrum includes also the harmonic distortion

Fig. 18. Total Harmonic Distortion versus frequency.

introduced by the switching operation. In both cases, the distor-tion is dominated by the second harmonic.

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Fig. 19. Output spectra at two load power levels.

TABLE IICLASS G PERFORMANCE SUMMARY COMPARED WITH RECENT PAPERS

This work has been compared with class AB, D, H, andG amplifiers reported in technical literature or in commercialdatasheets. In Table II the performance summary of the am-plifier and a comparison with class AB and D amplifiers takenfrom technical literature is shown. In this table the problemof the supply voltage generation is not considered. For a fairreading of this table, it must be taken into account that the classG amplifier, compared with class AB and D amplifiers, needsan additional supply rail . The negative high voltagesupply, instead, is widely used to avoid external decouplingcapacitor (whose linearity is a limit for the audio quality).

The quiescent power consumption is 0.41 mW which is 3times less than the lowest reported. The peak deliverable poweronto a 16 Ohms load is 90 mW. The total harmonic distortionis 80 dB when the delivered output power is 16 mW. The signalto noise ratio (A-weighted) is 101 dB.

Table III shows the performance summary compared withrecent class H and G commercial products. Unfortunately thedatasheets do not give the performance of the stand alone am-plifier. For example, [9] includes the power consumption of twocharge pumps while [10], [11] include power consumption ofone charge pump and one buck converter. The buck converter isused to generate VLV starting from VHV and the charge pumps

are used to generate the negative supply voltages and. In order to make a fair comparison the power consump-

tion of the charge pumps and of the buck converter need to beestimated.

Conservative power estimation for the two inverting chargepumps, with 2.5 Ohm of series resistance, is 0.6 mW (0.3 mWper channel). This power is fairly independent from the deliv-ered current. On the other hand Buck converter efficiency in-creases with the delivered current. We assumed quite a low ef-ficiency that should be easily achievable: 50% when deliveringthe quiescent current (0.4 mA) resulting in 0.1 mW power dissi-pation and 70% when the output power is between 0.1 mW and0.5 mW. Table III shows the overall power consumption of thereported class G amplifier taking into account also the contribu-tion of the charge pumps and the buck.

VII. CONCLUSION

A novel class G switching technique based on current injec-tion has been presented and a simple linear model of the classG amplifier, that allows to evaluate the compression operatedby the loop on the switching distortion has been proposed. Themain goal of this work was to achieve high efficiency while min-imizing linearity degradation due to the switching operation.

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TABLE IIICLASS G PERFORMANCE SUMMARY COMPARED WITH RECENT COMMERCIAL PRODUCTS

The proposed architecture achieves on the one hand high effi-ciency (being compatible with a switching point very close tothe low voltage supply) and on the other hand it gives a linearitycomparable to a class AB amplifier thanks to the smooth han-dover between the two output power stages.

ACKNOWLEDGMENT

The authors want to thank Francesco Rezzi and GiovanniCesura for helpful discussions and suggestions.

REFERENCES

[1] D. Self, Audio Power Amplifier Design Handbook, 4th ed. Oxford,U.K.: Newnes-Elsevier, 2006.

[2] R. van der Zee, “High Efficiency Audio Power Amplifiers: Designand Practical Use,” 1999 [Online]. Available: www.ub.utwente.nl/web-docs/el/1/t000000d.pdf

[3] R. Becker and W. H. Groeneweg, “An audio amplifier providing up to1 watt in standard digital 90-nm CMOS,” IEEE J. Solid-State Circuits,vol. 41, no. 7, pp. 1648–1653, Jul. 2006.

[4] G. Palumbo and S. Pennisi, “High-frequency harmonic distortion infeedback amplifiers: Analysis and applications,” IEEE Trans. CircuitsSyst. I, vol. 50, no. 3, pp. 328–340, Mar. 2003.

[5] R. Eschauzier and J. Huijsing, Frequency Compensation Techniquesfor Low-Power Operational Amplifiers. Boston, MA: Kluwer, 1995.

[6] W. C. M. Benirie, K. J. de Langen, and J. H. Huijsing, “Parallel feed-forward class-AB control circuits for low-voltage bipolar rail-to-railoutput stages of operational amplifier,” Analog Integrated Circuits andSignal Processing, vol. 8, pp. 37–48, 1995.

[7] V. Dhanasekaran, J. Silva-Martinez, and E. Sanchez-Sinencio, “Designof three-stage class-AB 16 Ohm headphone driver capable of handlingwide range of load capacitance,” IEEE J. Solid-State Circuits, vol. 44,no. 6, pp. 1734–1744, Jun. 2009.

[8] P. Bogner, H. Habibovic, and T. Hartig, “A high signal swing class ABearpiece amplifier in 65 nm CMOS technology,” in Proc. ESSCIRC,2006, pp. 372–375.

[9] “Low-Power, Low-Offset, Dual Mode, Class H DirectDrive Head-phone Amplifier, Rev. 1” Maxim, Jun. 25, 2010 [Online]. Available:http://datasheets.maxim-ic.com/en/ds/MAX97200.pdf, Mar. 2010,accessed on Jun. 25, 2010

[10] “Class-G Directpath Stereo Headphone Amplifier,” Texas Instruments,Inc. [Online]. Available: http://focus.ti.com/lit/ds/symlink/tpa6141a2.pdf, Mar. 2009, accessed on Jul. 7, 2009

[11] “Class G Headphone Amplifier With I2C Volume Control,” NationalSemiconductor [Online]. Available: http://www.national.com/ds/LM/LM48824.pdf, Aug. 31, 2009, accessed on Jan. 25, 2010,

[12] G. Pillonet et al., “A 0.01% THD, 70 dB PSRR single ended class Dusing variable hysteresis control for headphone amplifiers,” in Proc.ISCAS, 2009, pp. 1181–1184.

[13] B. Ahuja, “An improved frequency compensation technique for COMSoperational amplifiers,” IEEE J. Solid-State Circuits, vol. 37, no. 9, pp.1077–1084, Sep. 1990.

Alex Lollio was born in Lovere, Italy, in 1983. Hereceived the M.Sc. degree in microelectronic engi-neering from the University of Pavia, Italy, in 2007.Currently he is pursuing the Ph.D. degree at Univer-sity of Pavia. His research interests are in high-effi-ciency power amplifiers for mobile applications. Heis currently working as an intern with Marvell Italia.

Giacomino Bollati was born in Castel San Giovanni,Italy, in 1970. He received the electronic engineeringdegree from the University of Pavia, Pavia, Italy, in1995.

In the same year, he joined STMicroelectronics,Cornaredo, Italy, where he worked on the design ofmany blocks of read/write channel ICs for hard diskdrive. In 2002, he moved to the research group ofSTMicroelectronics, Pavia, where he designed someblocks of the preamp for hard disk drive. In 2006,he joined Marvell, Pavia, where he has been mainly

working on power amplifiers for portable applications.

Rinaldo Castello (S’78–M’78–SM’92–F’99) grad-uated from the University of Genova (summa cumlaude) in 1977 and received the M.S. and Ph.D. de-grees from the University of California at Berkeley in1981 and 1984.

From 1983 to 1985 he was a Visiting Assistant Pro-fessor at the University of California at Berkeley. In1987 he joined the University of Pavia, where he isnow a Full Professor. He consulted for STMicroelec-tronics, Milan, Italy, until 2005, and from 1998 to2005 was the Scientific Director of a joint research

center between the University of Pavia and STMicroelectronics. He promotedthe establishment of several design centers from multinational IC companies inthe Pavia area, among them Marvell, for which he has been consulting since2005.

Dr. Castello has been a member of the TPC of the European Solid StateCircuits Conference (ESSCIRC) since 1987 and of the IEEE InternationalSolid State Circuit Conference (ISSCC) from 1992 to 2004. He was TechnicalChairman of ESSCIRC’91 and General Chairman of ESSCIRC’02, AssociateEditor for Europe of the IEEE JOURNAL OF SOLID-STATE CIRCUITS from 1994to 1996 and Guest Editor of the July 1992 special issue. From 2000 to 2007 hewas a Distinguished Lecturer of the IEEE Solid-State Circuits Society. He wasnamed one of the outstanding contributors for the first 50 years of the ISSCC.He was a corecipient of the Best Student Paper Award at the 2005 Symposiumon VLSI.

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A Class-G Headphone Amplifierin 65 nm CMOS Technology

Alex Lollio, Giacomino Bollati, and Rinaldo Castello, Fellow, IEEE

Abstract—This paper presents a class G amplifier based on a lowdistortion switching principle technique called switching currentsinjection. The switching circuit enables a very smooth handoverbetween the voltage supply rails obtaining both high efficiency andlow distortion. An approach for the evaluation of the switching dis-tortion in a class G amplifier (and the ability of the loop to reject it)is proposed and the results obtained are used to optimize the overalldistortion after compression by the feedback loop. The integrated65 nm CMOS class G headphone driver based on the above con-cept operates from 1.4 V and 0.35 V supplies. At low powerlevel it uses almost exclusively the low voltage supply reducing thedissipation to 1.63 mW @ ���� � 0.5 mW into 32 �. At higherpower level, where both supplies are used, the smooth transitionbetween the rails allows a ��� � � better than 80 dB for���� 16 mW into 32 �. The SNR is 101 dB, quiescent poweris 0.41 mW and active die area is 0.14 mm�.

Index Terms—Class G amplifier, audio amplifier, efficiency, lin-earity, power amplifier, headphone driver, low power consumption.

I. INTRODUCTION

M ODERN cellular phones incorporate hands-free oper-ation, MP3 music playback and DMB reception. The

users may wish to activate these features for many hours and alow efficiency amplifier could deplete the battery in a short time.There are two classes of power amplifiers generally used for thisapplication: Class-D and Class-AB. Class-D architectures pro-vide the benefit of power efficiency at the cost of slightly re-duced performance (especially noise and distortion) and a levelof switching noise, which might, in some cases, interfere withRF functions such as mobile phone, GPS or FM radio reception.Class AB architecture has the benefit of higher audio quality anddoes not produce any switching noise, but its power efficiencyis much lower. Notwithstanding their lower efficiency, the greatmajority of the headphone drivers on the market today operatein Class AB mode.

A class G is an analog amplifier having an efficiency compa-rable to that of a class D (without EMI problems) and a linearitycomparable to that of class AB. Fig. 1(a) shows a schematicblock representation of a class G amplifier. It uses two voltagesupply rails (VHV is the high voltage rail and VLV is the low

Manuscript received April 21, 2010; revised July 12, 2010; accepted Au-gust 19, 2010. This paper was approved by Guest Editor Gyu-Hyeong Cho.This work was supported by the Italian National Program FIRB, under Con-tract RBAP06L4S5.

A. Lollio and R. Castello are with the Dipartimento di Elettronica, Universitàdegli Studi di Pavia, 27100 Pavia, Italy (e-mail: [email protected]).

G. Bollati is with Marvell Semiconductors, Pavia 27100, Italy.Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/JSSC.2010.2076450

voltage rail) and switches to the appropriate supply as requiredby the instantaneous output voltage level. In this way, it neveruses the high supply voltage when a low voltage output is re-quired which would waste power [1]. The core of a class G am-plifier is the switching circuitry, which should enable a smoothhandover of the load driving between the lower voltage supplyand the higher one. The switching point is defined as the outputvoltage level where the amplifier switches from one supply tothe other. In this design we define two switching point levelscalled VLV-VTH and , where VLV is the valueof the amplifier low voltage supplies and VTH is a thresholdvoltage (see Fig. 1(b)). The switching strategy should satisfytwo key points: first, the distortion due to the switching opera-tion must be minimized to maintain high audio quality; second,the switching point must be as close as possible to the lowvoltage supply (VLV) to maximize efficiency (this means thatVTH must be as low as possible). This paper is organized asfollows. Section II shows general design considerations aboutthe class G amplifier design, Section III introduces the principleof the new switching technique and the class G amplifier model,Section IV highlights the switching speed restriction, Section Vshows the amplifier architecture and finally Section VI gives theexperimental results. Conclusions are given in Section VII.

II. CLASS G DESIGN CONSIDERATIONS

There are two basic ways in which class G amplifiers are re-alized [2]: the “series” implementation (shown in Fig. 2(a)) andthe “parallel” implementation (shown in Fig. 2(b)). Thanks toits simplest switching circuit, the most common implementa-tion is the series one. It uses a single output stage connectedto both the low voltage and to the high voltage supply rails re-spectively through diodes and switches. The main limitation ofthe series topology is due to the diodes in series with the lowvoltage supply that make this implementation unsuitable for lowvoltage application. In fact, the turn-on voltage of the diode putsa strong limitation both on the minimum value of VLV and onthe switching point distance from VLV.

On the other hand, in the parallel topology, shown in Fig. 2(b),there are two output stages working in parallel and there isnothing between the power transistors and the supplies. This factposes no constraints on the minimum value of VLV and allowsplacing the switching point very close to VLV, giving higher ef-ficiency. This is shown in Fig. 3(a) in which the efficiency ofa class G amplifier is plotted versus output power for differentswitching point levels and compared with that of a class AB ableto handle the same maximum power.

The core of the parallel topology is the switching circuitwhich must simultaneously enable low distortion and high

0018-9200/$26.00 © 2010 IEEE

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Fig. 1. Class G amplifier: simplified block diagram (a) and output voltage versus time with the supply voltages and the switching point level (b).

Fig. 2. Class G topologies: serial (a) and parallel (b).

efficiency. If the output voltage of the class G amplifier isbelow the switching point level, the ratio between the efficiencyof the class G and the class AB is approximately equal to theratio between the value of the high and low supplies:

(1)

Music has a large peak-to-average power ratio which can varyfrom 10 dB for compressed rock to 30 dB for classical music[3]. This implies that the output power is below the peak levelfor most of the time. As a consequence power efficiency canimprove significantly taking advantage of class-G operation.

Fig. 3(a) shows the strong impact of the switching point levelon the efficiency. The switching point should be set as close aspossible to the low voltage supply VLV (ideally VTH should beequal to zero). However, if VTH is too small, the power transis-tors supplied by the low voltage rail have to work in deep trioderegion for a significant portion of time affecting the total har-monic distortion (THD) of the amplifier as shown in Fig. 3(b).The value of VTH needs to be chosen as a trade off between ef-ficiency and linearity.

In this work a class G parallel topology, which implementsa novel switching principle approach based on a switching cur-rent injection, is presented. The proposed switching principleenables very low distortion (better than dB) despite the

switching point beings only 50 mV away from the low voltagesupply ( mV).

III. CLASS G SWITCHING PRINCIPLE

The goal in a class G amplifier design is to find a switchingprinciple which maximizes the efficiency and limits the dis-tortion introduced by the switching operation. In this Sectionthe switching circuit proposed and its effects on the amplifierlinearity are presented. Using a simple 2 stages model we willstudy the distortion introduced by the switching circuit andthe capability of the loop to reject it. In order to simplify thediscussion, the class G amplifier (based on a parallel topology)is derived from a class A amplifier. The obtained conclusionscan, however, be easily extended to a push-pull class AB outputstage. The following equation describes the low frequencyinput-output transfer function of the two stages class A ampli-fier shown in Fig. 4(a):

(2)

Starting from this class A amplifier we want to build a simpleclass G one which switches from one supply rail to the other one.To do this, let us start to split transistor M3 into two transistorsM3L and M3H as shown in Fig. 5(a). The input-output transferfunction is given by the following equation:

(3)

where gm3L(Vo) and gm3H(Vo) represent the transconductanceof the low and high voltage output stages as a function of theoutput voltage (as long as the load in the band of interest ispurely resistive the dependence of gm3 on output current trans-late in a dependence on the output voltage).

Let us first suppose to implement an ideal switching betweenthe output stages in such a way that the switching operation doesnot introduce any extra distortion. This is obtained if the totalequivalent transconductance of the output stages of the circuitshown at the top of Fig. 5(a) given byis equal to the transconductance gm3(Vo) shown in Fig. 4(b). Ina real implementation this condition is difficult to satisfy, how-ever, it will be used only to derive the linear model shown at theend of this section and the analysis carried out on this simplifiedmodel, will shows that the sensitivity of the switching distor-tion to variations of the gm3 value is very low. Furthermore, thetwo output stages have the same topology making not difficult

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Fig. 3. Class G efficiency (a) and the total harmonic distortion versus the output power at different switching point level (b).

Fig. 4. Simple class A amplifier (a) and plot of the output stage transconductance versus the output voltage (b).

Fig. 5. Class G output stage with the switching circuit (a) and graphical relation between gm3L, gm3H, IJL and IJH versus the output voltage.

to keep the variation of gm3 during switching smaller than thatdue to the output current variation (typically the main source of

nonlinearity in a class AB amplifier). It will be shown that thedifference between the simulated behavior of the real amplifier

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connected in unity gain configuration as shown in Fig. 7(a) andthe model is acceptably small.

A possible behavior of gm3L and gm3H as a function ofthe output voltage that satisfy the ideal condition

is described in Equations (4) and (5),shown at the bottom of the page, whereand represent two voltage levels such thatthe switching point is in the middle betweenthem. The output voltage range is where the switching oper-ation takes place. The expression defines how the valueof gm3L evolves during switching and, for our purposes, doesnot need to be explicitly known.

Fig. 5(b) shows a graphical representation of these equa-tions where it can be immediately seen that

. Unfortunately this ideal situationcannot be realized in practice because the handover betweenone stage and the other requires an additional circuit able toforce such a transition. Fig. 5(a) shows this circuit which isimplemented as a differential pair that compares the outputvoltage to the switching point voltage . Thedifferential pair sends its bias current, IBIAS, either to the gateof M3L or to the gate of M3H according to the result of thecomparison. The value of IBIAS and the transconductance ofthis differential pair determine the speed of the transition.

Let us assume that gm3L and gm3H still have the expressionwritten in (4) and (5). In a similar way we can write the equations(6)-(7), shown at the bottom of the page, representing the currentIJL injected into the gate of M3L and the current IJH injectedinto the gate of M3H: The expression defines how thevalue of gm3H evolves during switching and, as , doesnot need to be explicitly known.

Fig. 6. Amplifier model of Fig. 5(a) used to analyze the switching distortion.

Fig. 5(b) shows a graphical representation of the switchingparameters (transconductances and currents) versus the outputvoltage. From the simple class G implementation of Fig. 5(a)we obtain the following input-output characteristic:

(8)

If we combine the (4)–(8) we obtain the following relation:

(9)

where is as shown in (10) at the bottom of the page.It is interesting to note that the input-output transfer functionfor the model shown in Fig. 6 is the same as that expressedby (9). This means that it is possible to model the distortion

(4)

(5)

(6)

(7)

(10)

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Fig. 7. Class G amplifier closed in a unity gain feedback loop (a) and the simulated parameters versus time (b).

introduced by the switching circuit with a current source (con-nected to the input of the last stage of the linear circuit of Fig. 6)that injects an unwanted signal at the harmonics of the input.This is consistent with what is done in literature [4] to modelthe nonlinearity due to the last stage of a class AB amplifier.Such a model will be used to understand the dependence of theswitching distortion on the circuit parameters in order to opti-mize the overall class G amplifier performance. Fig. 7(a) showsthe real class G amplifier connected in a unity gain feedbackconfiguration while Fig. 7(b) shows the time domain represen-tation of the output voltage and some key currents all obtainedthrough simulation. A design target is to size the two outputstages to minimize the variation dueto switching as shown in Fig. 5(b), nonetheless the circuit ofFig. 7(a) has been intentionally sized to have a significant vari-ation of (as shown in Fig. 7(b)). Thiswas done to show that this is not a strict requirement for themodel to remain valid as confirmed by the simulated resultsshown later in this section.

Using the model of Fig. 8(a), the relation between the injectedcurrents and the output voltage can be computed obtaining thefollowing expression:

(11)

Assuming and (11) becomes:

(12)

Equation (12) expresses the ability of the amplifier to reject theswitching distortion. The closed loop residual distortion is in-

versely proportional to gm2 and directly proportional to IBIAS(since is proportional to IBIAS). In headphone application, theamplifier bandwidth of a two stage amplifier is approximatelygiven by gm2/CM and needs to be much higher than the signalbandwidth (20 kHz). This means that the distortion introducedby the switching circuit is, to first order, insensitive to the valueof CM, gm3 and RL. The result is quite different from the re-jection of the distortion due to the output stage (that is the mainsource of distortion in a class AB stage). In fact, in this case,the distortion can be modeled as a current source, ,connected to the output node of the amplifier [4] (see Fig. 8(b)).The transfer function from to Vo can be calculated andsimplified assuming:

The result is given in (13):

(13)

To minimize distortion in a class AB, gm3 needs to be thehighest allowed by power consumption constraints and theclosed loop bandwidth needs to be the highest allowed bystability requirements. Equation (13) does not give constraintson the absolute values of gm2 and CM but only on their ratio.Equation (12), instead, shows that the ability of the loop toreject switching distortion is directly proportional to the abso-lute value of gm2. The requirement of an high gm2 value hasnegligible effect on the power consumption but forces to usea compensation capacitor CM much bigger than the one thatcould be used in a class AB amplifier with a significant increasein silicon area.

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Fig. 8. Amplifier model of Fig. 7(a) used to analyze the amplifier rejection to the switching distortion (a), and amplifier model used to analyze the amplifierrejection to the last stage nonlinearity (b).

Fig. 9. Comparison between the simulated THD and the model of Fig. 8(a).

We have simulated the THD of the simplified class G ampli-fier for a 1 kHz input signal with 400 mV peak to peak ampli-tude centered around mV. The simulations were carriedout under the following operating conditions V,

V mV and assumingthe following parameter values A/V, cm pF,

Ohm, A, mA/V (at DCpoint).

We have chosen a switching point relatively far from the lowvoltage supply ( mV). This was done to insure thatthe overall distortion is primarily caused by the switching oper-ation. In this way we are able to validate the model of Fig. 8(a).On the other hand, if the switching point is chosen very closeto the low voltage supply (i.e., VTH close to zero), the distor-tion caused by the nonlinearity of the last stage becomes dom-inant. Fig. 9 shows the dependence of THD on various designparameter values (IBIAS, gm2, RL, CM). The plots display bothsimulated results and analytical calculation obtained using (12).The expression for the current Ij (necessary to calculate the ab-solute value of the distortion for the model of Fig. 8(a)) has notbeen analytically derived. Instead, the first calculated value ofeach plot has been taken equal to the simulation result obtainedfrom the circuit of Fig. 7(a) and the others have been calculatedstarting from these points. It can be seen how the simulation re-sults validated the equations derived from the model of Fig. 8(a).

In particular the plot of THD as a function of CM shows that,as predicted by (12) switching distortion is independent fromthe CM value. This is different from what happens to the outputstage distortion (predicted by (13)).

IV. SWITCHING SPEED LIMITATION

In the previous Section it has been shown that the distor-tion introduced by the switching circuit is proportional to theswitching current IBIAS. Therefore, to achieve high linearityIBIAS should be taken as small as possible while still insuringproper operation. The first limit to the minimum usable value forIBIAS is determined by matching requirements. For the ampli-fier of Fig. 7(a) a mismatch associated with the pMOS transis-tors in the top mirrors causes an error current which appear at thesame points as the injected switching current. If the switchingcurrent value (IBIAS) is smaller than the maximum equivalentmismatch current of the pMOS transistors, the switching circuitmay not be able to switch on and off the output stages as re-quired to implement class G operation.

The second potential limit to the minimum value of IBIASis defined by the switching speed requirements. This limit cansignificantly affect the amplifier linearity, and, for this reason, acircuit which overcomes the problem has been introduced.

The speed limitation is due to the fact that the output MOStransistor M3L is switched off by pulling down its gate with the

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Fig. 10. Class G amplifier schematic including the hard switching circuit (a) and the output currents versus time using or not the hard switching (b).

small current IBIAS. Since the capacitive load at this gate issignificant (being the sum of the gate capacitance of M3L andof the Miller capacitance CM) the switching time can be verylong.

Also, M3L needs to be switched off when the output voltageis close to the switching point i.e., when it is delivering its max-imum current and its gate voltage is close to VHV. Further-more, in order to keep M3L off even when the output voltageapproaches its gate should be pulled all the way downto . In fact, if this is not the case, the terminal of M3L,connected to the output, starts to behave as a source and a crossconduction current can flow from to .

Due to all the above constraints the required voltage variationon the gate of M3L and the corresponding switching time arerelated by the following equation:

(14)

The minimum allowable value for in which the switchingmust be completed (no cross conduction) is given by the timeduring which the output voltage at the maximum audio fre-quency (20 kHz) goes from to . Fig. 1(b)shows a graphical representation of the minimum allowablevalue for the time interval while (15) gives its value:

(15)

Combining (14) and (15) it is possible to obtain an expressionfor the minimum allowed switching current (IBIAS):

(16)

This represents the minimum value for IBIAS which still ensurea correct switching operation in the worst case condition thatcorrespond to the maximum gate voltage swing

and maximum output voltage slope (i.e., maximumsignal frequency and maximum output signal amplitude VHV).

For this design, (16) suggests a value of IBIAS of 40 A thatis much higher than the value necessary to satisfy the matchingrequirements (1 A).

In order to use a value of IBIAS smaller than the one re-quired using (16), which means less distortion, we have im-plemented a hard switching circuit which immediately switchesoff M3L when the output voltage falls below the negative lowvoltage supply . Fig. 10(a) shows the implementationof the class G amplifier including such hard switching circuitwhich is made up by a comparator and a switch (realized usingan nMOS transistor). If the output voltage Vo is higher than

the switch is open and the amplifier works as describedin the previous section. When Vo falls below the switchis turned ON hard by the comparator and the gate of M3L isimmediately connected to the output node Vo forcing the gate-source voltage of M3L to be equal to zero. The hard switchingcircuit does not introduce any additional distortion because itacts when the VDS of M3L is equal to zero i.e., when M3Lis not contributing any current to the output. The plot at thetop of Fig. 10(b) shows the output currents without the hardswitching circuit assuming a small IBIAS value (used to re-duce switching distortion). A current glitch flows between thesupplies ( and ) when the output voltage crossesthe switching point. This current means wasted power and has anegative impact on the overall distortion. The plot at the bottomof Fig. 10(b) shows that the glitches have been removed. How-ever, the limited speed with which the gate of M3L can be turnedON (that still depends only on IBIAS/ since thehard switching circuit is of no help) affects the shape of the

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Fig. 11. Amplifier architecture: a three stage opamp with a detail on the last stage compensation approach.

output currents that appear to be nonsymmetric. These nonsym-metrical output currents only slightly affect the linearity (even athigh frequency) and the efficiency and they have been acceptedin this design. As a consequence the value of IBIAS has beendefined only by matching requirements. To minimize the am-plitude of current glitches on the output node the comparatorshave been designed to have a rise/fall time smaller than 10 usand an offset smaller than 5 mV. The residual offset does notaffect significantly the linearity because the harmonics fall out-side the audio bandwidth.

V. AMPLIFIER ARCHITECTURE

The implemented class G headphone driver uses a differentialinput and single ended output topology. The number of stagesto be used depends on the linearity requirements: three stagesare enough to satisfy the target THD of dB at 1 kHz.

Fig. 11 shows the chosen architecture. The amplifier mainpath is composed of three stages compensated using the nestedMiller techniques [5]. In order to save quiescent power con-sumption, the last stage gm3 is compensated using an active-feedback compensation technique [13] as shown in Fig. 11. Thefirst stage, gm1, drives two parallel paths. One is made up by thecascade of gm2 and gm3L and the other one by the cascade ofgm2 and gm3H. The switching stage alternatively enables oneof these two parallel paths according to the output voltage levelrelative to the threshold level. Only the gm3L stage is suppliedby the low voltage rail VLV while the rest of the circuit is sup-plied by the high voltage rail VHV.

Fig. 12 shows a somewhat simplified transistor level imple-mentation of the amplifier. The first stage, gm1, is a conven-tional pMOS differential pair that also implements the differen-tial to single ended conversion. The second stage is made up bythe nMOS transistor M2 that drives a pMOS current mirror withone input and two pairs of output. The floating battery, shownin Fig. 12, is a circuit used to control the quiescent bias currentof the push-pull low voltage output stage, gm3L [6]. The com-plete output stage is composed by two push-pull class AB paths

working in parallel (for simplicity, in the previous sections onlythe pull-down part was shown). The switching principle is thesame as the one reported in the previous section. The switchingcircuit is composed by two differential pairs: one of them actson the nMOS power transistors and the other one acts on thepMOS power transistors. For simplicity the hard switching cir-cuit has not been shown: it is built with two comparators and twoswitches which rapidly switch off the nMOS and pMOS lowvoltage power transistors when the output voltage falls below

or rise above VLV.Switching Distortion Analysis: The switching distortion

analysis that was carried out in Section III for the case of atwo stages amplifier can be easily extended to a three stagetopology. Fig. 13 shows the simplified linear model corre-sponding to this case.

The transfer function from the switching current to the outputis given by

(17)

Where is the closed loop dBangular frequency of the amplifier that, in this design, is muchhigher than the signal bandwidth krad/s versusan audio bandwidth of kHz). Moreover, for stabilityreasons, has been chosentwice as high as . It follow that (17) can be approximated by(18) with very good accuracy.

(18)

The simple relation reported in (18) expresses with good ap-proximation the ability of the used three stage amplifier to rejectthe unwanted current injection Ij associated with the switchingcircuit. From (18) we can see that the amount of switching dis-tortion compression operated by the amplifier is proportional tothe value of gm2 as in the case of a two stages amplifier.

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Fig. 12. Transistor level implementation of the class G opamp.

Fig. 13. Simplified model of the class G amplifier shown in Fig. 12.

As for the simpler two stage amplifier of Section II the THDof the complete amplifier has been obtained via simulation ap-plying a 1 kHz 600 mVpp tone centered at 0 V at its input underthe following operating conditions V,V and assuming the following parameters A/V,

A/V, mA/V (simulated in DC oper-ating point), pF, pF. Again the switchingpoints have been chosen far from the low voltage supply VLV( mV) to avoid saturation effects of the low voltagestage.

Following the same procedure described in Section III themodel of Fig. 13 has been validated evaluating the distortion

sensitivity to the key circuit parameters and comparing the re-sults with the simulations on the real circuit. Fig. 14 shows thatthe comparison results validate the expression given by (18).

VI. EXPERIMENTAL RESULTS

To achieve a high integration level, placing the headphoneamplifier on the same die with the baseband processor would beadvantageous. In this case the digitally intensive nature of theprocessor forces the usage of a deeply scaled CMOS technology,such as 65 nm or below.

The prototype class G amplifier reported here (designed towork using a high voltage supply V and a lowvoltage supply V) has been realized using the 1.8V devices available in 65 nm CMOS. For reliability reasons notransistor should see (even during transients) a gate to sourceand gate to drain voltage that exceed the maximum value al-lowed by the process. Since the amplifier output voltage swingsfrom V to 1.4 V, the 1.8 V output transistors need to becascaded and the biasing circuit should be carefully designedto ensure that no device is stressed beyond its limit even duringpower on/off transients.

The die micrograph is shown in Fig. 15 and corresponds to asilicon area of 0.14 mm per channel. We have integrated bothaudio channels. Table I shows the values of gm’s in the threestages and that of the compensation capacitors. CM2 representsthe value of each compensation capacitors used across the fouroutput transistors: this means that the total capacitance is fourtimes the CM2 reported. As explained in Section III the area

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Fig. 14. Comparison between the simulated THD of the class G opamp of Fig. 12 and the model of Fig. 13.

Fig. 15. Die micrograph.

occupied is much bigger than the area necessary to compensatea class AB amplifier.

The switching point has been set only 50 mV away from thelow voltage supplies making it possible to scale VLV down to0.35 V while still having good efficiency up to an output powerof 1.5 mW on a 32 load. Fig. 16 shows the efficiency andthe Signal to Noise Distortion Ratio versus theoutput power that displays the classical nonmonotonic behaviorof class G amplifiers, measurements have been performed usingan A-weighted filter. Better than 30% efficiency is achievedfrom mW to the maximum deliverable outputpower of 30 mW, for a 1 kHz tone is better than 80 dBin the entire operating range and reaches dB just below thepower level for which class G operation begins to occur at thesignal peaks. As expected, beyond this point the plotshows a slight degradation (a step of about 6 dB occurs at the

TABLE ITABLE OF GM’S AND CURRENTS IN THREE STAGES

AND COMPENSATION CAPACITORS

output amplitude corresponding to the switching point). Fig. 17shows the power dissipation versus the delivered output power(per channel). A key target for a headphone driver is to mini-mize the power dissipation when the delivered output power is0.1 mW and 0.5 mW into a 32 load. This is because suchpower levels define the range of operation of a typical headsetspeaker used to reproduce MP3 audio signals. In those condi-tions, the proposed driver dissipates much less than today stateof the art circuits [7]–[12]. When the output power is below 1.5mW the amplifier uses only the low voltage stage thanks to thelow VTH used and the power dissipation is less than 3 mW asshown in Fig. 17. To deliver an output power exceeding 1.5 mWrequires also the use of the high voltage stage. As shown by the

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Fig. 16. Total harmonic distortion and efficiency versus the output power.

Fig. 17. Amplifier power consumption versus the delivered output power.

plot from this point on the power dissipation increases at a muchhigher rate with the delivered power.

Fig. 18 shows a plot of THD versus frequency for two dif-ferent output power levels (2 mW and 5 mW). In both casesdistortion increases with frequency up to kHz (abovethis frequency distortion appears to decrease because THD hasbeen evaluated only in the signal band integrating both noiseand harmonics up to 20 kHz). In the frequency range of interestthe maximum THD degradation with respect to low frequencyis only 10 dB and this is a very good result for a class G ampli-fier [10], [11].

In Fig. 19 the output spectra at two different output powerlevels are shown. In Fig. 19(a) the output power is 1 mW (thislevel is below the switching threshold and the amplifier worksalways in class AB) producing a very clean spectrum. On theother hand, in Fig. 19(b) the output power is 20 mW. In thiscondition the amplifier uses both the output stages (class G op-eration) and the spectrum includes also the harmonic distortion

Fig. 18. Total Harmonic Distortion versus frequency.

introduced by the switching operation. In both cases, the distor-tion is dominated by the second harmonic.

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Fig. 19. Output spectra at two load power levels.

TABLE IICLASS G PERFORMANCE SUMMARY COMPARED WITH RECENT PAPERS

This work has been compared with class AB, D, H, andG amplifiers reported in technical literature or in commercialdatasheets. In Table II the performance summary of the am-plifier and a comparison with class AB and D amplifiers takenfrom technical literature is shown. In this table the problemof the supply voltage generation is not considered. For a fairreading of this table, it must be taken into account that the classG amplifier, compared with class AB and D amplifiers, needsan additional supply rail . The negative high voltagesupply, instead, is widely used to avoid external decouplingcapacitor (whose linearity is a limit for the audio quality).

The quiescent power consumption is 0.41 mW which is 3times less than the lowest reported. The peak deliverable poweronto a 16 Ohms load is 90 mW. The total harmonic distortionis 80 dB when the delivered output power is 16 mW. The signalto noise ratio (A-weighted) is 101 dB.

Table III shows the performance summary compared withrecent class H and G commercial products. Unfortunately thedatasheets do not give the performance of the stand alone am-plifier. For example, [9] includes the power consumption of twocharge pumps while [10], [11] include power consumption ofone charge pump and one buck converter. The buck converter isused to generate VLV starting from VHV and the charge pumps

are used to generate the negative supply voltages and. In order to make a fair comparison the power consump-

tion of the charge pumps and of the buck converter need to beestimated.

Conservative power estimation for the two inverting chargepumps, with 2.5 Ohm of series resistance, is 0.6 mW (0.3 mWper channel). This power is fairly independent from the deliv-ered current. On the other hand Buck converter efficiency in-creases with the delivered current. We assumed quite a low ef-ficiency that should be easily achievable: 50% when deliveringthe quiescent current (0.4 mA) resulting in 0.1 mW power dissi-pation and 70% when the output power is between 0.1 mW and0.5 mW. Table III shows the overall power consumption of thereported class G amplifier taking into account also the contribu-tion of the charge pumps and the buck.

VII. CONCLUSION

A novel class G switching technique based on current injec-tion has been presented and a simple linear model of the classG amplifier, that allows to evaluate the compression operatedby the loop on the switching distortion has been proposed. Themain goal of this work was to achieve high efficiency while min-imizing linearity degradation due to the switching operation.

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TABLE IIICLASS G PERFORMANCE SUMMARY COMPARED WITH RECENT COMMERCIAL PRODUCTS

The proposed architecture achieves on the one hand high effi-ciency (being compatible with a switching point very close tothe low voltage supply) and on the other hand it gives a linearitycomparable to a class AB amplifier thanks to the smooth han-dover between the two output power stages.

ACKNOWLEDGMENT

The authors want to thank Francesco Rezzi and GiovanniCesura for helpful discussions and suggestions.

REFERENCES

[1] D. Self, Audio Power Amplifier Design Handbook, 4th ed. Oxford,U.K.: Newnes-Elsevier, 2006.

[2] R. van der Zee, “High Efficiency Audio Power Amplifiers: Designand Practical Use,” 1999 [Online]. Available: www.ub.utwente.nl/web-docs/el/1/t000000d.pdf

[3] R. Becker and W. H. Groeneweg, “An audio amplifier providing up to1 watt in standard digital 90-nm CMOS,” IEEE J. Solid-State Circuits,vol. 41, no. 7, pp. 1648–1653, Jul. 2006.

[4] G. Palumbo and S. Pennisi, “High-frequency harmonic distortion infeedback amplifiers: Analysis and applications,” IEEE Trans. CircuitsSyst. I, vol. 50, no. 3, pp. 328–340, Mar. 2003.

[5] R. Eschauzier and J. Huijsing, Frequency Compensation Techniquesfor Low-Power Operational Amplifiers. Boston, MA: Kluwer, 1995.

[6] W. C. M. Benirie, K. J. de Langen, and J. H. Huijsing, “Parallel feed-forward class-AB control circuits for low-voltage bipolar rail-to-railoutput stages of operational amplifier,” Analog Integrated Circuits andSignal Processing, vol. 8, pp. 37–48, 1995.

[7] V. Dhanasekaran, J. Silva-Martinez, and E. Sanchez-Sinencio, “Designof three-stage class-AB 16 Ohm headphone driver capable of handlingwide range of load capacitance,” IEEE J. Solid-State Circuits, vol. 44,no. 6, pp. 1734–1744, Jun. 2009.

[8] P. Bogner, H. Habibovic, and T. Hartig, “A high signal swing class ABearpiece amplifier in 65 nm CMOS technology,” in Proc. ESSCIRC,2006, pp. 372–375.

[9] “Low-Power, Low-Offset, Dual Mode, Class H DirectDrive Head-phone Amplifier, Rev. 1” Maxim, Jun. 25, 2010 [Online]. Available:http://datasheets.maxim-ic.com/en/ds/MAX97200.pdf, Mar. 2010,accessed on Jun. 25, 2010

[10] “Class-G Directpath Stereo Headphone Amplifier,” Texas Instruments,Inc. [Online]. Available: http://focus.ti.com/lit/ds/symlink/tpa6141a2.pdf, Mar. 2009, accessed on Jul. 7, 2009

[11] “Class G Headphone Amplifier With I2C Volume Control,” NationalSemiconductor [Online]. Available: http://www.national.com/ds/LM/LM48824.pdf, Aug. 31, 2009, accessed on Jan. 25, 2010,

[12] G. Pillonet et al., “A 0.01% THD, 70 dB PSRR single ended class Dusing variable hysteresis control for headphone amplifiers,” in Proc.ISCAS, 2009, pp. 1181–1184.

[13] B. Ahuja, “An improved frequency compensation technique for COMSoperational amplifiers,” IEEE J. Solid-State Circuits, vol. 37, no. 9, pp.1077–1084, Sep. 1990.

Alex Lollio was born in Lovere, Italy, in 1983. Hereceived the M.Sc. degree in microelectronic engi-neering from the University of Pavia, Italy, in 2007.Currently he is pursuing the Ph.D. degree at Univer-sity of Pavia. His research interests are in high-effi-ciency power amplifiers for mobile applications. Heis currently working as an intern with Marvell Italia.

Giacomino Bollati was born in Castel San Giovanni,Italy, in 1970. He received the electronic engineeringdegree from the University of Pavia, Pavia, Italy, in1995.

In the same year, he joined STMicroelectronics,Cornaredo, Italy, where he worked on the design ofmany blocks of read/write channel ICs for hard diskdrive. In 2002, he moved to the research group ofSTMicroelectronics, Pavia, where he designed someblocks of the preamp for hard disk drive. In 2006,he joined Marvell, Pavia, where he has been mainly

working on power amplifiers for portable applications.

Rinaldo Castello (S’78–M’78–SM’92–F’99) grad-uated from the University of Genova (summa cumlaude) in 1977 and received the M.S. and Ph.D. de-grees from the University of California at Berkeley in1981 and 1984.

From 1983 to 1985 he was a Visiting Assistant Pro-fessor at the University of California at Berkeley. In1987 he joined the University of Pavia, where he isnow a Full Professor. He consulted for STMicroelec-tronics, Milan, Italy, until 2005, and from 1998 to2005 was the Scientific Director of a joint research

center between the University of Pavia and STMicroelectronics. He promotedthe establishment of several design centers from multinational IC companies inthe Pavia area, among them Marvell, for which he has been consulting since2005.

Dr. Castello has been a member of the TPC of the European Solid StateCircuits Conference (ESSCIRC) since 1987 and of the IEEE InternationalSolid State Circuit Conference (ISSCC) from 1992 to 2004. He was TechnicalChairman of ESSCIRC’91 and General Chairman of ESSCIRC’02, AssociateEditor for Europe of the IEEE JOURNAL OF SOLID-STATE CIRCUITS from 1994to 1996 and Guest Editor of the July 1992 special issue. From 2000 to 2007 hewas a Distinguished Lecturer of the IEEE Solid-State Circuits Society. He wasnamed one of the outstanding contributors for the first 50 years of the ISSCC.He was a corecipient of the Best Student Paper Award at the 2005 Symposiumon VLSI.