jui-hung chien hao yu ruei-siang hsu hsueh-ju lin shih-chieh chang package geometric aware thermal...
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Jui-Hung Chien
Hao Yu
Ruei-Siang Hsu
Hsueh-Ju Lin
Shih-Chieh Chang
Package Geometric Aware Thermal Analysis by Infrared-Radiation Thermal Images
DATE’14
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Outline
Introduction Preliminaries Efficient Method Of Approximating A
Package-transfer Matrix Experiments Conclusion
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Introduction
In high density integrated circuits, the total power as well as power density can increase dramatically
There are two major difficulties for adopting the package into thermal simulation Thermal analysis tools for chip designers
provide very few choices of package types Accurate modeling of a package thermal
conductance is very difficult
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High-speed infrared radiation (IR) image can provide accurate temperature profiles of a manufactured chip
The proposed methodology builds a matrix, called the package-transfer matrix (PT-matrix) for every two packages
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Contributions
Develop a special matrix, called the package-transfer matrix(PT-matrix) to perform translations of temperature profiles between two packages
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Preliminaries
Thermal simulation of a chip needs to take the package effect into consideration
The widely used standard for modeling temperature profiles of a board level system is JEDEC JESD 51-14 standard
Only the volume of the package and the coverage area of the chip are considered
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Problem Description
To enhance the accuracy of the thermal model for the chip, we add additional thermal resistors, called peripheral thermal resistors.
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We can use the duality of electrical-thermal relationship to solve the steady-state thermal circuit by Kirchhoff’s Circuit Laws (KCL,) Kirchhoff‘s Voltage Law (KVL,) and Branch Constitutive Equations (BCE.)
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There are N grid nodes in the package model of a chip (where N=n×n)
Vector P and T in EQ (1) have N elements to represent the system power and temperature profiles
A is an N × N thermal conductance matrix of which elements represent the meshed thermal resistors of the chip with package.
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In general, PT-matrix PT in EQ(2) is strongly related to the material and structural properties of a die and package but is weakly related to the design in the die
Use IR images of Tpkg2 and the corresponding simulated temperature profiles of Tpkg1 to derive PT-matrix
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There are two challenges to derive PT-matrix need to design a special test chip which allows
us to feed the same power profile into both the simulator and the test chip
obtaining N steady-state temperature profiles is very time-consuming and impractical
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Efficient Method Of Approximating A PT-Matrix
The Special Characteristic of a PT-matrix Two types of grids node
Edge node Non-edge node
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Tpkg2(s) can be expressed as =
from EQ (2) Theorem 1: The element PT(s, t) in a PT-
matrix is zero if grid node t is a non-edge node and grid node s is not equal to grid node t
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Proof: Consider that a power profile P is applied to
two identical chips with two different packages
The difference between Apkg1 and Apkg2 is the peripheral thermal impedance
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Where D is a diagonal matrix with at most N
non-zero elements representing all the heat transfer characteristics of packages
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From EQ (6), we can find that the PT-matrix is related only to the material and structural properties, Apkg2 and D
Element PT(s, t) in PT-matrix
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If grid node t is a non-edge node, then D(i, t) is zero for all i
where grid node t is a non-edge node
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The Approximation of a PT-matrix
Those non-zero elements in a PT-matrix Heat equation with the solution by Green’s
function
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Experiments
The design of the two thermal test chips feed the same power profile into both a test chip
and the simulation model should have the ability to create different
locations of hotspots
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Standard Thermal Test Chip for PT-matrix Establishment(STTC) fabricated by TSMC in 0.18μm technologies, and
the chip size is 5000μm × 5000μm. The package of this chip adopts 256-pin PBGA
Power Thermal Test Chip for PT-matrix Verification(PTTC) The package of this chip uses PBGA as well. In
order to show the feasibility of the proposed PT-matrix, the size of PTTC is 873μm × 873μm
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Conclusion
Propose a novel methodology which allows designers to simulate chips using a default package model and translate to the other desired package by applying the PT-matrix.