julien lamoureux and steven j.e wilton iccad 2003 1

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ON THE INTERACTION BETWEEN POWER-AWARE

FPGA CAD ALGORITHMS

Julien Lamoureux and Steven J.E Wilton

ICCAD 2003

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Outline

Introduction

Algorithms

Experimental results

Conclusion

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Introduction

Technology Mapping(CutMap)

Clustering(T-VPack)

Placement(VPR:T-VPlace)

Routing(VPR Router)

Circuit

Delay / Area / Power Estimations

FPGA CAD FLOW

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Introduction


Clustering(T-VPack)


Routing(VPR Router)

Circuit


FPGA CAD FLOW

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Introduction

AB

C

DE

mapping

f2

f3

f1AB

C

DEF

Technology mapping transforms a netlist of gates and registers into a netlist of K-input lookup tables (K-LUTs) and registers.

...

fSRAM

x

y

z...

001

0

...1

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Introduction


Clustering(T-VPack)


Routing(VPR Router)

Circuit


FPGA CAD FLOW

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Introduction


Clustering(T-VPack)


Routing(VPR Router)

Circuit


FPGA CAD FLOW

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Introduction Figure 1: An N cluster

Figure 2: A LUT and flip-flop BLE

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Introduction


Clustering(T-VPack)


Routing(VPR Router)

Circuit


FPGA CAD FLOW

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Introduction


Clustering(T-VPack)


Routing(VPR Router)

Circuit


FPGA CAD FLOW

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f3

f2

f1

Introduction

A

B

C

DEF

f1

f2 f3

ABC

DEF

Mapping + Clustering

PlacementRouting

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Algorithms

Technology Mapping(EMap)

Clustering(P-T-VPack)

Placement(P-T-VPlace)

Routing(P-VPR Router)

Circuit


FPGA CAD FLOW

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Algorithms





Circuit


FPGA CAD FLOW

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Technology Mapping

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Technology Mapping

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Algorithms





Circuit


FPGA CAD FLOW

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Algorithms





Circuit


FPGA CAD FLOW

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Clustering

T-VPack

P-T-VPack

Crit(B) is a measure of how close LUT B is to being on the critical path, Nets(B) is the set of nets connected to LUT B, Nets(C) is the set of nets connected to the LUTs already selected for cluster C

Activity(i) is the estimated switching activity of net i, Activityavg is the average switching activity of all the nets in the user circuit.

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Clustering

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Algorithms



Placement(P-V-Place)


Circuit


FPGA CAD FLOW

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Algorithms





Circuit


FPGA CAD FLOW

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Placement

T-Vplace

P-T-VPlace

q(i) is used to scale the bounding boxes to better estimate wirelength for nets with more than 3 terminals, as described in

[9]. Delay(i,j) is the estimated delay of the connection from source i to sink j, CE is a

constant, and Criticality(i,j) is an indication of how close to the critical path the connection is [9]. bbx(i) and bby(i) are the x and y dimensions of the bounding

box of net i

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Placement

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Algorithms





Circuit


FPGA CAD FLOW

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Algorithms





Circuit


FPGA CAD FLOW

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Routing

VPR-Router

P-VPR-Router

The baseline VPR router uses the following cost function to evaluate a routing track n

while forming a connection from source i to sink j:

b(n) is the “base cost”, h(n) is the historical congestion cost, and p(n) is the present

congestion of node n.

Activity(i) is the switching activity in net i, MaxActivity is the maximum switching

activity of all the nets, and MaxActCrit is the maximum activity criticality that any net can have. cap(n) is the capacitance associated with routing resource node n and ActCrit(i) is the activity criticality of

net i.

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Routing

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Experimental results

Node Duplication 3-LUTs mappings:

With duplication No duplication

julien lamoureux and steven j.e wilton iccad 2003 1

Documents

set of nets

steven j

close lut b

source i

critical path

average switching activity

n cluster figure

bounding box of net