june 20101 clock data q-flop flop dataq clock flip-flop is edge triggered. it transfers input data...

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June 2010 1 cloc k data Q- flop Flop data Q cloc k Flip-flop is edge triggered. It transfers input data to Q on clock rising edge. Memory Elements

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June Sequencing Elements Timing Notations

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Page 1: June 20101 clock data Q-flop Flop dataQ clock Flip-flop is edge triggered. It transfers input data to Q on clock rising edge. Memory Elements

June 2010 1

clock

data

Q-flopFl

opdata Q

clock

Flip-flop is edge triggered. It transfers input data to Q on clock rising edge.

Memory Elements

Page 2: June 20101 clock data Q-flop Flop dataQ clock Flip-flop is edge triggered. It transfers input data to Q on clock rising edge. Memory Elements

June 2010 2

Flop

clk

Flop

clk

Combinational Logic

TC

Static Sequencing by Flip-Flops

One flip-flop is used on each cycle boundary. Tokens advance from one cycle to the next on rising edge.

Page 3: June 20101 clock data Q-flop Flop dataQ clock Flip-flop is edge triggered. It transfers input data to Q on clock rising edge. Memory Elements

June 2010 3

Sequencing Elements Timing Notations

Logic Propagation Delaypdt

Flop Clock-to- Propagation Delaypcqt

Q

Flop Clock-to- Contamination Delayccqt

Q

Logic Contamination Delaycdt

Page 4: June 20101 clock data Q-flop Flop dataQ clock Flip-flop is edge triggered. It transfers input data to Q on clock rising edge. Memory Elements

June 2010 4

hold

Flop Hold Timet

setup

Flop Setup Time

t

Flop -to- Contamination Delacdqt

D Q

Flop -to- Propagation Delaypdqt

D Q

Page 5: June 20101 clock data Q-flop Flop dataQ clock Flip-flop is edge triggered. It transfers input data to Q on clock rising edge. Memory Elements

June 2010 5

Combinational LogicA Y

Flop

clk

D Q

A

Y

clk

D

Q

cdt

pdt

setuptholdt

ccqt pcqt

Page 6: June 20101 clock data Q-flop Flop dataQ clock Flip-flop is edge triggered. It transfers input data to Q on clock rising edge. Memory Elements

June 2010 6

Max-Delay Constraints

Q1

D2

TC

clk setuptpcqt

pdt

FF1

clk

FF2

clk

Combinational LogicQ1 D2

setup setup

sequencing overhead

c pcq pd pd c pcqT t t t t T t t

Page 7: June 20101 clock data Q-flop Flop dataQ clock Flip-flop is edge triggered. It transfers input data to Q on clock rising edge. Memory Elements

Min-Delay Constraints

Logic circuits cannot be too fast.

Such malfunction is called race condition, hold time

failure or min-delay failure.

Otherwise the input data to next sequential circuit will

change while it is still holding its current data.

Page 8: June 20101 clock data Q-flop Flop dataQ clock Flip-flop is edge triggered. It transfers input data to Q on clock rising edge. Memory Elements

June 2010 8

Combinational LogicFF

1

clk

Q1FF

2

clk

D2

Q1

D2

clkccqt

holdt cdt

hold hold ccq cd cd ccqt t t t t t

Page 9: June 20101 clock data Q-flop Flop dataQ clock Flip-flop is edge triggered. It transfers input data to Q on clock rising edge. Memory Elements

July 2010 9

Clock Skew

• Clock should theoretically arrive simultaneously to all

sequential circuits.

• Practically it arrives in different times. The differences

are called clock skews.

• Clock skew consists of the following components:– Systematic is the portion existing under nominal conditions. It

can be minimized by appropriate design.– Random is caused by process variations like devices’ channel

length, oxide thickness, threshold voltage, wire thickness, width and space. It can be measured on silicon and adjusted by delay components.

Page 10: June 20101 clock data Q-flop Flop dataQ clock Flip-flop is edge triggered. It transfers input data to Q on clock rising edge. Memory Elements

June 2010 10

FF1

clk

FF2

clk

Combinational LogicQ1 D2

setup skew

sequencing overhead

pd c pcqt T t t t

Q1

D2

setuptpcqt

pdt

clk

TC

skewt