kay rehlich xtca workshop @ rt2012 microtca.4 timing distribution and power supply issues

Kay Rehlich

xTCA Workshop @ RT2012

MicroTCA.4 Timing Distribution andPower Supply Issues

MicroTCA.4 Timing Distribution

Outline 2

Kay Rehlich, DESY (FLASH + XFEL Controls) MTCA.4 Timing Distribution, xTCA Workshop @ RT2012

MicroTCA.4 connectivity: Precision clocks Bussed clocks and triggers PCIe, Ethernet, SRIO Point-to-point links

Power supply issues Noise measurements Grounding

Conclusions


3


Motivation 3


Backplane

Ethernet To Timing Distribution


MTCA.4: Connectivity 4


2 radial clocks per AMC:

low jitter, configurable direction

8 bussed M-LVDS lines:

triggers, clocks and interlocks

Backplane

Ethernet (1) and PCIe (4)

Point-2-point:

SATA (2)

FPGA-2-FPGA (4)

Point-2-point:

SATA (2)

FPGA-2-FPGA (4)

Ter

min

atio

n

Ter

min

atio

n


5



Radial Clocks 7


B

ackp

lane

AMC ksender

MCH. . .

Cro

ssp

oint

Sw

itch

AMC nreceiver

AMC mreceiver

Clock

Gen.

. . .

• Point-to-point

• High precision(some ps jitter)

• Both ends terminated

• Any AMC can be sender

• With one MCH:TCLKA and TCLKB usable

• FCLK for PCIe

• Low jitter MCH in preparation

ADC

ADC


8 M-LVDS Lines: Trigger & Gate Distribution 8


B

ackp

lane

AMC ksender

. . .

AMC nreceiver

AMC mreceiver

Trigger

Gen.

. . .

FPGAFPGA

FPGAFPGA

L

H

H

One AMC is Master per line

Other AMCs can receive

All differential lines are terminated

on both ends of the backplane


8 M-LVDS Lines: Interlock Distribution 9


B

ackp

lane

AMC ksender

. . .

AMC nSender/receiver

AMC mreceiver

Interlock

Gen.

. . .FPGAFPGA

H

Interlock

Gen.

H

AMC can be Driver only

AMC can be Receiver only

AMC can be Driver andReceiver


8 M-LVDS Lines: Data Distribution 10


B

ackp

lane

AMC ksender

. . .

AMC mreceiver

FPGAFPGA

Data

Gen.

Data

Clock

Data

Clock

D0 D1 D2 D3

Data

Clock: e.g. 108 MHz

Other AMCs can receive

For lower speeds one single diff. line is enough


Point-to-Point Communication Links 11


B

ackp

lane

AMC k

AMC m

FPGA

Rx

Tx

Bi-directional ports

Several Gbps speed

Rx

Tx

FPGA


Clock and Trigger Transmission 12


LVDS

M-LVDS Trigger distribution

Radial Clockdistribution

Transition times: 1 ns

Rate: <= 500 Mbps

Rate: <= 2 Gbps


M-LVDS Specs 13


Drives: 100 Ohm 2 * 100 Ohm parallel termination

Required for Interlocks (wired-or)


XFEL Timing System: 1. Prototype

New timing system• Fiber optic links 1.3GHz • with drift compensation• AMC prototype is receiver

and transmitter• ps stability (< 5ps RMS)• Clock, trigger and

event distribution

14


1.3GHz

Clock

Data


A Timing System to Sync the Overall Facility


15

Receiver

Switch

Divider8 line

M-LVDS

4* RJ45:

4 * LVDSI/O

9 * LVDS

Out

FPGA

3 channel transmitter piggyback

PCIe

Ext. 1.3 GHz ref clock in

Opt

ion

al R

TM

:

9 tr

ansm

itter

s, t

rigg

ers

or c

lock

s

TCLKA, TCLKB

IN

O

UT

O

UT

O

UT

Fib

er o

ptic

s

PCB:In Progress

Piggyback:ready


Signal Quality and Power Supplies 16



MicroTCA Analog Performance 17


ADC

With RTM:

RMS= 5.86 bits

ENOB ~ 11.5

w/o RTM:

RMS= 4.9 bits

ENOB ~ 11.7

Open transformer:

RMS= 67.7 μV

2.22 bits

ENOB ~ 12.7

SIS8900 RTM

SIS8300

16 bit ADC


Grounding 18


220 Volt in

=

≈

ADC

Linear reg.

12 Volt DC

DC/DC

chassis

≈

AMC


SIS8300 ADC with 1.3 GHz Down Converter 20


Frequency spectrum with bad power supply Frequency spectrum with good power supply


Conclusions

MicroTCA.4 offers a variety of connectivity

Radial switched clocks

Bussed signaling for triggers and data

Point-to-point links

MicroTCA.4 provides very clean data acquisition

One power supply only showed high frequency noise

o Excellent performance with fast 16 bit ADCs

22



Thank you! 23


kay rehlich xtca workshop @ rt2012 microtca.4 timing distribution and power supply issues

Documents

timing distribution8

timing distributionoutline

timing distributionclock

timing distributionmtca

interlock distribution

data distribution

kay rehlichxtca workshop

preparationadcadckay