kenwood dp-1100sg optimisé

I I Knob (+IO, +20. +30, +40, +50)

Phone Jack (PHONES) Knob (OUTPUT LEVEL) (K29-2648-04) X 5

(El 1-01 62-05) (K29-2648-04) X 2

Metallic Cabinet Ass'y Front Glass (DISPLAY) Rernote Controller Ass'y

(A01-1618-12) (81 0-0897-04) (A70-0180-05)

I Knob (DIGITAL OUTPUT) (-7-1 51 4-04)

Power Cord Bushing (J42-0083-05)

Panel Ass'y (A20-5343-02)

Knob (POWER) (K29-2516-04)

Insulator Ass'y R: (J02-0356-05) X 2 L: (JO2-0357-05) X 2

Panel Ass'y (TRAY) (A29-0112-04)

I Phono Jack (COAXIAL) 1 (El 3-01 31 -05) Electric Circuit Module (OPTICAL)

Cap (~02 -0784 -05 )

(809-0068-05) Cap (809-0063-05)

Phono Jack (LINE OUTPUT) (El 3-0485-05)

in cornpliance w'th Federal Regulations, fol- KENWOOD-Corp. certifies this equipment lowing are reproductions of labels on, or conforms to DHHS Regulations No. 21 Inside the product relating to laser product CFR 1040. 1 O, Chapter 1, Subchapter J. safety. DANGER: Laser radiation when open

AC Power (E30-)

and i AVO

Refer to parts list on page 85.

CONTENTS

TRANSPORTATION SCREW.. . . . . . . . . . . . . . . . . . . . . . . . . . 2 . . . . . . . . . . . . . . . . . . . . . . . . . DISASSEMBLY FOR REPAIR 3

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYSTEM CONNECTIONS 4 CONTROLS AND INDICATORS. . . . . . . . . . . . . . . . . . . . . . . 5 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CIRCUIT DESCRIPTION 9 Description of components.. . . . . . . . . . . . . . . . . . . . . 9 Set Mode Flowchart.. . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Test mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Microprocessor pPD7521 6ACW-051 (X32-1170-00: ICI 0). . . . . . . 17 RF amplifier CXA1081 M (X29-1870-00: ICI) . . . . . . . . . . . . . . . . 20 Servo signal processor CXAI 244s (X32-1170-00: ICI ) . . . . . . . . . . . . . . . . . 26 Digital signal processing LSI CXDl l25QZ (X32-1170-00: IC6) . . . . . . . . . . . . . . . 30 Static RAM CXK5816SP-12L (X32-1170-00: IC7) . . . . . . . . . . . 51 Reset IC M51951ASL (X32-1170-00: ICI 1 ) . . . . . . . . . . . . . 52

DA Converter PCM56P-K (X25-3050-00: ICI, IC2). . . . . . . . . . . . . 53 Digital filter SM5804D (X25-3050-00: IC14). . . . . . . . . . . . . . . . . 54 D/A distortion correct TC1 7G005AF-0048 (X25-3050-00: ICI 5) . . . . . . . 58 Hexa D Flip-flop TC74HC174F (X25-3040-00: IC2). . . . . . . . . . . . . . . 58 Transistor array TD62003AP (X25-3040-00: IC3). . . . . . . . . . . . . . . . 59 2-channel analog switch IC pPD4053BC (X32-1170-00: IC2) . . . . . . . . . . . . . . . . 59

ADJUSTMENT/REGLAGE/ABGLElCH . . . . . . . . . . . . . . . . 60 PC BOARD (Component Side View) . . . . . . . . . . . . . . . . . . 67 PC BOARD (Foil Side View) . . . . . . . . . . . . . . . . . . . . . . . . . . 71 SCHEMATIC DIAGRAM.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 EXPLODED VlEW (MECHANISM) . . . . . . . . . . . . . . . . . . . . 83 EXPLODED VlEW (UNIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 PARTS LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 SPEClFlCATlONS . . . . . . . . . . . . . . . . . . . . . . . . . . . Back cover

Transportation screw Before transport: tighten the transportation

Before operation, remove the two red screws attached to screws

the bottom of the unit used during transport from the Before transporting this unit, be sure to tighten the two

factory. Remove both screws using a coin, etc. and, after transportation screws o r the bottom of the unit.

removing, retain them together with the Warranty card and other documents. When the unit isso be transported again, 1. Turn ON the power switch when no disc is loaded.

be sure replace the two screws to their original position: 2. Wait a few seconds until the disc OUT indicator cornes "ON". Then turn "OFF" the power.

DISASSEMBLY FOR REPAIR

Mechanism assernbly removal procedure 1. Rernove the screw (a) retaining the ground lug frorn

the rnechanism assernbly. 2. Rernove the three connectors (0). 3. Rernove the four screws (O) retaining the mechanisrn

assernbly.

4. Rernove the rnechanism assernbly by pulling out in the direction of the arrow (0 1.

SYSTEM CONNECTIONS Connection precautions Always turn OFF the power before making connections. Incorrect connections can cause damage to your audio system. Heed the precautions and follow the directions carefully.

To AC outlet

O DO not connect to other than the DIGITAL IN jack. It could darnage the

Use these stereo output jacks for connection to a typical amplifier or receiver. Note:

@ variable output (VARIABLE): output voltage 1. If your amp has both optical and coax digital inputs. use

O- 2Vrms variable only one or the other. Connection to both creates a loop which can cause undesirable oscillation.

'Ou adjust.the Output level from jacks t0 2. Be careful never to kink, twist or bend the optical fiber cable match the signal level of other sources connected to excessively. your amplifier Or receiver. als0 be used 3. Thi's unit is not necessarily compatible with the optical fiber

DIGITAL OUT, COAXIAL) successful. consult your dealer or service representa-

Connection to amplifier or receiver P I U ~ in the AC power cord for the CD piayer and (The following three methods are possible.) amplifier. i

Conventional amplifier connection: Connect the CD player's LlNE OUTPUT (FIXED or VARIABLE) to the AUX or CD input jacks on the rear panel of the amp or receiver. Use the supplied cord. Be sure to connect the left (L) and right (R) jacks on the CD player to the corresponding jacks on the amplifier or receiver.

Connection to an amplifier equipped with digital input: Use a single coaxial cable to connect the CD player's DIGITAL OUT jack to the digital input jack on the amplifier.

Connection to a component equipped with optical fiber cable (OPTICAL INPUT) terminal: Use an optical fiber cable to connect the CD player's (DIGITAL OUT) OPTICAL terminal to the optical input terminal on the other component.

CONTROLS AND INDICATORS

O POWER switch (B Numeric keys (1 - 0) - -

@ DIGITAL OUTPUT indicator This illuminates when the digital output switch IS on.

@ DIGITAL OUTPUT switch This switches digital output on and off.

O PHONES jack Plug stereo headphones into this jack.

Q Dyna-pneumatic suspension Designed to safeguard sound quality by isolat- ing the player from adverse external vibrations.

Note: To rnaintain the effectiveness of the Dyna-pneurnatic suspension. do not place other cornponents or items weighing more than 5kg on top of this unit.

@ REMOTE SENSOR window This picks up infrared signals from the remote control.

O OUTPUT LEVEL adjustment keys These DOWN/UP keys simultaneously adjust both the rear panel VARIABLE output signal level and headphone volume. The output level setting is shown by the indicators on the right side of the display:

8 OPEN/CLOSE key ( A ) Press once to open the disc tray. Press again l l to close.

O 4D

@ INDEX keys ( a INDEX El ) Used to specify index numbers within tracks.

(b Manual search keys ( 44 , bb ) These keys let you move quickly forward or backward across the disc.

Q) Music skip keys ( 44 , bbl ) Used to skip forward to the start of the next track or back to the start of the current or preceding track.

(D STOP key (W) Press to stop play.

@Play indicator ( b)

@ PLAY/PAUSE key ( D II ) Press to begin play. Press during play to pausr- or resume play.

@ Pause indicator ( Il )

(B PLAY MODE keys Used to select the play mode: TRACK, PROGRAM, TIME, or SINGLE.

Display window

@ Disc indicator (DISC) Confirms that a disc is in the tray.

@ Disc out indicator (m) This illuminates (red) when there is no disc in the tray.

0 A-B repeat indicator (mm) @ REPEAT indicator ((REPEATI)

Used to specify first digit in a number when selecting a tune or setting a time.

(b Numeric keys (+IO - +50) Adds ten to a number. Used with the numeric keys.

@ EDlT key Used to automatically fit tracks into a program of a specified time length.

SPACE key This causes play to pause for about four seconds between tunes. useful when taping.

@ TlME DISPLAY key This switches the time display.

@ CLEAR key This erases the last tracks in a program.

@ DISPLAY

Q) CHECK key Press to check program contents.

@ TO key When programming, this lets you input a number of consecutive tunes starting at a particular track number.

1 1 1 1 1 1 1 1 1 1 1 @ A b 4 B repeat key

' @ Time counter (TOTAL TIME, SIN- t

lndicates the track (selection) num- I I I I I 1 bers on the disc. or shows which 0 0 0 8 @ O selections are programmed for play.

GLE TIME)

8 Maximum track number indicator (MAX TNo.) Shows the highest track number found on the current disc.

Music calendar (1 - 20)

OUTPUT LEVEL indicator Six LEDs show the output level (of the signal from the VARIABLE jacks on the rear panel.) This can be adjusted by remote control or output level adjustment screw on the roarnanol

r------- -r--1 1 2 3 4 511LEEI

8 8 B E - I 7 8 9 ,o/!:g 1

I 1 1 3 ~ 1

'7% ;Es wxTm. 111 12 13 14 1 5 ! 1 2 s ' -3-gj3338 8 8 I '16 17 1 1 l e 200'3 - I

L -----T- A l L r A I

@ SPACE indicator (-1) @ Emphasis indicator (EMPHASIS)

This confirms that the disc in play was recorded with high frequency emphasis.

I I l l

0 Edit indicator ( m l ) @ Program check indicator (m)

Lights up when you check program contents.

@ Index number (INDEX)/program number (PNO.) Shows the current index number within the track. Shows the number of tracks during programming or when checking program contents.

@ Track number display (TRACK NO.) Shows the track number (according to the order of the selections on the disc).

This key lets you define the beginning (A) and end (B) points of a section of music that you want played repeatedly.

@ REPEAT key Used for repeated play.

@ Disc tray

BLOCK DIAGRAM

CIRCUIT DESCRIPTION

Description of components

I C2 TC74HC174F 1 D-type flip-flop 1 Controls larnps and LEDs for each mode

IC3 TD62003AP Transistor array 1 Transistor array drives larnps and LEDs for each mode

Display Unit (X25-3040-51)

( data.

IC3.4 NJM5532D-D ( 1-V converter 1 (1/2) Converts current output of D/A converter into voltage.

Operation/Condition/Cornpatibility Cornponent

DAC Unit (X25-3050-00)

1 (2/2) Generates offset voltage for distortion compensation.

IC5-8 NJM5532D-D 1 Op amp 1 Consists GIC (general irnpedance converter) in LPF

UselFunction

ICI BX1408 1 Rernote control signal receiving

Operation/Condition/Cornpatibility Cornponent

(OS) D l 7 E-102 Constant current diode ( Constant current diode for +-15 V constant power supply

Converts the infrared signal from the remote control into logic signal

UseIFunction

IC9.10 NJM5532D-D

IC1 3 M5220P

ICI4 SM5804D

ICI 5 TC1 7Q005AF- 0048

ICI 6 M5F79M06L

ICI 7 M5F78M06L

IC22 M5F79M05L

IC23 M5F78M05L

IC24 M51951ASL

0 2 2SD1266(P)

Q3 2SB941 (P)

0 1 O DTC114YFF

QI1 DTC114YFF

Q1 2 DTC143EFF

Q1 3 DTC143EFF

Q I 4 2SA733(A)

ICI .2 PCM56P-K 1 D/A converter Resistance ladder type D/A converter; converts digital data into the volume of analog

Op amp

OP amp Digital filter

D/A distortion compensator

3-pin regulator

3-pin regulator

3-pin regulator

3-pin regulator

Reset lC .

Ripple filter

Ripple filter

Switch

Switch

Switch

Switch

Transistor

Control Circuit Unit (X29-1870-00)

Buffer amp and output arnp

Error arnp for f 15 V constant power supply

4 times oversampling digital filter

D/A distortion compensation. 2SB detection circuit

-6 V (-VCC) power supply for D/A converter circuit

+6 V (+VCC) power supply for D/A converter circuit

-5 V (-VL) power supply for D/A converter circuit

+5 V (+VL) power supply for D/A converter circuit

Reset IC for digital filter

Ripple filter for +15 V constant power supplv

Ripple filter for -1 5 V constant power supply

Relay driver for deemphasis

Relay driver for muting

Muting photocoupler driver

Photocoupler driver for deernphasis

For power supply of photocoupler output

ICI CXA1081 M

I C2 TC74HCOOP

0 1 2SC2878

Operation/Condition/Cornpatibility Cornponent Use/Function

RFarnp

NAND gate

Switch

Focus error signal generation. tracking error signal generation. RF signal generation and phase compensation. and auto symrnetry compensation circuit

EFMT signal waveform detection. auto syrnmetry signal detection

Focus error amp bias select switch

CIRCUIT DESCRIPTION

CD Player Unit (X32-1170-00)

IC2 pPD4053BC

IC3 M5218P-K

OperationlConditionICompatibility

Various pulse generation for focus servo. tracking servo. and feed servo. (CX20108 shrink type)

Cornponent

ICI CXA1244S

I C4 NJM4558D

IC5 M5218P-K

UseIFunction

Servo lC

Analog switch

Op amp

IC6 CXD1125QZ

1 C7 CXK5816SP

IC9 TC74HC08P

ICI O pPD75216 ACW-05 1

Receives scratch detection signal (DFCT signal frorn pin 21 of CXA1081 M) and turns focus and tracking servo OFF when scratches are present.

(1/2) For focus servo phase compensation (2/2) For trackina servo hase corn~ensation

Op arnp

Op amp

ICI 1 M51951ASL

ICI 2 LB1344N

IC13- 17 LB1294

Q I 2SC2878 1 Switch 1 Focus gain select

(1/2) For VARIABLE volume motor drive (2/2) For tray rnotor drive

(1/2) PLL compensation circuit (LPF+amp) (2/2) CLV corn~ensation circuit (LPF+level shifter)

Digital signal processing LSI

Static RAM

AND gate

Microprocessor

ICI 8 M5F78M05L

ICI 9 M5218L

IC20 NJM558D

Executes al1 digital signal processing including EFM data decoding, error correction, interpolation. PLL circuit. CLV servo and digital out, etc.

Signal processing RAM (16K)

Buffer arnp for digital out. and reset signal generator when power is ON/OFF

Display, each key input processing and servo IC control.

Reset lC

Linear scale level rneter IC

FL driver IC

0 5 2SA1534A 1 Driver 1 Tracking actuator driver

Generates reset signal when power is ON/OFF

Outputs VARIABLE volume position indication

IC for drivina FL disolav

3-pin regulator

OP arnp

Op amp

O2 2SC3940A

Q3 2SA1534A

Q4 2SC3940A

+5 V power supply for digital and servo circuits

Headphone amp

(1/2) Rising and trailing control for +5 V and -5 V power supply (2/2) Suo~ l ies +5 V for ALPC. and controls laser ON/OFF

1 0 9 2SA1534A 1 Driver 1 Tray rnotor driver

Driver

Driver

Driver

Q6 2SC3940A

Q7 2SA1534A

O8 2SC3940A

Focus actuator driver

Focus actuator driver

Trackina actuator driver

1 Q I 3 2SB772 1 Driver 1 VARIABLE volume rnotor driver 1

Driver

Driver

Driver

Q I 0 2SC3940A

Q I 1 2SA1534A

Q12 2SD1266

Q I 4 2SC1685 1 Ripple filter 1 Power supply for FL driver (+6.6 V)

O1 5 2SC945(A) 1 Switch 1 FL driver switch

Feed motor driver

Feed motor driver

Trav motor driver

Driver

Driver

Driver

Disc motor driver

Disc motor driver

VARIABLE volume rnotor driver

(0.P)

Q I 6 2SA733(A) i0.P)

0 1 7 2SC3940A

0 1 8 2SA954

O1 9 2SA1127NC

Q20 2SC3940A

Level shifter

Q21.22 2SC3940A

023.24 2SA1534A

Q25 DTAl24EN

Q26 DTAl24EN

Level shifter for FL driver

Ripple filter

Ripple filter

Ripple filter

R i ~ ~ l e filter

Power supply for larnps and LEDs foreach mode (+7.5 V)

Power supply for FL reference voltage (-32 V)

-5 V power supply

+5 V ~ o w e r s u ~ ~ l v (for ALPC)

Driver

Driver

Digital transistor switch

Digital transistor switch

Headphone amp driver

Headphone amp driver

Controls focus offset voltage by the MUTE signal

Selects focus gain by the FGSW signal

CIRCUIT DESCRIPTION

Set Mode Flowchart (Simplified flowchart after power ON)

POWER ON Q 500ms Wait r - i

Tray close u Returns pickup

to inside

Laser ON

Focus Lens ldDunl 350ms Wait u Focus Lens 9

1 signal "H"

SENSE signal chattering

rernoval. 500 us "DISC OUT"

indicated I

A I

If 1.2 sec failure .

Dise Motor rotation start

Tracking ON u or more

Feed Motor a TOC read-out a

IF 15 sec failure

1 Searches start

of 1 st track and starts play

Disc Motor bra ke

Disc Motor ii

CIRCUIT DESCRIPTION

Test mode I f the TEST pins are short-circuited when the power is

turned ON, the microprocessor enters test mode. With the microprocessor set to test mode, each operation can be easily checked after making a repaire or adjustment.

With the DP-1 100SG. the microprocessor can be set to test mode by short-circuiting pin 6 and pin 7 of the CD PLAYER UNIT (X32-1170-00). Note': "Set mode" shows the normal status.

the TEST pin short-

circuited? c ,, , , 1-1

OPENICLOSE key.

"01" is dirplayed.

Set mode Effective keys in the Test mode and their functions 6 No. Input k.y Function Track No. display

. . . . . . . . . . . . . . (1 ) Focus servo ON. TRACK NO.

. . . . . . . . . . . . . (2) Tracking servo ON.

(3) Feedsewo. ON. 1-1

. . . . . . . . . . . . . . I I , 1 1 PLAY When the key is pressed i n the Stop mode. the servoes are switched 1

ON automatically in the order from (1 ) t o (3). Displayed for a few seconds after (1 ) t o (3).

1 Disc's Track No. is displayed.

(1) Focus s e ~ o . . . . . . . . . . . . . . ON. TRACK NO.

2 CHECK (2) Tracking servo . . . . . . . . . . . . OFF. 1-1 J' . . . . . . . . . . . . . . (3) Feedsewo. OFF. I I , 1

(1) FOCUS servo . . . . . . . . . . . . . . ON. T R A C K NO.

. . . . . . . . . . . . 3 CLEAR (2) Tracking servo ON. 1-1 I I . . . . . . . . . . . . . . (3) Feed servo. OFF. L I 1

(1) FocusSewo . . . . . . . . . . . . . . OFF. TRACK NO.

. . . . . . . . . . . . 4 STOP (2) Tracking servo OFF. 1-1 1 (3) Feed servo . . . . . . . . . . . . . . . OFF. I l 1 (1) Tray open

TRACK N O (2) Laser.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ON.

5 REPEAT When the tray is closed by pressing it. +10 function will be released. 1-1 -1 The TRACK NO. display shows "01 ".

I I r I n Stop mode : Moves the PU slightly t o the outer tracks.

6 bb With feed servo ON : Switches the tracking gain to "H".

I n Stop mode : Moves the PU slightly t o the inner tracks. 7 44

With feed servo ON : Switches the tracking gain t o "L".

Jumps the number of tracks as follows:

Numeric (digit) 8

keys (0-9)

When the tray is opened and the closed again in test mode, TRACK

12 9 OPEN/CLOSE NOS. 2, 17. 2. 6. 7. 8. 10. 13 and 22 are automatically programrned

Opening the tray again will cause the unit to enter set mode.

Key Number of tracks

Direction

Key Number of tracks

Direction

1 1 2 1 3 1 4 1 5

1 1 4 1 16 1 32 11000 Outward

6 1 7 1 8 1 9 1 0 1 1 4 1 16 1 32 11 000

lnward

CIRCUIT DESCRIPTION

Flow chart of test mode Flow chart from tray OPEN status sfter power ON

Power ON 7 Tray CLOSE

i

1

utward feed of PU

01 displayed in TNO

SLT : "H"? 9

5 sec. elapsed?

Cancellation FI

SLT : "Lu? e Outward feed l?]

SLT : "H"? 9

data store

5 sec. elapsed?

YES YES

Cancellation of tray

CLOSE key pressed?

1 YES l SLT : Pickup start lirnit switch CLS : Tray clore detect switch OPEN : Tray open detect switch

Acceptance of key

CIRCUIT DESCRIPTION

Focus warch & focus servo ON

1 .O sec

Focus UP h

SENSE :

Focus servo ON

4 I

Disc motor ON

&

C b

Tracking sewo ON

CIRCUIT DESCRIPTION

Disc rnotor stop

Trac k i ng servo I ON 1 4 0-j) FOK terminal 1

YES

3 sec. elapsed?

("SENSE")

NO

v 2

200rns WAlT Q

Disc motor brake

Disc motor

Disc motor 4OP

>

2 sec.

l

1 YES

Focus search O Ga

CIRCUIT DESCRIPTION

Flow chart from the time the tray opens until the STOP a From loading of Q data to display

START < indicator lights, after pressing the tray.

START

m 4 t Tray CLOSE

NO

Y ES -1

Loading of al1 of @ 96 bit data

Focus servo ON after focus search

. i , Tracking

A servo ON NO b

4 Feed servo ON

4 I TOC load I

4 NO STOP display

1

1 Stop of PU 1 Disc stop I a

Microprocessor pPD75216ACW-051 (X32-1170-00 : ICI 0) Terminal connection diagram

(Top View)

Pd VDD (+5v)

Pc Pe

Pb P f

Pa p g

SENSE Ph

WFCK pl

SUBQ p i

CRCF GND

Fi CI GND

SCOR Pk

FOK PI

GFS G14

RMUTE G13

EMPH G12

DlRC G11

MUTG G10

FGSW G 9

SLTSW G8

OPNSW G7

CLSSW G 6

K 1 G 5

K 2 G4

K3 G3

K 4 G 2

DATA G 1

X L T RESET

CLK VRUP

LDC VRWWN

XRST CLSM

(4.23MHz) X I OPNM

X2 N C

GND NC

CIRCUIT DESCRIPTION

Pin Function Table

Pin No.

RESET

I/O 1 Pin Name 1 Functions

O 1 Pd- Pa 1 FL display segment indication and key scan signal output

I 1 SENSE 1 Sensing signal input (from CXDl125QZ. CXA1244S)

I WFCK O data read-off clock input (from CXD112502)

l SUBO Q data input (from CXDl125QZ)

I CRCF O data CRC OK rH") input (from CXD1125QZ)

I RCI Remote control signal input

I SCOR Q data sync signal input (from CXDl125QZ)

I FOK Focus OK ("Ha') input (from CXA1081 M)

I GFS 1 EFM sync OK ("Ha') input (from CXD1125QZ)

O 1 RMUTE 1 Relay mute ON/OFF ("L"/..H")

O EMPH Emphasis ON/OFF ("H"/"L")

O DlRC DlRC signal output (to CXAl244S)

O MUTG MUTG signal output: Mute ON/OFF ("Hm/"L) (to CXD1125Q.Z)

O FGSW Focus gain switch signal output

I SLT SW Start limit switch signal input (SW ON = "L")

I OPN SW Tray open switch signal input (SW ON = "L") 1 CLS SW Tray close switch signal input (SW ON = "L") I K 1

*l Key input for frontpanel

O DATA Control data signal output (to CXD1125QZ. CXA1244S)

O X LT Control data latch signal output (toCXDl12502. CXAl244S)

O CLK Control data clock signal output (to CXD112502. CXA1244S)

O LDC Laser ON/OFF ("H"/"L") signal output

O XRST Control reset signal output (to CXD1125O.Z. CXAl244S)

I X 1 Clock input pin (1/2 clock of CXD1125QZ)

O X2 (Oscillating frequency 4.2336 MHz)

- Vss GND (ground)

O OPNM Tray open/close signal output Normal (OPNM = "Y, CLSM = " L ) Open (OPNM = "H". CLSM = "L")

O CLSM Close (OPNM = "Y, CLSM = "HM)

O 1 VRDOWN 1 Motor volume level down signal output

O 1 VRUP 1 Motor volume level up signal output -

I RESET Reset signal input

O G1 - G14 FLdisplay digit indication output

O PI FL display segment indication output

O P k (Pt is also used for key scan)

I VLOAO GND (ground)

I VPRE GND (ground)

O Pj- Pe FLdisplay segment indication and key scan signal output

I VDO +5 V power supply

CIRCUIT DESCRIPTION

RF amplifier CXAl081 M (X29-1870-00 : ICI) The CXA1081 M supplies the following functions as

required for controlling the RF'amp in the compact disc player.

RFamp Focusing error amp Tracking error amp APC circuit Auto asymmetry control amp Focus OK detection circuit Mirror detection circuit Defect detection circuit EFM comparator

Block diagram VI

O a L U

w 5 O m 14 E z VI

O m a 0 O 4;i

- w

Y

l- Y W LL 2' U

Z W U U U

- O LL LL O Z D . J

O O

- N U W O - K

K a O > W

N

O O Y LL

V

K O

> U

CIRCUIT DESCRIPTION

Explanation of terminals

4

5

6

7

8

9

1 O

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

Terminal No.

1

2

3

I

110 I

O

I

Terminal name

RF1

RF0

RF

PIN

LD

PD

PD1

PD2

VC

F

E

€ 0

El

VR

CC2

CC 1

VEE

FE BlAS

FE

TE

DEFECT

MlRR

CP

C B

DGND

ASY

EFM

FOK - LD ON

30

Function

Input pin of the Ccoupled signal output from the RF summing amp.

Check point of eye pattern for the RF sumrning amp output pin.

RF summing amp feedback input pin.

Vcc 1 - 1 Positive power supply. 1

I

O

I

I

I

-

I

1

O

I

O

I

O

-

I

O

O

O

O

I

I

-

I

O

O

I

P-subIL-sub select pin of LD. (DC voltage: in N-sub mode)

APC LD amp output pin. (DC voltage: PD open in Nsub mode)

APC PD amp input pin. (DC voltage: open)

RF 1-V amp (1) invert input pin. Current input by connecting to PIN diode A + C.

RF 1-V amp (2) invert input pin. Current input by connecting to PIN diode B + D.

Connected to GND when using a positive ( + )lnegative (-) dual-voltage power supply. Connected to VR (pin 14) when using a single-voltage power supply.

.F 1-V arnp invert input pin. Current input by connecting to PIN diode F.

E 1-V amp invert input pin. Current input by connecting to PIN diode E.

E 1-V amp output pin.

E 1-V arnp feedback input pin. For E 1-V amp gain adjustment.

DC voltage output pin of (Vcc + V E E ) / ~ .

Input pin of the Ccoupled signal output from the defect bottom hold.

Defectbottom hold output pin.

Connected to the negative power supply when using a positive ( + Ilnegative (-) dual-voltage power supply. Connected to GND when using a single-voltage power supply.

Bias pin at the focus error amp non-invert side. For CMR adjustment of the focus error amp.

Focus error amp output pin.

Tracking error arnp output pin.

Defect comparator output pin. (DC voltage: connected to a 10kn load).

Mirror comparator output pin. (DC voltage: connected to a l O k n load).

Mirror hold capacitor output pin. Mirror comparator non-invert input.

Defect bottom hold capacitor connect pin.

Connected to GND when using a positive ( + Ilnegative (-) dual-voltage power supply. Connected to GND (VEE) when using a single-voltage power supply.

Auto asymmetry control input pin:

EFM comparator output pin. (DC voltage: connected to a l O k n load).

FOK comparator output pin. (DC voltage: connected to a 10kn load).

LD ONIOFF select pin. (DC voltage: when LD ON).

CIRCUIT DESCRIPTION

Explanation of function The low frequency component of the RF0 output

RFamp voltage, VRFO is represented by the following equation:

The photodiode current input to the input pins (PD1, PD2) is converted to a voltage by an equivalent resistance VRFO = 2.2 x (VA + VB)

of 58kS2 in RF 1-V amp (1) and (2) respectively. The = 127.6k C2 x ( i p n i + i p n z )

voltage which is converted from the current of the photodiode (A + B + C + D) is added in the RF summing amp and is output from the R F 0 pin. The eye pattern can be checked at this pin.

VCC

d

! l!l k I - V AMP ( 1 ) 1 . . . LI

5aK Y 1 RF SUMMING AMP ,

10K 1b

IP02 I VB

RF I -V amplifier

Focus error amp The difference between the RF 1-V amp (1) output

(VA) and the RF 1-V amp (2) output (VB) is calculated, and the current of the photodiode (A + C - B - D) is converted to a voltage and output.

The FE output voltage (low frequency) is represented by the following equation:

- IB+D) - ( A + C )

F E

VA F O C U S ERROR

C 2 25P- 164 K AMP

CIRCUIT DESCRIPTION

Tracking error amp The difference between the E 1-V amp and the F 1-V The current from the side spot photodiodes is input to amp is calculated by the tracking error amp, and the photo.

pins E and F and is converted to a voltage by the E 1-V diode (E-F) current is converted to a voltage and output.

arnp and F 1-V arnp respectively. That is: VTE = (VE - VF) X 3.2

V~= iFX403kQ = (iE-iF) X 1290k Q

V ~ = i E x 2 6 0 k !2 X R A / ( R B + ~ ~ ~ ) + (RA +260k)

Focus OK circuit C34 is used to determine the time constants of the EFM The focus OK circuit creates a timing window, turning comparator, the HPF in the mirror circuit, and the LPF

the focusing servo ON with the focus search status. in the focus OK amp. Normally, C34 = O.01pF is selected, While the RF signal is present at pin 2, its HPF output with fc = 1 kHz. This will prevent degradation of the block

is present at pin 1. At the same time, the LPF output error rate due to an RF envelope lack caused by cracks, etc. (opposite phase) of the focus OK amp is obtained. on the disc.

The focus OK output is inverted when VRFI -VRFO = -0.37V.

1 From summing amplifier.

I

'% ~~~~~~~ 15 K QK FOK

0 . 6 2 5 V

1 FOCUS OK AMP FOCUS OK 1 I CCUPARATOR 1 L,,----,---,,,----,,,J

CIRCUIT DESCRIPTION

Mirror circuit In the mirror circuit, after the RF1 signal is amplified,

both peak and bottom holds are held by a time constant which can follow a traverse of 30kHz. while only the bottom hold is held by a time constant which can follow a cyclic period envelope variation respectively.

These peak/bottom hold signals, H and I are differ- entially amplified to obtain the DC-reproduced envelope signal J.

This signal is compared with signal K, that the 2/3 level of the peak value is peak held by a large time constant so that the mirror output is obtained. That is, the mirror output goes "L" on the disc tracks and goes "H" between tracks (mirror section). In addition, the output goes "H" when -a defect is detected. The time constant of the mirror hold should be quite larger when compared with the traverse signal.

H (PEAK HOLD) n / v \ o v

I (BOTTOM

HOLD) Oov

I I I

0 . 0 3 3 ~

I I

MIRROR AMP I I

i MlRRoR

I CowARAToR DGNo h i b - - - - - - - - - - - J

CIRCUIT DESCRIPTION

EFM comparator The EFM comparator converts the RF signal into a

binary coded signal. Since asymmetry caused by disper- sion when manufacturing the discs cannot be reduced by AC coupling only, the reference voltage of the EFM comparator is controlled using the characteristics that the present probability of a 1 or O is 50% each for the binary coded EFM signal.

The EFM comparator is designed as a current switching type, and the "H" and "L" levels are not equal to the power voltages. Therefore, feedback is required via a CMOS buffer.

R9. R I O , C3 and C8 constitute a LPF to obtain the DC cornponent of (Vcc+DGND)/2 (VI. If the cut-off frequency (fc) is set to more than 500Hz. leakage of the EFM low frequency signals will be greatly increased and will result in a degradation of the block error rate.

AUTO ASYMMETRY

RF1

I EFM COMMRATOR 1 L-------- ,,,- - ------- -----A

Defect circuit After inverting the RF1 signal, the defect circuit bottom

holds with the two long/short time constants. The bottom a

hold with a shorter time constant responds to a mirror defect of more than 0.1 msec on the disc, and the bottom b hold with a longer time constant holds the mirror level obtained immediately before the defective section. These signals are C-coupled, then differentiated with level shift-

BOTTOM ing. The signals are compared with each other to generates Broken line CC2 the rnirror defect detecting signals. Continuous

line CC1 n n H

e 2- LL - 1 Amsec M A X

EFECT BOTTOM DEFECT AMP

Servo signal processor CXAl244S (X32-1170-00 : ICI)

CIRCUIT DESCRIPTION

CXA1244S is a bipolar IC developed for servo of compact disc (CD) players, and it provides the following functions.

OTracking control (servo ONIOFF, single track jump, multiple track jump, gain control, phase compensation control, brake circuit)

0 Sled control (servo ONIOFF, fast forward, fast reverse)

Block diagram

Terminal connection diagram - SENSE

V)

XRST 3 DATA N

s CLK X

10 O MlRR 11

TZC 12

TE 13 ISET 14

VCC 15

29 TG 1 T A O

TAO DlRC SL@

S L O S LO

FE@ 2 1 F EO

20 FE

19 ATSC 18 FS3 17 VEE

16 SRCH

TG2 TA@ T E 0 TE@ SENSE C.OUT XRST DATA XLT CKL MlRR TZC TE ISET VCC

CIRCUIT DESCRIPTION

Terminal No.

1

7

3

4 5

If0 Terminal name

TG2

TA a

- 6

7

8

9

1 O

11

12

13

14

Functiom Tracking amplifier gain switching terminal. GND level.

Non-inverted inout of ooerational amolifier 2.

TE0

TE

SENSE

15

C. OUT

X RST

DATA

X L T

CLK

MlRR

TZC

TE

ISET

- 17

18

19

20

21

22

23

24

25

26

27

28

29

Note 1 : SENSE terminal output

.

O

Vcc

1 Explanatien

I 1 "H" when focus zero

Output of operational amplifier 4.

lnverted input of operational amplifier 4.

Output o f SSP interna1 status that corresponds t o ADDRESS of CPU -+ SSP.

O

I

I

I

I

I

I

I

/ Power supply terminal. Normally +5V.

16 1 SRCH

VEE

FS3

ATSC

FE

FE0

FE O S LO

SL

SL @ Dl RC

TAO

T A O TG 1

30

cross. Focus erro volL Tage is O\/ or higher.

FOCUS PULL opera-

(Changes in accordance with ADDRESS content of internal serial register.) See Note 1 .

Signal output for counting number of tracks at the time of high speed access.

Al l interna1 registers are cleared when CPU + SSP "L". Connected with CPU RESET. See Note 2.

Serial data transmission of CPU -t SSP. Input is made from LSB. DO-D7.

Latch o f serial data of CPU + SSP. (The contents of interna1 serial register are transmitted t o each

address decoded latch.) Transmission at "L". Change t o "H" occurs immediately after execution because no edge trigger is produced.

CPU -t SSP serial data transmission block. Data is read at falling. "H" level before and after transmission.

Mirror signal input from RF amplifier.

Tracking error signal is input wi th C couple. The time constant is determined by one single track jump, but it is usually around 2kHz.

Tracking error signal input.

Setting o f current level for determining focus search voltage, tracking jump voltage and thread feed voltage.

1 The condenser for determining the time constant of chargeldischarge waveform for focus search

GND 1 1 GND terminal of IC. 1

tion.

"H" when the ATSC input level exceeds the wind camparatbr level

CONTROL IVTH = 'Vcc x 13%).

I

O

I

O

I

I

I

O

O

1 1 1 1 But fhis is no1 used in 1

is connected.

Power supply terminal. Normally -5V.

Focus amplifier gain switching terminal. GND level.

Such information that a mechanical shock was applied t o the player is input. Simply, a trakcing error is input through BPF. I n this equipment it is connected t o GND level and is not used.

Input of focus error signal.



Output of operational output 3.


Non-inverted input of operational amplifier 3.

Used at the time of one track jump. Normally "H". The direction of the track jump pulse is reversed with "L". Setting is made in the normal tracking mode by changing to "H". "L" for a fixed length of time with detection of activation, deactivation of TZC.



Tracking amplifier gain switching terminal. GND level.

fhis equipmenl.

1 1 Judoement output of positive or negative ol tracking zero cross. tracking error. When used at the timr of ringle track lump. DlRC ir reduced 10 "Ln on defection of TZC t . in FWD JUMF or on derection of TZC 1 in REV JUMP

TRACKING MODE

Note 2 : Digital unit timing chart

I l

Data is loaded at activation

TZC

CLK k t w c k w twck

w 1 Ifck

, 1 ,

Execution of instruction 1 + 1 tWL

2 7

CIRCUIT DESCRIPTION

Systern control

GAlN SET* TG1, TG2 may be set independently. In the case of ANTl SHOCK = 1 (0001 I X X X ) , both TGl , TG2 are inverted when ANTl SCHOCK = "Hu.

COMMAND

FOCUSCONTROL

TRACKINGCONTROL

TRACKINGMODE

TRACKING MODE *

SERVO ON

FWD JUMP

REV JUMP

SLED MODE * I D ~ / D O ( 1

OFF

ADDRESS

1 SERVOON 1 ; 1 ; 1 FWD MOVE

Note : The antishock circuit is not used in this equipment.

*

SENSE

FZC

AS

TZC

D7

O

O

O

DATA

D6

O

O

O

D5

O

O

1

D3

FS4 FOCUS

ON

ANTl SHOCK

D4

O

1

O

D2

FS3 GAlN DOWN

BREAK ON

TRACKING* MODE

SLED* MODE

D l

. FS2 SEARCH

ON

DO

FS 1 SEARCH

U P

TG2 TG1 * GAIN SET

CIRCUIT DESCRIPTION

Serial data truth value table Serial data

FOCUS CONTROL

00000000

00000001

0000001 O

O000001 1

O00001 O0

O0000 1 O 1

O00001 1 O

O00001 1 1

O0001 O00

O000 1 O0 1

00001 O1 O

O0001 O1 1

00001 1 O0

O0001 1 O1

O0001 110

O0001 1 1 1

AS : ANTI SHOCK TRACKING CONTROL

O001 O000

O001 O001

O001 O010

O001001 1

O001 O100

O001 O1 O1

000101 10

O001 O1 1 1

O001 1 O00

O001 1 O01

00011010

00011011

O001 1 1 O0

O001 1101

00011110

00011111

- -

TRACKING MODE

Hexa-

SOO

SO 1

S02

S03

S04

S05

S06

S07

S08

S09

SO A

SO B

SOC

SOD

SOE

SO F

00001 0 O01 01 0 00001 1

O1 @O00 01 1 O00 1 00001

100000 101 O00 100001

000001 O001 O0 00001 1

O0001 1 O001 1 O 00001 1

010001 010100 1 O000 1

100001 1 O01 O0 100001

O00 1 O0 O01 O00 00000 1

O001 1 O O01 O1 O 00001 1

010100 O1 1 O00 100001

100100 101000 1 O000 1

O01 000 000100 O000 1 1

001010 O001 10 00001 1

O1 1 O00 O1 O1 O0 1 00001

1 O1 O00 100100 100001

DC : DlRC input terrnin

Function

FS = 4321

O000

O001

O01 O

O01 1

O100

O101

O1 10

O1 11

1 O00

1001

1010

101 1

1100

1101

1110

1111

S1 O

SI 1

51 2

S13

SI 4

SI 5

SI 6

SI 7

S18

SI9

SI A

SI B

SIC

SI D

S1 E

S1 F

D2 AS=O AS = 1

(Brake) T G = 2 1 T G = 2 1

O O O O O

O O 1 0 1

O 1 O 1 O

O 1 1 1 1

1 O0 O 0

1 O 1 O 1

1 1 O 1 O

1 1 1 1 1

O O O 1 1

O O 1 1 O

O 1 O 0 1

O 1 1 0 O

1 O O 1 1

1 O 1 1 O

1 1 O O 1

1 1 1 O O

CIRCUIT DESCRIPTION

Digital signal processing LSI CXD1125QZ (X32-1170-00 : IC6)

The CXDl125QZ is the digital signal processing LSI for the compact disc player, and has the following functions. All the digital signals for reproduction can be processed in- ternally with this one-chip design.

Bit clock reproduction by an EFM-PLL circuit. EFM data demodulation. Frame sync signal detection, protection and insertion. Powerful error detection and correction.

Interpolation with average value or by holding the previous value. Demodulaiton of sub code signal or error detection of sub code O. Spindle motor CLV servo. 8-bit tracking counter. CPU interface with a serial bus. Sub code O register. DIA interface output.

Block diagram L Y O C, U VI

VI Y m W V I

1 subcoae 1 1 ~ u b c o d e ~ u b c o r ~ e O

Sync Detector Demodulotor Regis ter

G F S

LOC K

FSW

M DP

MDS

MON

VCOO

XTAO

XTA l

VOO

VOD

TEST

XRST

MUTG

MD1

M D 2

MD3

PSSL

SLOB

vss

VSS

X'TAL circuit Digit01 Filter

timing generoior w (:xo:::z3

I !

C N l N

WDCK

LRCK

DOTX

CIRCUIT DESCRIPTION

Explanation of terminais

8

9

1 O

11

12

13

14

Function

Time constant switching output of output filter of spindle motor.

ONIOFF control output of spindle motor.

Drive output of spindle motor. Rough speed control in CLV-S mode and phase control in CLV-P mode.

Drive output of spindle motor. Speed control in CLV-P mode.

EFM signal input from RF amplifier.

Output for controlling the slice level of EFM signal.

Samples the GFS signal with WFCKI16, and outputs "H" when the level is high. When it is "L" for eight times, in arow, outputs "L".

15

16

17 - 18

19

I/O

O

O

O

O

I

O

O

Terminal No.

1

2

3

4

5

6

7

VCOO

VCOl

TEST

PD0

Vss

CLK

X LT

20

2 1

22

23

24

25

28

Terminal name

FSW

MON

M DP

M DS

EFM

AS Y

LOCK

DATA

XRST

CNlN

SENSE

MUTG

O

I

l

O -

I

I

CRCF

EXCK

SBSO

SUBQ

SCOR

WFCK

CFS

VCO output. f = 8.6436MHz when locked t o EFM signal.

VCO input.

(OV)

Phase cornparison output of EFM signal and VC012.

GND (OV)

Serial data transmission clock input from CPU. Data is latched at rising edge of a dock.

Latch input from CPU. Data (serial data from CPU) from the 8 bit shift register is latched in each

I

I

I

O

I

Serial data input from CPU.

System reset input. Reset at "L".

Input of tracking pulse.

Output of interna1 status in correspondence t o the address.

Muting input. I n the case where ATTM of interna1 register A is "L".

O

I

O

O

O

O

O

normal status when MUTG is "L" or soundless state when i t is "H".

Output of result of CRC check of sub code O. Clock input for sub code serial output.

Sub code O read-off clock.

Sub code Q output.

Sub code sync SO +SI output.

Write Frame Clock output. f = 7.35kHz when the frame sync is locked.

Output of display of lock status of frame sync.

CIRCUIT DESCRIPTION

Notes: C l F I C l F2 C2F1 C2F2 C2PO C2F L

RFCK

WFCK

: } Error correction status rnai i tor output for C l decode.

i } ~ r r o r correction status rnonitor output for C2 decode.

: C2 pointer signal. : Correction status output. Goes "H" when the currently corrected C2 series data cannot be corrected.

: Read frarne clock output. 7.35MHz when locked t o the crystal line.

: Write frarne clock output. 7.35MHz when locked t o the crystal line.

- PLCK : VC0/2 output. f = 4.3218MHz when locked t o the EFM

signal. UGFS : Non-protected frarne sync pattern output. GTOP : Frarne sync protect status display output. RAOV : 14 frarne jitter absorption RAM overflow and underflow

display output. C4LR : Strobe signal. 176.4kHz. - C210 : C210 invert output. C210 : Bit clock output. 2.1 168MHz. DATA : Audio signal serial data output.

CIRCUIT DESCRIPTION

Explanation of functions

CPU interface to three terminals, XLT, CLK and DATA. The address 1) Data input and data of each terminal are as shown in Table 6-2, and

Each register may be set by input of 4 bit address, and their functions are as follows. The contents of each register

4 bi t data from LSB in the timing that is shown in Fig. 6-2 become entirely O when XRST = "L".

k- Data Address -CI D A T A terminal

CLK terminal

X LT terminal

Registers Val id A -E

Timing chart for data input

2) Registers

0 Register 9 - New function control Controls the new functions added to the CX23035.

0 3 : ZCMT Switches the zero cross mute function ON/ OFF. Detai ls are described in "lnterpola- tion and Mute, Attenuate".

D2 : HZPD One of the defect countermeasures. Switches ONIOFF the function which rnakes the PD0 pin a high impedance (Z) for a maximum of 0.55ms from the rising edge of GFS. Details are described in "Countermeasures to de- fects".

D l : NCLV Switches between the old CLV-P servo and the new CLV-P servo by comparison with newly added base counter. Details are described in "CLV servo control".

DO : CRCQ Switches ON/OFF the function which out- p u t ~ the CRCF data to the SUBQ pin from the rising edge of SCOR to the trailing edge of SQCK. Details are described in "5) Subcode output".

0 Register A - Sync. protection, attenuator control D3 : GSEM Provided for switching framesynk. protection D2 : GSEL characteristics in correspondence to the time D l : WSEL 1 of playback and time of access. Details DO : ATTM will be descri bed in the paragraph of "EFM

demodulation". DO : ATTM Used for attenuating audio signals by 12dB,

and the details will be described in the paragraph of "DIA interface".

ORegisters B and C - Counter set, more significant 4 bits (register C) and less significant 4 bits (register B)

these registers are used for setting the tracking count value. the data of registers B and C are preset in the counter through the 4 bit buffer register assigned by address.

Accordingly, when data of either register B or C is input, the contents of both registers are preset in the counter simultaneously as 8 bit data (either buffer register is of "OLD" data.) D3 : DIV The dividing ratio of RFCK and WFCK in

CLV-P mode is fixed, and the phase is compared with R FCKl4 or WFCK/4 respectively, regardless of the status of D3, then output from the MDP pin.

0 Register D-CLV control D3 : DIV Used for setting the frequency dividing ratio

of RFCK, WFCK in the CLV-P mode. When D3 = O,, phase comparison of RFCK/4 and WFCKl4 is made, and when 0 3 = 1, phase comparison of RFCK/8 and WFCK/8 is made, and output is made out of MDP terminal in each case.

D2 : TB Used for determining the period of bottom hold in the CLV-S and CLV-H modes. Bottom hold is made in the period of RFCK 132 when D2 = O or in the period of RFCK/ 16 when D2 = 1.

D l : Tp Used for setting the period of peak hold in the CLV-S mode. Peak hold is made in the period of RFCK/4 when D l = O or in the period of RFCK/2 when D l = 1.

DO : GAIN Used for setting the gain of MDP terminal output in the CLV-S and CLV-H modes. I t is -12dB (time of 314 out of the period of RFCK/2 is of high impedance) when DO = O or is OdB when DO = 1.

CIRCUIT DESCRIPTION

0 Register E-CLV mode It is as shown in Table 6-2.

The details of each mode wil l be described in the paragraph o f CLV servo control.

+ l Register 9

Register

name

9"'

Ai2

B

C

D I 3

E*4

+2 Register A

A d d l ~ g

D7-D4

1 0 0 1

1 O 1 O

1 O 1 1

1 1 O O

1 1 0 1

1 1 1 0

Command

New function control

Sync protection,attenuator control

Counter set, Less significant 4 bits

Counter set, More significant 4 bits

CLV control

CLV mode

GSEM GSEL Frame

1 13

D n = 1

Zero-cross MUTE on

PDC pin is "Z" at the trailing edge of GFS

CLV-P servo for the base coanter

SUBQ = CRCF at the raising edge of SCOR

WSEL Clock

D n = O

Zero-cross MUTE off

PDC pin is always active

CLV-P servo for the frame sync signal

CRCF is not superimposed on SUBQ

ZCMT

HZPD

NCLV

CRCQ

SENSE

terminal

Z

Z

COMPLETE

COUNT

Z

Pw 1 6 4 ,

Data

0 3

D2

D l

DO

*3 Register D

DO

CRCQ

ATTM

Tc0

Tc4

GAIN

DIV

TB

+4 Register E

1 Mode 1 D3-DO 1 MDP terminal 1 MDS terminal IFSW terminal 1 MON terminal 1

CLV mode

D l

NCLV

WSEL

Tc1

Tc5

T p

D 3

ZCMT

GSEM

Tc3

Tc7

D IV

Tp

GAlN

D 2

HZPD

GSEL

Tc2

Tc6

TB

D3

D2

O 1 RFCK/4 & WFCK/4 Phase comparison frequency

1 1 RFCKl8 & WFCK/8 in CLV-P mode

D l

DO

STOP 1 0 0 0 0 1 L

O

1

r

BRAKE

CLV-S

CLV-H

List of registers

O

1

O

1

Z

CLV-P 1 1 1 1 1 1 CLV-P 1 CLV-P

RFCK/32

RFCK/16

KICK 1 1 0 0 0 1 H

1 0 1 0

1 1 1 O

1 1 0 0

Bottom hold period in

CLV-S. CLV-H mode

RFCK/4

RFCKl2

-12dB

OdB

L

Z

Peak hold frequency in

CLV-S mode

Gain at MDP terminal in

CLV-S. CLV-H mode

L

Z

L

C LV-S

CLV-H

H

CLV-A

L

Z

Z

Z

Z : High impedance

0 1 1 0

H

H CLV-S or CLV-P

L

L

i

H

H

H

Z or CLV-P L or Z

CIRCUIT DESCRIPTION

3) Trakcing counter O) is loaded in registers and the address is set at "6". This counter is provided for facilitating track jump. a signal (COMPLETE) that is of HlGH level up to "n"

Load the number of tracks to be jumped in register B and pulses an.3 is of LOW level after "n" pulses is output of

C. Count of CNlN pulses is started at raising edge of XLT SENSE terminal. When the address is set at "C", signal

after i t was loaded in either register B or C. (m) of CNINl2n ( H z ) is output.

When n (n = 256 is meant when register B = register C = The tracking counter timing chart is shown in Fig. 6-3.

Register X n (n = 256 when "O" is loaded) B,C

X L T terminal

l

I

C N l N terminal

COMPLETE I X I I

I

COUNT X I I I I 1

Tracking counter timing chart

4) SENSE when the pulse width after bottom hold is over

The following signals are output from SENSE terminal 63, and is of HlGH level otherwise. It is used

depend ing on the address of D7-D4. for detection of a drop in the speed of the

1. COMPLETE : Address is "B"; Shown in Fig. 6-3. spindle motor after braking and so on.

2 . COUNT : Address is "C"; Shown in Fig. 6-3. Note : Address setting is determined only by the data that 3. PWZ64 : Address is "E"; this signal is of LOW level corresponds to D4-D7 which can be input from

DATA terminal shown in Fig. 6-2.

D7-D4 B E Others

I l I

I I I l l I Z : High impedance

SENSE terminal COMPLETE

Timing chart of SENSE terminal

CIRCUIT DESCRIPTION

(CI Timing of SCOR, CRCF, SQCK, SUBQ

SQEX= "H" level

SQCK

SUBQ 1 *5 X Q4 X 0 3 )( 0 2 )( Q1 X Q8 X a 7 7 X

SQEX= "L" level '5 : CRCF when CRCQflag is "1". undefined when "0.

so S I

SQCK

SUBQ X *6 XQlx Q2 )( 0 3 X 0 4 X 0 5 x Q 9 6 x Q 9 7 x x '6 : CRCF when CRCQ flag is "1", 098.01 when "O".

(2) Timing chart of sub code outputs

80bit shift register SUBQ terminal

4-bit replacement

SQCK terminal

SQEX terminal

CIRCUIT DESCRIPTION

EFM demodulation made by TRI STATE out of PD0 terminal. The mean value 1) Playback of bit clock by EFM-PLL circuit of PD0 terminal is about 112 VDD if synchronized, but

The EFM signal read out of the optical block contains the mean value drops when VCO becomes higher. On the a clock cornponent of 2.16MHz. Therefore, it is possible to other hand, the mean value increases when VCO becornes take out a bit clock (PLCK) of 4.32MHz synchronized less. with this clock by the EFM-PLL circuit. The timing charts of EFM terminal, EFMO, PLCK and

At each edge of EFM signal, phase comparison is made PD0 are shown in Fig. 6-7. with PLCK, which is 112 of VCO, is made and output is

(a) When EFM signal ahd VCO are synchronized

EFM terminal 1 I l

EFMO 1 1 1 - I I .l I l I I

Z I , ;---- P D 0 terminal - - - - n - I - - l u--

l l I l

Z : High irnpedance

PLCK I I 1 I

(b) When VCO is higher than EFM signal

1 1 I I I

EF M terminal

l I l I I I l

EFMO

I I ! PLCK 1 1 I I I I I

! I

I I I I 1 I I I

P D 0 terminal

Z : High irnpedance

(c) When VCO is less than EFM signal

EFM terminal

I I EFMO 1 1

I I I I 1 I I

PLCK I I I 1 I I I 1 I I l l I I I I I I I I I I I I

P D 0 terminal - J-L - I I I - 1 u---- Z : High impedance

Timing charts of EFM-PLL circuit

CIRCUIT DESCRIPTION

2) Detection, protection and interpolation of frame synchronizing signals There are cases during recording where the same pattern

is detected in the data due to the influence of drop-out and jitter, even if a pattern that is same as the synchronizing signal will not appear.

On the other hand, there also are cases where original frame synchronizing signal is not detected. Therefore, protection and interpolation are required besides detection.

The edge portion only of EFM signal (EFMO) latched with PLCK is converted to "1" and the rest to "O", and then input is to a 23 bit shift register and a frame synchronizing signal is detected.

In order to protect a frame synchronizing signal, a window is provided and the same patterns outside of this window are removed. This width can be selected with WSEL. If no frame synchronizing signal is located in this window, interpolation is made with a signal produced by 588-mal counter (4.321 8MHzl588 = 7.35kHz)

A 4 bit counter for counting the number of these frarnes to be interpolated is provided, and when its count reaches the level selected with GSEL, GSEM, the window is ignored and the 4 bit counter is reset with the next frame synchronizing signal. the GTOP terminal is of "H" while this operation is performed. Further, GFS terminal is of "H" when the frame synchronizing signal generated by the 588-mal counter for making interpolation is synchronized with the frame synchronizing signal from the disc.

The frarne synchronizing signal before passage through the window or the wondow is output out of UGFS (DA05 terminal at the time when PSSL = L.)

3) EFM demodulation 14 bit data is taken out of the 23 bit shift register and is

demodulated to 8 bit data through 14 + 8 conversion circuit composed of array logics. Then a write request (WREQ) signal is output to the RAM interface block, and the data is then output to the data bus (DB08- DBO1) terminals) of the RAM in accordance with the OENB signal transmitted from said block.

WSEL Window width

13 clock

17 clock C-i

Sub code demodulation 1) Sub code demodulation

synchronizing signals SO, SI of 14 bit sub codes are detected out of the 23 bit shift register. and sampling is made in the timing that is synchronized with WFCK.

After delay of $0 by one frame, SO + SI is output out of SCOR terminal and SO . SI is output out of SBSO terminal (only when SCOR = H.)

Data (P-W) of sub' codes only is input to the register in the timing synchronized with WFCK after EFM demodulation; and sub code Q is output out of SUBQ terminal, and at the same time, i t is loaded in the 8 bit shift register and is output out of SBSO terminal in correspondence to a clock from EXCK terminal.

The detials of this timing will be shown in the paragraph of CP.U interface. 2) Sub code O error detection

The CRC sub code result is output from the CRCF pin in synchronism with the SCOR pin. I t goes "L" when an error is detected. A t the same time as the CRCQ flag is "l", the CRCF flag is output frorn the SUBQ pin during the time frorn the rising edge of the SCOR pin to the trailing edge of the SUBQ pin. This timing is detialed in "CPU interface".

GSEM

O

O

1

1

The timing for write request signal (WREQ), Write Frarne Clock (WFCK), etc. is generated based on the protected and interpolated frame synchronizing signal.

GSEL

O

1

O

1

Number of frames t o be interpolated

2 frames

4 frames

8 frarnes

13 frarnes

UGFS (PSSL = "L")

Window

Window

Frame synchronizing signal before Passage through window.

Window

CIRCUIT DESCRIPTION

RAM interface (generation of external RAM address) 1) Request from EFM demodulation block (Write RAM

request) When one symbol of demodulation is complete in the

EFM demodulation block, the EFM demodulation block requests to write data to the external RAM to the RAM interface block. This request is WREQ signal. This block gives priority orders to requests from other blocks and processes these requests.

When EFM write request is received, an address is generated to the RAM and Write Enable state is produced. Furthermore, a data output instruction is issued against the EFM demodulation block. This instruction is OENB signal.

Clocks of .PLL system are used for EFM block and for requests (WREQ) from EFM block, but clocks of X'Tal system are used for processing thereafter. 2) Request from DIA converter output circuit (Read to DIA request)

This is a de-interleaved data request issued out of the timing generator in this block. This request is of the highest priority among al1 requests, and addresses of three types are generated against this request.

This request is generated once every 24 periods based on the period of system clock C212 (8.4672MHzl4). The data output out of the RAM is C2 pointer first, less significant 8 bits out of 16 bits and finally more signifiant 8 bits. 3) Request from error correction block (ClIC2 correction,

pointer RMI) The error correction block requests the data located

on the system (Cl/C2) to be corrected. Furthermore, there is a request to rewrite incorrect data to correct data. In addition, there is a request for pointer R/W which indicates reliability of data.

These requests are made by the 8 bit data directed to the RAM interface block from the error correction block. The requests from the error correction unit are of the lowest priority among requests of three types. After acceptance of a request, data from RAM is directed to the 3rd clock of C212.

The data of acceptance of a request is output to the error correction block as a PREN signal. This block generates the address of the requested data, and controls R/W of the RAM at the same time.

4) Address generation The data after EFM demodulation is data subjected to

interleave processing. This interleave processing is subjected to data lag by the unit of a frame. Data of 108 frames are required for de-interleave. In other words, for obtaining one frame of audio data played in a certain length of time, data of 108 frames after EFM dernodulation are required. Further, the system data of Cl /C2 is of the systern in the process of application of interleave, and therefore, is included in 108 frames.

Data in practice are generated continuously. That is, de-interleave should be updated by the unit of a frame. Therefore, Read~Write base counters are required. This base counter performs counting by the unit of a frarne.

The writer base counter is used only at the time of EFM data writer. The address directed to the external RAM is deterrnined by the relative lag value to EFM demodulation data and their number of frames. 5) Priority of address generation request

The system control block determines priority of address generation requests made to the RAM interface block.

The priority order is as follows beginning with higher priority.

1. Read to DIA request 2. Write to RAM request 3. Cl lC2 request

The number of times of requests is as follows. 1. Requests of 12 times in the frame section

The number of times of address generation to i t i s 36 times.

2. Requests of 32 times in the frame section .The number of times of address generation to it is 32 times.

3. Maximum number of times of request (Cl Double error correction, C2 pointer copy) Read R/W 64 times, Pointe R/W 65 times in one frame section The number of tirnes of address generation to it is 129 times.

288 C212 (clocks) are included in a frame. and the number of times of operation of the RAM in it is 197 tirnes at maximum. In the system control block, against request 1, the 'timing of its occurrence is reserved in advance. Requests 2, 3 are not accepted in this timing. When requests 2, 3 are generated simultaneously, priority is given to request 2, and if a requestis generated during execution of either request, priority is given to the job in execution.

6) Jitter rnargin The EFM demodulation data is synchronized with data's

playback system (PLL) as described earlier. Accordingly, i t includes disturbance (wow.flutter, etc.) of disc rotation servo, etc. It is loaded to the external RAM. As the data taken out of the RAM is synmchronized with the clock of X'Tal system, this RAM is subjected to time axis correction.

However, the limit of time axis correction is determined by the capacity of the RAM. In this system, other data is destroyed when readlwrite frames are spaced apart by 115 frames. In such a status how the playback sound is cannot be guaranteed. The base counter monitor is provided in order to avoid it.

In other words, when the difference between read base counter and write base counter exceeds 114 frames, the write base counter is set in the value of the read base counter. As a result, there is no case where data without error correction is output to the DIA.

The RAOV signal is of "H" for one frame (WFCK) section when the difference between base counters ex- ceeded +4 frames.

CIRCUIT DESCRIPTION

8) The flow of data with the external RAM is as follows.

A data request is made frorn the correction block to the RAM interface block.

The RAM interface block accepts the request with the operating situation of the entire system observed. The address of the requested data is generated to the external RAM.

ReadANrite of the correction block and RAM data are enabled.

Error correction 1) The error correction block makes correction up to

double errors with each of C l correction and C2 correction.

2 ) This system adopts a unique pointer erasure method in order to minimize erroneous correction. Accordingly, the external 16k RAM stores these pointer data in

addition to audio data. 3 ) The pointer generated in C l correction is called Cl

pointer and the pointer generated in C2 correction is called C2 pointer.

4) When the data of Cl system is judged as reliable, a Cl pointer is set in this systern.

5) During C2 correction, whether correction is to be made or not to be made and whether the data is reliable or unreliable are judged from .the error location, locations and number of C l pointers obtained through computa- tion. A C2 pointer is set against an unreliable word (16 bits).

6) The word in which a C2 pointer was set is subjected to previous value hold or mean value interpolation when it is output out of this LSI.

7) Terminal C2FL becomes "H" when one or more C l pointers are set in the data included in the C2 system at the time of C2 correction. C2FL is reset to "L" when a period of minimum 472ns after deactivation of terminal RFCK. C2FL is the AND of C2F1 and C2F2.

Note : 47211s : One period of 2.1 168MHz

9) When PSSL is set at "L", a signal that is capable of monitoring error correction is output. C l F I . C l F2, C2F2 output to DA01 -DA04 are these monitor signals. This signal is reset to "L" when a period of minimuni 472 ns has elapsed since deactivation of RFCK. The levels and meanings of these signals at the time of

deactivaiton of RFCK are as follows.

Cl correction status

No Error

Siiigle error correction

Double error correction

Irretrievable errcir

C l F l

O

1

O

1

C 2 F 1

O

1

O

1

C1F2

O

O

1

1

C2 correction status

No Error

Single error correctioii

Double error correctiori

Irretrievable error

C 2 F 2

O

O

1

1

C 2 FL

O

O

O

1

CIRCUIT DESCRIPTION

CLV servo control The spindle motor revolution is controlled with one

selected out of the following seven modes in accordance with a cornmand from the CPU. CLV is the abbreviation of Constant Linear Velocity. The output is composed of MDP terminal for controlling synchronization of velocity and phase, MDS terminal for controlling synchronization of velocity, FSW terminal for making selection of filter constant and MON terminal for controlling motor ON/ OFF.

1 ) STOP : Register E = 0000'6 (B means binary) Mode for stopping the spindle motor. MDP = FSW = MON = "L", MDS = "Z"

2) KlCK : Register E = 1000'6 Mode for running the spindle motor in forward direction. MDP = MON = "H", MDS = "Z", FSW = "L",

3) BRAKE: Register E = 1010'6 Mode for running the spindle motor in reverse direction. MDP = FSW = "L", MDS = "Z", MON = "H".

Typical control of spindle motor

MON

FSW

MDP

,.,,,, or ,,L,, in "Z" in CLV-P mode CLV-S mode " /

MDS - - - - - -- - - - - .- - - - - - - -----

Cornmand from CPU :

STOP KICK CLV-A CLV-H CLV-A BRAKE STOP

At the time of high speed access

Automatic switching between CLV-S and CLV-P

Activation i s made quicker by applying Rotation is quickly stopped by apply ing

forward rotational torque to the motor. reverse rotational torque to the motor.

Z : High impedance

"1" in CLV-S mode "1" in CLV-P mode

-

"Z" at the time' ,,L" or ,.Z,, at the'time uH,,, ,,L,t or ,,Z,, of-12dBinCLV-Smode

"H" or "L" at or at the tirne in Ci-v.' the time of O ~ B of OdB J P' - - - - . - - - - ---

CIRCUIT DESCRIPTION

TP : RFCKl2 or RFCK14 in the case of CLV-S. F8M1256 in the case of CLV-H

TB : RFCK116 or RFCKl32 in the case of CLV-S, CLV-H

Peak hold

F, JJi \ Initial StatUS

1 $&

j G

I ' I I I I

I 1 I I

I - 1

1 7

O \

Latch

F (22 F and up)

FF (23 and up)

Initial status

Timing chart in CLV-S, CLV-H mode (2)

14- < L

Initial status

( 1

1

1 ,

( 1 !'

\\\ \, \ 4 TB c

\

\

- TP -

F F (22 and up) 1 O

FF (23 and up)

Bottom hold

F F (22 and UP)

O

FF (23 and up) 9

Initial status

1 1 t

' 1

,

\

[, 1 -

CIRCUIT DESCRIPTION

4) CLV-S : Register E = 1 100'8 Rough servo mode used at the time of start of rotation, at the time of track jump and also when the EFM-PLL circuit is unlocked due to another reason. When the period of VCO's oscillation frequency 8.6436MHz is expressed as "T", the pulse width of a frame synchronizing signal is "22T" during specified revolution, and i t is the maximum pulse width in a period of RFCK. In practive, however, there are pulses having widths over "22T" due to drop- off of EFM signal due to other reasons, and the frame synchronizing signal cannot be correctly detected unless such pulses are removed. There- fore, the maximum value (peak) of the pulse width of EFM signal is detected (called peak hold) in the period of RFCK/2 or RFCK/4, than the minimum value in this peak is detected (called bottom hold) in the period of RFCK/ 16 or RFCK/32, and this value is used as the frarne synchronizing signal. "Lu is produced out of MDS termipal while the frame synchronizing signal is "21T" or less, "Z" when i t is "22T", or "H" when it is "23T" or more. Either OdB or 12dB can be selected as its gain. MDS = "Z", FSW = "Lu, MON = "H",

5) CLV-P: Register E = 11 11'8 PLL servo mode. When the NCLV of register 9 is "O", the phase of the WFCKl4 signal and the phase of the RFCK/4 signal are compared and output to the MDP pin. When NCLV = "lu, 114 of the base counter frame frequencies at the Write side and the Read side are phase-compared and output to the MDP pin. I t goes "H" when WFCK is slow, "L" when i t is fast, and is "Z" when synchronized. I f the 8.467212MHz period is T, and the time when WFCK is "H" is tHW, then the MDS pin outputs a signal which goes "H" during the time from the trailing edge of WFCK to the time represented by (~Hw-279T) X 32, and then goes "L" until the next trailing edge of WFCK. MDS 5 "H" when tHW = 279T. MDS = "L" when tHW 2 279T. The MDS pin varies between 32T and 544T. in 32T steps, when 280T 5 ~ H W 5 296T. For example, when synchronized (rotating at the standard speed), that is when tHW = 288T, a 7.35kHz signal, with a duty cycle of 50% is output. FSW = "Z" , MON = "H".

a t h (22 and up) /-"+'-l

RFCK terminal

MDP terminal (when OdB)

MDP terminal (when -12dB)

Timing chart in CLV-S. CLV-H mode (1 1

CIRCUIT DESCRIPTION

6) CLV-P : Register E = 11 11 'B PLL servo mode. Phase comparison of signals WFCK/4 and RFCK/4 or WFCK/8 and RFCKl8 is made, and output is made out of MDP terminal. "H" when WFCK has delayed, "L" when WFCK is fast, and "Zn when synchronized. When the period of 8.467212MHz is expressed at T and the length of time when WFCK is "H" is expressed at tHW,. such a signal that is of "Hu during (t HW-279T)

x 32 with 7.35kHz as a period and that is "L" during the remaining time is produced out of MDS terminal. MDS = "L" when tHW 5 279T. MDS = "H" when tHW 5 297T. When 280T ': tHW 5 296T, the MDS terminal changes in 32T steps from 32T to 544T. When synchronized, for instance, that is, when tHW = 288T, a signal of 7.35kH.z of DUTY 50% is producerl FSW = "Z", MON = "H".

MDP terminal

WFCK14 i 1 (or WFCKl8) I I

Z : High impedance

MDS terminal (The Period of 4.2336MHz is expressed as "TM.)

(1 ) When rotating at specified velocity

1- 288T

WFCK I 1 I I l I I

2 8 8 ~ +

M DS I

(2) When rotation becomes fast 2 8 0 ~

WFCK I I I l I I

(3) When rotation becomes slow

WFCK I I I l I

Timing chart in CLV-P mode

CIRCUIT DESCRIPTION

7) CLV-A: Register E = 01 10'B The mode used for normal play status. The GFS signal ("H" when locked, "L" when unlocked), after frame sync detection, protection and insertion block, is sampled at WFCK/ 16, and functions in CLV-P mode when the signal is "H". When the "L" signal continues for 8 times, the mode is automatically changed to CLV-S mode. When in the CLV-S mode, setting of the peak hold period, and setting of the period and gain of the bottom hold of the CLV-S and CLV-H are performed in register D, and the selection of each mode is perfomred in register E. The description of these registers are detialed in "CPU interface". Note: When PSSL = "Lw, DA07 pin outputs WFCK/4 or WFCK/8 as FCKV, and DA08 out- p u t ~ EFCKl4 or EFCKW as FCKX.

8 Interpolation and DIA converter interface. 1) Interpolation circuit block

3 byte data can be obtained with a Read to DIA request. They are C2 pointer, less significant 8 bits and more significant 8 bits. The total 16 bits constitute the data generated per sampling (2's complement.)

The C2 pointer expresses the reliability of this 16 bit data. Therefore, data with C2 pointer is subject to interpolation in this block.

O : Without C2 pointer X : With C2 pointer

Mean value interpolation

1 B = ( A + C )

2

1 H = - ( E + I ) : When pointers are continuous

2

8) CLV-A' : Register E = 01 01'8 New auto servo mode added to the CX23035. The difference between CLV-A. and CLV-A is in the rough servo system. With the old rough servo system, the EFM pattern is meas- ured by a crystal and the servo is applied so that the width of the sync pattern is a fixed value, and the rotation speed of the spindle motor is roughly fixed. In this case, if the value is out of the VCO capture range, the VCO never locks with the EFM. With the new rough servo system, a VCO is used for rneasurement instead of a crystal. If the VCO center is shifted from true center the VCO tends t o lock, since the rotation of the spindle motor varies in the same direction. The new rough servo functions'only in CLV-A' mode. The rough servo in CLV-A mode and CLV-S mode is the old rough servo.

16 bit data is alternately output to L-ch and R-ch, R-ch data is output in the section in which LRCK is "L" and L-ch data is output in the section in which LRCK is "H". C2PO signal outputs C2 pointer to the 16 bit data directed to DAO1-DA16 (PSSL = H), DA16 (PSSL = L). In other words, it means that the 16 bit data that is output when C2PO is "H" is interpolated data.

2) Explanation of muting and attenuator In the muting block i t is possible to mute (- dB) or

attenuate (-12dB) the audio signal in accordance with the MUTG terminal and ATTM signal of the CPU interface block.

-12dB

- - d B See Note

-12dB See Note

NOTE : When the MUTG is set to "H" level with the NCLV flag set to "O", the read base counter value is continuously loaded into the write base counter as well as the muting. Except at CLV-A, CLV-P, CLV-S, or CLV-A' with the NCLV flag set to "l", the base counter is loaded.

Previous value hold

F = G = E

CIRCUIT DESCRIPTION

Mode setting MD3 pin : Mainly for selection of the digital filter func- The various kinds of mode can be set by combining the tion.

following pins. (Refer to the table below.) PSSL pin : Mainly for selection between serial and MD1 pin : Mainly for selection of the oscillator clock at parallel output.

the XTAl or XTAO pin. SLOB pin : Selection between offset binary and 2's MD2 pin : Mainly for selection of the digital out func- complement.

tion.

(Note) 8M/16M : Selection of clock, XTAL or XTAO. 8.4672MHzI 16.9344MHz DO OFF/ON : Digital out OFFION DF OFFION : Digital filter OFFION

1) Selection of clock The oscillator clock for XTAl and XTAO is available

at 16.9344MHz and 8.4672MHz. However, when digital out is used, the clock must be set to 16.9344MHz. 2) Selection of digital out (Refer to "DIA interface")

When digital out is set to ON, a signal conforming to the DIA interface format is output from the DOTX pin. When i t is set to OFF, the DCTX pin outputs the WFCK signal. In the DP-969, this function is fixed to ON. 3) Selection of digital filter

When the digital filter function is set to ON, the DAC interface signal are al1 set to double speed. 4) Selection of parallel outputlserial output

When the parallel output is selected, DAO1 to DA16 pins output the 16-bit parallel data. When the serial output is selected, DAO1 to DA16 pin output the following signals respectively.

DAO1 + C l F I : Error correction status monitor DA02 + C l F2 : 1 output at C l decode. DA03 + C2F1 : Error correction status monitor DA04 -* C2F2 : 1 output at C2 decode. DA05 + C2FL : Correction status output,

C2FL = C2FI.CZF2.

PIS : Parallel outputlserial output OB/2's : Offset binary/2's cornplement CD ROMIAUDIO : Compatible t o CD ROM/Compatible to audio

DA06 + C2PO : C2 pointer signal. DA07 + RFCK : Read frame clock signal, 7.35kHz

when locked to the crystal line. DA08 + WFCK : Write frame clock signal, 7.35kHz

when locked. - DA09 + PLCK : 112 of the divided signal from the

VCO pin, 4.3218MHz when locked. DA1 0 + UGFS : Non-protect frame sync signal. DA1 1 + GTOP: Frame sync protect status display

signal. DA12 + RAOV : Jitter margin over or underflow dis-

play signal. DA13 + C4LR : 4 times the LRCK signal. - DA14 + C210 : Bit clock (invert signal of C210). DA I 5 + C210. : Interna1 system clock (4.2336MHz

when DF is ON, 2.1 168MHz when CXD11250 or DF is OFF).

DA16 + DATA : Serial data output (MSB or LSB first output).

CIRCUIT DESCRIPTION

5) Selection of OFFSET BINARYIS'S COMPLEMENT When the SLOB pin is "H", an offset binary signal is

output, and when it is "L", a 2's complement signal is output. 6) Selection of CD ROMIAUDIO cornpatibility

When MD1 = MD2 = MD3 = "H", the player is compatible with a CD ROM and outputs the C2 pointer for each byte. At the same tirne, the average value interpolation and the previous value holding operations are not perforrned. For example, when there is an error in the upper 8 bits of the 16 bits, only the C2 pointer corresponding to the upper 8' bits goes "Hu, and the lower 8 bits are processed as the correct data.

DIA Interface The player incorporates a DIA interface output (digital

output) and the digital signal is output frorn the DOTX pin. The digital signal is output after passing through interpolation, mute and attenuator circuits. The 4 control bits (IDO, ID1, COPY, EMPHASIS) in the C-bit channel status perform a CRC check and are revised only when it's OK.

Counterrneasures to defect To counter a defect, the PDC pin is set to "Hi-Z"

during the time until GFS goes "H" again after inverting from "H" to 'IL" or after approx. 0.55rns has elapsed. However, this operation is perforrned only when the HZPD flag of register 9 is "1 ". When HZPD = "O", i t will never be set to "Hi-Z".

The signal switching between the rough servo in the CLV-A or CLV-A' mode and the PLL servo is output from the LOCK pin. After the GFS signal is sampled at WFCKI 16, and when the signal is "l", the LOCK pin goes "H", when a "O" is present 8 times in a row, the LOCK pin goes "LU.

This operation is sirnilar to that for the FSW pin. How- ever, while the FSW outputs a fixed signal when not in CLV-A' mode, the LOCK pin always output the above signa 1.

Timing chart

- WDCK \ / 7 /

APTR

Timing chart of audio output

r

APTL /

*PSSL = "L"

CIRCUIT DESCRIPTION

DAOI-DAM mfl )i lm)mA 4-P-

I 1 Min 47211s

DAOl -DA04 (C IF I , C l F2, C2F1, C2F2) are cleared when a period of minimum 472 ns has elapsed since RFCK was deactivated. ANDing signal of C2F1 and C2F2 is output out of C2FL termnal.

WFCK \

I l

35 period with DA09 I

-(bA09 is of about 4.32MHz) A

WFCK 7 1 \

WFCK \ 1 \ \

RFCK \ \ / \ \ 1

Timing chart of DAOl -DA1 6 output when PSSL="L"

CIRCUIT DESCRIPTION

1 l I C2PO (DA06') when compatible C2PO corresponding to the Lch 16-bit data with audio K

I I

C4LR (DA1 3)

I I \

- WDCK /

L X (DAlO) -

Timing chart of C2PO output (when PSSL="L")

/

C2PO (DA06') when compatible C2PO corresponding to the upper C2PO corre~ponding to the lower

with a CD-ROM 8-bits of L-ch data 8-bits of L-ch data

' RAOV becomes "H" for one frame (synchronized with WFCK) when a jitter that exceeds I 4 frarnes is generated between RFCK and WFCK.

DA16* (DATA) X Lch (MÇB) 16

I

w F c K 3 ~ [ ~ [ ~ ~ RAOV

l

Min 47211s

Timing chart of RAOV output

CIRCUIT DESCRIPTION

Static RAM CXK5816SP-12L

Block Diagram

Terminal connection diagram

A 7

A 6

A5

A4

A 3

A 2

A l

AU

1 0 1

1 0 2

l 0 3

GND

V p r

GND

Ciiluniri Drc i i liv

(Top View)

Explanation of terminalç

Terminal name

AO- A10

1/01 - 1/08 - CE - WE - OE

Vcc

END

Function

Address input

Data input/output

Chip enable input

Write enable input

Outfit enable input

+5v

Ground

5 1

CIRCUIT DESCRIPTION

Reset IC: M51951ASL (X32-1170-00: ICI 1)

Output

Operating Waveform

Power voltage

DA Converter: PCM56P-K (X25-3050-00: ICl , lC2)

Block diagraml


CIRCUIT DESCRIPTION

OUT

Explanation of terminais

1

Function

Voltage output

Feedback resistor.

Surnrning junction (op arnp. input).

Analog ground.

Current output.

MSB adjustment terminal.

Potentiorneter terminal.

Analog positive power supply.

Terminal name

Vout

RF

S.J

ANA GND

lout

MSB ADJ

V POT

+ Vcc

Terminal No.

9

1 O

11

12

13

14

15

16

Function

Analog negative power supply.

Digital ground.

Logic positive power supply.

No connection.

Clock input.

Latch enable control input.

Data input.

Logic negative power supply

Terminal No.

1

2

3 4

5

6

7

8

Terminal name

-Vcc

DIG GND

+ V L

NC

C K

LEC

DATA

-V L

CIRCUIT DESCRIPTION

Digital filter: SM5804D (X25-3050-00: ICI 4) Block diagram

CIRCUIT DESCRIPTION

Explanation of Pins Wi th this LSI, the switching between the serial and parallel in- of the funct ions o f pins X I t o X I 6 and Yi t o Y16 rnay be

putsloutputs is perforrned by the K L and K L pins. Some changed by this switching.

AH the terrninals o f this uni t funct ion w i th PlSL = H. Note: ip designates an input jack with a pull-up resistor.

55

Pin No.

1

2

3

4

5

6

7

8

9

1 O

11

12

13

14

15

16

17

18 -

19

20

2 1

22

23

24

25

26

27

- PlSL = H

Pin Name - SIMD

- SIE0

- SI EA

BCKl

SID

44CI

ABSL

TEST 1

TEST 2

- 4SSL

- CKSL

Vss

XT

- XT

CKO

- SCSL

m - POMD

s'mm

LSBo

(NCI

110

i P

i P

[P

[P

i P

i P

1 P

1 P

i P

ip

1 P

A

l

O

O

1 P

1 P

i P

i~

1 P

Function

Serial input mode switching.

Parallel data input (Bit 5) .

B CH serial input enable.

Parallel data input (Bit 4 ) .

A CH serial input enable.

Parallel data input (Bit 3).

Serial input bit clock input.

Parallel data input (Bit 2).

Serial input data

Parallel data input (LSB).

44 1 kHz sync clock input. - ABSL= H-44 CI clock, HIL = A CHIE CH -- ABSL=L-44 CI clock, HIL = B CHIA CH.

Test input 1 (Normally Open).

Test input 2 (Normally Open). - -

Normally 4SSL= H or Open. 4SSL= L when input is 16.9344 MHz or 17.2872 MHz. - CKSL= H-External clock input. - CKSL= L-X'tal oscillation.

GND power supply pin (O V).

m= H-Clock input. C m = L-X'tal oscillation input. - CKSL= H-(Open). C m = L-X'tal oscillation output.

Clock output -

System clock 96 fs-SCSL= H System clock 98 fs-== L.

Open. - POMD=H-Normal parallel output mode. - POMD= L-ln-phase parallel output mode

m= L with serial output. - - LSBO= H-MSB-first serial output. LSBO = L-LSB-fis serial output.

(NC)

- PISL = L

Pin Name

X 5

X4

X3

X 2

X 1

f--

a

a

a

t-- - (NC)

(NC)

(NC)

A CH deglitch control output.

B CH deglitch control output.

A CH serial data output.

Parallel output iinverted, LSB).

110

ip

ip

ip

ip

ip

ip

ip

ip

ip

. IP

ip

,' /

I

O

O

ip

ip

ip

ip

iP .

O

O

O

(NC) - (NC) i

(NC) - DG A

DGB

SODA

O

O

O - Y 1

CIRCUIT DESCRIPTION

d

Function

B CH serial data output.

Parallel output iinverted, Bit 2) .

Pin No.

28

29

30

3 1

3 2

33

34

3 5

36

3 7

38

39

40

41

42

43

44

45

46

47

48

49

- PlSL = H

5 6

- PlSL = L

Pin Narne

SODB

Pin Narne

- Y2

110

O

(NC)

BCKO

CO 1

CO2

CO3

CO4

(NC)

(NC)

(NC)

iNC)

(NC)

(NC)

(NC)

(NC)

(NC)

- POSL

YOFB

Voo

x m

KL

(NC)

110

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

ip

. IP

,- . IP

ip

lnternally short-circuited to VDO. Not to be connected externally.

Serial output bit clock output.

Parallel output (inverted, Bit 3).

Serial output control clock 1.

Parallel output iinverted, Bit 4 ) .


Parallel output iinverted, Bit 5 ) .

Serial output control clock 3

Parallel output (inverted, Bit 6) .



(NC)

Parallel output iinverted, Bit 8).

iNCi


(NC)


(NC)

Parallel output (inverted, Bit 1 1).

(NC)


(NC)


(NC)


(NC)

Parallel output iinverted, Bit 15).

(NC)

Parallel output (inverted, MSB).

m= H-Serial output systern. - POSL= L-Parallel output systern.

KjFB= H-2's cornplernent display output. mTFB= L-Offset binary display output.

+ve power supply pin (5 V). - XOFB= H-2's cornplernent display input. m B = L-Offset binary display input.

m= H-Serial input systern. P~SL = L- parallei input systern.

iNCI

O

O

O

O

O

Hz

Hz

Hz

Hz

Hz

Hz

Hz

Hz

Hz

i~

1 P

/

IP

i P

- Y 3

vf

- Y5

- Y 6

Y7

Vg

- Y 9

- Y 1 O

- Y1 1

v.7

n-3

- Y 14

- Y15

- Y16

-

CIRCUIT DESCRIPTION

- Senal Output Timing (SOMD = L, SCSL = H, system clock = 4.2336 MHz)

P I N @ SODA

@ s o D e

@) BCKO

0 CO 1

@ c 0 2

@ CO3

@ CO4

@$ DGA

@ D G 0

Function

(NC)

Parallel data input (MSB).

INC)


(NC)

Parallel data input (Bit 14 )

(NC)

Paraltel data input (Bit 13) .

(NC)

Parallel data input (Bit 1 2 ) .

(NC)


(NC)

Parallel data input (Bit 1 0 ) .

(NC)

Parallel data input (Bit 9)

(NCI

Parallel data input (Bit 8 )

(NC)


LSBl= H- MSB-first serial input - LSBl = L- LSB-first serial input


Pin No.

5 0

5 1

5 2

5 3

5 4

5 5

5 6

5 7

5 8

5 9

6 0

4.n , I I dich 2 n d ncn 3 r d th 41h

rn I l l l l l l l l l l l l l l l l 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B C ~ i . 1 ch 2nd ~ ç n 3 r d B L ~ 411

rn 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 l l l l l l l l l l l l l l l l l 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I I I I I I l l 1 1 1 1 1 1 1 1 1 ( 4 . 2 3 3 6

1 MHZ)

7 I L ( 4 4 . 1 kHz)

1 1 1 J ~ ( 8 8 . 2 k H z )

A I I 1 r 1 1 1 1 1 1 L r L( I76.4kHz)

I 1 1 I I r L

- PlSL = H

Pin Name

(NC)

(NC)

(NC)

(NC)

(NC)

(NC)

(NC)

(NC)

(NCI

(NC)

- LSBl

- PlSL = L

Pin Name

X I 6

X I 5

X I 4

X I 3

X I 2

X I 1

X 1 O

X9

X 8

X 7

X 6

Il0

i P

iP

i P

i P

i P

i P

i P

ip

i~

i P

1 P

110

ip

ip

ip

ip

ip

ip

ip

ip

ip

ip

ip

CIRCUIT DESCRIPTION

DIA distortion correct TC1 7G005AF-0048 (X25-3050-00: ICI 5) Explanation of terrninals

Crystal oscillator input terminal


Hexa D Flip-flop TC74HC174F (X25-3040-00: IC2) Block diagram

Vcc 6Q 6D 5D 5Q 4D 4 0 CLOCK

CLEAR 1 0 I D 2D 2 0 3D 3 0 GND

Truth table

l nputs Outpub

H

CIRCUIT DESCRIPTION

Transistor array (X25-3040-00: IC3) TD62003AP DARLINGTON DRIVER Pin configuration

0 1 0 2 0 3 0 4 0 5 0 6 0 7 COMMON

COMMON INPUT OUTPUT

I I L - - - - - - - GND

Il 12 13 14 15 16 17 GND

pPD4053BC 2-channel analog switch IC Truth table (X32-1170-00: IC2) The pPD4053BC is a multiplexer cornposed of a level converter and analog SWs. The switches corresponding to the required channels are turned on according to the digital signal input to the control terminals.

Block diagram

H: "H" level..L: "L" level, X: H or L

ADJUSTMENT - No. -

1

-

2

-

3

-

4

-

5

-

6

-

7

-

8

-

9

-

1 O

-

11

- loti

1 NPUT SETTl NC SETTI NC SETTl NC

ALICNYENT POINT 1 TEM ALICN FOR

ien the porer is fra Short-circuit

pins TEST and turn APPIY the sensor power on to enter

section of the optical the Test mode. power meter on the Press the REPEAT

pickup lens. key. the tray opens and

0.15 to 0.4mV. RF evel is 1.OVp-p or iore, TE (servo open s 2.OVp-P or more ind the diffraction grating is aligned ,orrect lu. the picku

is acceptable.

LASER WVER

the LO emits light Short-circuit pins

Connect a DC ammeter TEST and turn pore across CN2 on to enter the pin 6 and Test mode. Press the pattern. the REPEAT key. (X32-1110) the tray opens and

the LD emits light

LASER PICKUP lPERATl NC CURRENT (Only when the pickup seems defective.)

-5.5mA current valus abeld on the laser pickup. If current 6 40mA or more ove1 .he above value. it'

defect ive.

Connect a frequency counter to CNll(P1CK)

(X32-1110)

Turn Power OFF, then ON again. VCO

Stop mode Enter the test mod by turning Power ON while shorting

the Test Pin. Press the CHECK ke and confirm that th display is ' 0300' Enter the test mod

- -

Test disk Type 4

Check that the diffraction

grating is aligned correctly.

:The grat ing cannot be adjusted.)

Connect an osci 1 loscopi as follows. CHI: RF (X29-1810 Test pin) CH2: TE (X32-1170 pin 1)

DIFFRACTION GRATlNC

Connect an ose i 1 loscop by turning Power ON while shorting

the Test Pin. Press the CHECK ke and confirm that th display is ' 0300'

as follows. CHI: RF (X29-1810 Test pin) CH2: TE

TE. BALANCE VR3

(X29-1870)

Symmetry between upper and lower

pat terns. or DC=OIO. O5V

TRACK l NC ERROR BALANCE

Test disk Type 4

(X32-1110 pin 1) Connect an oscilloscop as follows. CHI: RF (X29-1810 Test pin) CH2: TE (X32-1110 pin 1) Use a servo jig. or connect a 4TkR. 410pF LPF to pin 1 of CN3.

(X32-1110) Use a servo jig. or connect a 4lkR. 470pF LPF to pin 5 of CN3.

(X32-1110)

Press the PLAY key. and conf irm that the display

is' 0500'.

FE BALANCE VR4

tx29-18io)

FOCUS ERROR BALANCE

Test disk Type 4 lptimum eye pattern

Test disc Type 4 iply 900Hz. 4OmVrm gnal to CN3 pin 2 ' PC board X32-111 Test disc Type 4 1p1y 900Hz. 4OmVrm gnal to CN3 pin 4 ' PC board X32-117

Turn Power OFF then ON again. and press

the PLAY key.

FOCUS CAlN VRl

(X29-1810) FOCUS CAlN

- -

4OmVrms

1.9-2.OVrms

Minimum distortion

TRACK l NC CA 1 N VR2

(X29-1810) PLAY TRACK INC GAIN

Test disk Type 4 to the output OdB signal DAC OUTPUT

Test disk Type 4 to the output -20dB signal DAC DISTORTION

Test disk Type 4 to the output OdB signal

!quivalent.

DAC DISTORTION Minimun distortion

Type 4 disk: SONY )S-18 Test Oisk or

REGLAGE

RECLACE 1 RECLACE 1 RECLACE DE LA 1 POINT 1 D' ENTREE

-

DE SORTIE LECTURE ( D' ALIGNEMENT Court-circuiter les]

ALIGNEMENT POUR Quand 1' alimentation

FIG -

(a)

-

(b)

broches TEST et mettre sous tensio pour passer dans le mode d' essai. Appuyer sur

la touche REPEAT. le plateau s'ouvre et le LD emet de

est de 0.15 à 0.4iX. le niveau RF de 1.OVc-c ou plus.

TE (asservissement ouvert) de 2.OYc-c 01

Appliquer la section dëtecteur du compteu de puissance optique

sur la lentille du capteur.

plus et le reseau de diffraction aligne correctement. le cap teur est acceptable.

1

la lumiëre.

broches TEST et mettre sous tensio pour passer dans le mode d' essai. Appuyer sur

la touche REPEAT,

PUISSANCE LASER

+5.5mA de valeur de courant indiquee sur

le capteur laser. Si le courant est de

40mA ou bien

courant de fonctionnement du

Raccorder un ampëremetre CC en travers de la broche 6 de

CN2 et la forme. (X32-1110)

supérieur à la valeur ci-dessus. i l est défectif.

2

le plateau s' ouvre et le LD émet de

la lumiére.

1' alimentation.

capteur laser (Uniquement quand le capteur semble

dëfect if.)

Raccorder un compteur de frëquence

à CNI1 (PLCK). 1 1 VCO (X32-1110) 1 Mode d'arrêt

1 1 Entrer en mode de

Raccorder un r cil loscope comme suit CHI: RF (X29-1810 broche test) CH2: TE (X32-1110 broche 1)

test en mettant 1' alimentation en circuit tout en court-circuitant la broche test.

Presser la touche CHECK et s' assurer que 1' aff ichage

Yerifier que le réseau de diffraction est

correctement aligné. (Le réseau ne'peut pas ëtre ajuste.)

4 Disque test

Type 4 RESEAU DE DIFFRACTION

Entrer en mode de test en mettant 1' alimentation en circuit tout en court-circuitant la broche test.

Presser la touche CHECK et s'assurer que l'affichage

1 Raccorder un Symétrie entre les formes supërieure et

inférieure ou DC=Ot0,05V

>scilloscope comme suit CHI: RF (X29-1810 broche test) CH2: TE (X32-1110 broche 1)

BALANCE D' ERREUR 5 D' ALIGNEMENT

TE BALANCE VR3

(X29-1870)

Disque test

Type 4

1 est "0300'. Raccorder un

)scilloscope comme suit. CHI: RF (X29-1810 broche test) CH2: TE

FE BALANCE VR4

(X29-1810)

Presser la touche PLAY et s'assurer que l'affichage

est ' 0500 ' 6

Disque test Type 4

BALANCE D' ERREUR DEMISEAUPOINT Forme optimum

CAlN DE MlSE AU POINT

VRI (X29-1810)

Disque test Type 4 Appliguer un signal

900Hz. 40mYrms â la troche 2 de

CN3 sur la plaquette X32-1110.

Disque test Type 4 Apyliauer un signal

9OOHz. 40mVrms â la troche 4 de

CN3 sur la plaquette

Couper 1' alimentation et la redonner puis presser la touch PLAY.

(X32-1110 broche 1)

Utiliser un gabarit d' asservissement

ou raccorder un FPH de 4'7kIi. 410pF

la troche 1 de CN3.

Utiliser un gabarit d' asservissement

ou raccorder un FPH de 41kQ. 410pF

CAlN D' ALIGNEMENT VR2

(X29-1870)

7

8 1 CAlN D'ALICNEMEN.

GAIN DE MlSE AU POINT

PLAY

132-1110. 1 latroche5deCN3. 1 ( Raccorder un voltmètre 1 Lire le signal 1 YRl: C

9 1 SORTIE DAC Disque test 1 CA sur la borne de 1 IkHz. 0dB dans 1 VR2: D 1 1.9-2.OYrms 1 (h) 1 DISTORSrOti DAC

DISTORTION DAC

:Remarque)Disque de type

Type 4

Disque test

Type 4 1 sortie (FIXED). 1 la piste n. 4. 1 (X25-3050) 1 :Disque test SONY YEDS-18 ou ëquivalent.

sortie (FIXED). Raccorder un voltmétre

CA sur la borne de

Type 4

Disque tes1

la piste n' 2. Lire le signal IkHz. -20dB dans

sortie (FIXED). Raccorder un voltmëtre

CA sur la borne de

(X25-3050) YR3: C VR4: D

la piste n' 15. Lire le signal 100Hz. OdB dans

Distortion minimum (125-3050) YR5: C YR6: D

(h)

Distortion minimum (hl

NU. GEGENSTAND

1 LASERLEISTUNG

2

BETR 1 EBSSTROM DES LASERTONABNEHYERS (Nur wenn der Tonabnehmer defekt zu sein scheint)

5

7 ( FOKUSVERSTARKUNC

SPURHALTEFEHLER- AUSCLEI CH

6

SPURHALTE- VERSTARKUNC

FOKUS- FEHLERAUSCLEICH

9 1 DAC-AUSCANC

DAC-VERZERRUNC 4- II 1 DAC-VERZERRUNC

El NCANGS- El NSTELLUN

Testdisc TYP 4

Testdisc TYP 4

Testdisc TYP 4

Testdisc Type 4 Ein 900Hz. 40mVrns Signal an Stift 2 von CN3 an platine 132-1110 anlegen. Testdisc Type 4 Ein 900Hz. 40mVrms Signal an Stift 4 von CN3 an platine X32-1170 anlegen.

Testdisc. TYP 4

Testdisc TYP 4

Testdisc

Type 4

AUSGANCS- 1 SPIELER- 1 ABCLEICH- 1 1

Das Sensortei l des optiscben

Leistungmeters auf die Aufnehnerlinse

ansetzen.

El NSTELLUNGE

kurzschlieBen und die Spannungsver- sorguns einschal ten. um den Test-Modus zu aktivieren. Die Taste REPEAT drücken dann offnet sich der Trager. und die

Spannung von 0.15 bis 0.4 n Y der RF-Pegel 1.OVs-s oder mehr. TE (Servo-Of f en)

2,OVs-s betragt und das Beugungsgitter richtig ausgerichtet ist. ist der Abtaster

1 DieStifteTEST 1 1 lenn bei einer 1.. El NSTELLUNG PUNKT

1 LD gibt Licht aus. 1

Stromwert + 5.5mA auf den Lasertonab- nehmer markiert.

Venn der Strom 40mA

ABGLEICHUNG 1 ABB

in Ordnung. 1

Ein-Cleichstrom- Amperemeter zwischen CN2 Stift 6 und

iem Muster anschlieBen. (X32-1170)

Einen Frequenzzahler an CNll(PLCK) anschlieBen. (X32-1170)

Ein Oszilloskop rie folgt anschlieBen: Kanal 1: RF (X29-1870 Teststift) Kanal 2: TE (X32-1170 Stift 1)

oder mehr über den obigen lert liegt.

ist er defekt.

1 Die Stifte TEST (

Priifen. ob das Beugungsgitte richtig ausgerichtet

ist.(Das Citter kann nicht

eingestellt werden.)

kurzschl ieBen und die Spannungsver- sorguns einschalten. um den Test-Modus zu aktivieren. Die Taste REPEAT drucken. dann offnet sich der Trager. und die LD gibt Licht aus. Die Spannungsversor- gung aus-und dann wieder einschalten. Stop-Betriebsart

Den Testst ift kurz- schlieBen und dabei die Spannungsversor- gung einschalten. un den Testmodus zu aktivieren. Die CHECK- Taste driicken und prufen. da0 ' 0300 " auf dem Display

1 angezeigt wird. 1 Den Testst ift kurz- 1

-

L9 (X32-1170)

-

Symmetrie zwischen Ein Oszilloskop

wie folgt anschlieBen: Kanal 1: RF (X29-1870 Teststift) Kanal 2: TE (X32-1170 Stift 1)

Ein Oazilloskop rie folgt anschlie0en: Kanal 1: RF (X29-1810 Teststift) Kanal 2: TE

Optimales Ausenmuste Cf) 1

schl ieBen und dabei die Spannungsversor- gung einschalten. un den Testnodus zu aktivieren. Die CHECK- Taste driicken und prufen. da0 ' 0300 ' auf den Display angezeigt wird.

Die PLAY-Taste driicken und prüfen. da0 ' 0500 ' auf dem Display

oberen und umteren Mustern oder Cleichstrom DC=OfO.O5V

TE BALANCE VR3

(X29-1810)

FOKUS- FEHLERAUSCLEICH

VR4 (X29-1870)

(e)

(X32-1110 Stift 1) Eine Servo-Lehre v e r wenden oder ein 47kQ. 410pF TiefpaDfilter an Stift 1 von CN3

anschl ieBen. Eine Servo-Lehre ver- wenden oder ein 47kP. 470pF TiefpaBf ilter an Stift 5 von CN3

angezeigt wird. Die Spannungsversor- gung aus-und dann wieder einschalten. dann die PLAY-Taste

anschlieBen. Ein lechselstroai-

Voltmeter an die Aus- gangsklemme(F1XED)

1 anschliesen. 1 wiedergeben. 1 (X29-1870) 1 1 (Hinveis) TYP 4 Disc: SQNY YEDS-18 Testdisc oder Aquivalent.

drueken.

PLAY

- -

anschl ie0en. Ein Yechselstrom-


anschlieBen. Ein lechselstrom-


FOKUSVERSTARKUNC VR1

(X29-1810)

Das IkHz. OdB Signal in Titel Nr. 2

SPUHALTE- VERSTARKUNG

VR2 (X29-1810)

VR1: L VR2: R

wiedergeben.

Das 1kHz. -20dB Signal in Tite1 Nr. 15 wiedergeben.

Das 100Hz. OdB Signal in Titel Nr. 4

40mVrms (9)

4OmVrms

(X29-1870)

VR3: L VR4: R (X29-1810)

VR5: L VR6: R

(B)

Minimale Verzerrung

Minimale Verzerrung

(b)

Ch)

4. Description of Signal Waveforms, Connection of Measuring Instruments/Description des formes d'onde des signaux, connexion des instruments de mesure/Beschreibung der Signal-Wellenformen, Anschlui3 der Mefiinstrumente

RF signal and T.Error signal after diffraction grating CH1 RF adjustment.

Signal RF et signal T.Error après ajustement de réseau de diffraction. RF-Signal und T.Error-Signal nach Diffraktions-gitter- Einstel lung.

CH2 T.Error 2.0VIdiv

(Photo. 1) RF signal and T.Error signal when there is small diffrac- (20msecldiv) (Photo. 1) tion grating position error.

(Foto. 1) The T.Error signal level is small, and the envelope is as shown in the diagram below.

RF Signal RF et signal T.Error quand il y a une petite 1 .OVldiv erreur de position du réseau de diffraction.

Le niveau de signal T.Error est petit et I'envelope est telle qu'indiquée dans le diagramme ci-dessous. RF-Signal und T.Error-Signal bei kleinem' Diffraktions- gitter-~ositionierungsfehler. Der T.Error-Signalpegel ist klein, und die HüII-kurve ist

CH2 T.Error 2.0Vldiv

+O(V)

RF signal and T.Error signai in test mode (with focus- (Photo. 2) ing ON).

Trigger point (20msecldiv) point de déclenchement (Photo. 2, When the sub-beam traces the same bit series as the main Triggerpunkt (Foto. 2) beam during diffraction grating adjustment, bringing the

RF trigger point to the position shown in the Photo

CHI RF causes a "projection" to be observies in the T.Error

1 .OVldiv waveform, Le signal RF et le signal T.Error en mode de test (avec la mise au point sur ON).

+-O(V) Quand un faisceau auxiliaire tracela même serie de bits que le faisceau principal pendant l'ajustement de r6seau de diffraction, l'apport du point de déclenchement RF à la position indiqube dans la photo provoque une

CH2 T.Error "projection" qui s'observe dans la forme d'onde d' 2.OVldiv T.Error.

-O('' RF-Signal und T.Error-Signal irn Testmodus (bei ein- geschalteter Fokussierung). Wenn der Nebenstrahl die gleiche Bitreihe wie der Hauptstrahl wahrend der Diffraktionsgitter-Einstellung - Projection (Photo. 3) verfolgt und den RF-Triggerpunkt auf die im Foto

(2wecldiv) Projection (photo. 3) gezeigte Position bringt, wird eine "Hervorstehung" Hervorstehung

(Foto. 3) verursacht, die in der T.Error-Wellenform beobachtet werden kann. 63

ADJUSTMENTIREGLAGEIABGLEICH

RF signal and E.Spot signal in test mode (PLAY). I f the diffraction grating has been adjusted properly, the influence of triggering is observed on the E.Spot waveform of approx. 1% after RF signal, in the form of a projection. Signal RF et signal E.Spot en mode de test (PLAY).

CH1 RF 1 .OV/div Si le réseau de diffraction a été ajusté correctement,

l'influence du déclenchement s'observe sur la forme d'onde E.Spot d'environ 1 2 p après le signal RF, sous la forme d'une projection. RF-Signal und E.Spot-Signal im Testmodus (PLAY). Wenn das Diffraktionsgitter richtig eingestellt wurde,

CH2 E.Spot wird der EinfluB des Triggers in der E.Spot-Wellenforrn

0.1 Vldiv etwa 1 2 p nach dem RF-Signal in der Form einer AC coupling for Hervorstehung beobachtet. CH2 only Couplage CA pour canal 2 seulement AC-Ko~oluno nur für Kanal2 . . -

(2pecldiv) L pro~ect lori Projection

(Photo. 4)

Hervorstehung 4,

(Photo. 6) (Photo. 6) (Foto. 6)

RF signal and T.Error signal: in test mode (Focusing ON) (Disc type 4) Adjust T.Error so that the waveform is syrnrnetrical above and below OV. (VR3 of X29-1780-00) Signal RF et signal T.Error; en mode test (mise au point ON). (Disque de type 4) Ajuster T.Error pour que la forme d'onde soit symé- trique en-dessus et au-dessous de OV. (VR3 de X29-1780-00) RF-Signal und T.Error-Signal; im Testmodus (Fokussie- rung eingeschaltet). (Disc-Typ 4) T.Error so einstellen, daB die Wellenform über und unter OV syrnmetrisch ist. (VR3 von X29-1780-00)

RF signal in test mode (PLAY). Perform the tangential and focusing offset adjustments so that each of the center cross points are focused into one point on the display. The crossing points above and below the center shall also be displayed clearly. Signal RF en mode de test (PLAY). Effectuer les ajustements d'offset tangentiel et de mise au point pour que chacun des points de croisement central soit mis au point sur un point de l'affichage. Les points de croisement au-dessus et en-dessous du centre doivent aussi être affichés clairement. R F-Signal im Testmodus (PLAY). Die Tangential- und Fokusversatz-Einstellungen so durchführen, da8 jeder der mittleren Kreuzungs- punkte in einem Punkt auf dem Display fokussiert wird. Auch die Kreuzungspunkte über und unter der Mitte müssen klar angezeigt werden.

Eye pattern center Centre de la forme oculaire

- Augenmuster-Mitte

RF signal and PLCK signal in test mode (PLAY). When the synch system is normal, the cross points at the center of the eye pattern shall coincide with the PLCK fall points. Le signal RF et le signal PLCK en mode de test (PLAY). Quand le système sync est normal, les points de croisement au centre de la forme oculaire doivent coïncider avec les points de chute PLCK.

2.0VIdiv RF-Signal und PLCK-Signal im Testmodus (PLAY). Wenn das Sync-Sys'tem normal ist, müssen die Kreu- zungspunkte in der Mitte des Augenmusters mit den PLCK-Fallpunkten zusammenfallen.

Pickup u Capteur Optical power meter Abnehmer Compteur de puissance optique

Optikleistungsmesser

(Foto. 7)

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Descript ion

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FLAT WASHER l'LAT WASt-IER (02. 1 1 FLAT WAÇt1ER (YBKEj f:LAT WACjtiF'l? ( 1I:HASSI S 1 RETAINIING RINCj ( 0 2 . 5 1

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[Format] [General]

Power consumption: .............. 23W Type: ............................................ Compact disc player ............................... Read system: ............................ Non-contact optical Dimensions: W: 440mm (1 7-5/1 6")

pickup Laser: GaAIAs. wave- H: 1 24mm (4-7/8") ...........................................

length=780nm, 3-beam tracking

Rotational speed: .................... About 500 to 200 rpm ....................................... Error correction: ....................... Cross lnterleave Read-Sol- Wei9ht: 1 1 .8kg (26 Ib)

omon code Audio channels: ....................... 2

[Audio]

.............. Frequency response: Signal-to-noise ratio: .............. Total harmonic distortion: ... Channel separation: ............... Wow f lutter: ............................. Output voltage

Analog outputs LlNE OUT (FIXED): ............. LlNE OUT (VARIABLE): ....

Digital output Coax cable terminal: .........

Optical output: ..................... Headphone jack: ..................

4Hz - 20kHz more than 108dB 0.001 % at 1 kHz more than 106dB at 1 kHz Below measurable limit

0.5V p-p. 75 ohms - 15dBm - - 25dBm 60mW (8 ohms)

[Wireless remote control unit]

Model: ......................................... RC-Pl 1 00SG ............................................ Type: lnfrared pulse

Power supply: ........................... DC 3V (two AA size batteries)

Weight: ....................................... 1 15g (with batteries)

[Supplied accessories]

..................... Connection cord: 1 stereo cord Wireless remote control

......................... (RC-Pl 1 00SG): 1 .......................... Batteries (AA): 2

Note: We follow a policy of continuous development. For this reason specifications may be changed without notice.

Note:

Component and circuitry are subject to modification to insure best operation under differing local conditions. This manual is based on the Europe (E) standard, and provides information on regional cirucuit modification through use of alternate schematic diagrams, and information on regional component variations through use of parts list.

KENWOOD CORPORATION Shionogi Shibuya Building, 17-5. 2-chome Shibuya. Shibuya-ku, Tokyo 150. Japan

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