keynote qualification of power electronics modules – from ... · characterization tests (qc)...

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Andreas Aal

Qualification of Power Electronics Modules – from an industry gap analysis to international standardization

Semiconductor Strategy / ReliabilityVolkswagen AG

Andreas Aal Semiconductor Strategy / Reliability (EEH/1)Volkswagen AG, Berliner-Ring 2, 38436 Wolfsburg, Germany Phone: +49-(0)5361-9-38277; Fax: +49-(0)5361-9-57-38277 e-mail: [email protected]

Keynote

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OEM Standard LV324 / Power Electronics Industry Guideline AQG324 / future IEC standard = a success story of trough the

supply chain alignment-

a blueprint for further approaches within the automotive transformation

ECPE Guideline AQG 324 Qualification of Power Modules for Use in Power Electronics Converter Units (PCUs) in Motor Vehicles

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ContentBackground – Power module qualification standard 1

Motivation, scope, challenges 2

Underlying product design flow principle3

Module (QM) and characterization tests (QC) 4

Environmental tests (QE)5

Life tests (QL)6

Further features & outlook to an Automotive Platform environment 7

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Background – Power module qualification standardOrigin of a successful industry initiative

Status 2011/2012 – Increased functional demand to use PM in vehicle applications

Observation Endurance tests for power electronics inside HV components cannot be and do not

relate(d) in the same manner to the stress metric - temperature – compared to typicalLV components validation methods need to be extended to cover relevant missionprofiles / automotive load conditions

Qualification of automotive power modules not addressed by any standard. Eachmanufacturer has its own way to qualify power modules

New challenges – eMobility supply chain status

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Background – Power module qualification standard …Origin of a successful industry initiative

Resulting field of action

Generate a standard for qualification of automotive power modules that includesstandardized endurance testing

Standard to be based on state-of-the art industry standards + changes orenhancements w.r.t. automotive needs

Established an open expert group along the supply chain of engineers from OEMs,Tier1 and module vendors

Action & Collaboration

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Motivation, scope, challenges Automotive industry needs

Standardization along the automotive industry is a key factor to enhance quality and toreduce costs

Standardization leads to a better comparability of different design approaches

Standardized qualification as a unique basis for capability proof of power modules inautomotive applications

A win-win in industry

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Motivation, scope, challenges Automotive industry needsDefinition of minimum requirements towards

test conditions / tests for validating properties service life & fail criteria. Targeted are automotive power electronics modules & corresponding functional similar (discrete) assembly groups (special designs)

based on power semiconductors using silicon technology – are considered amodule.

Qualification of semiconductor chips or production processes are not targeted (butrequired), only the module level.

Extended requirements adapted for technologically innovative designs, newinterconnect or assembly technologies or GaN / SiC

Build a foundation

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Motivation, scope, challenges Automotive industry needs The thermal interface between the PM and cooling system at component level is not

covered if it is not part of the module structure (changed – now it is).

Example: Validation of the thermal interface of power electronics modules applied via a TIM

material on a heat sink shall not be analyzed in this document (in such a casecorresponding tests need to performed based on a reference test setup recommendedby the module manufacturer).

Validation of the thermal interface of power electronics modules with a PinFIN like baseplate located directly in the cooling medium shall be analyzed

Understand responsibilities along the supply chain

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Underlying product design flow principleDesign process

Design optimization potential along the supply chain

(Power semiconductor design)

PM design

Component / ECU design

OEM system design / operation strategy

VW 82324 / AGG324

Limited availability for new system designs

Prerequisite: module lifetime model available to OEMs

Product design flow

https://www.ecpe.org/research/working-groups/automotive-aqg-324/

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Module tests (QM)Ensuring fault free DUTs, met requirements & functional accuracy

Standard end-of-line tests

Interconnection layer tests (e.g. SAM analysis)

Nominal collector current ICN (IGBT modules)a) Nominal collector current = permanent direct current at a given Rth,j-c with Tvj < Tvj,max

b) Nominal collector current = collector current at typ. UCE,sat with maximum Rth,j-c

Note: The implemented rated chip current (e.g. 800 A) is usually specified in data sheets; this does not usuallycorrespond to the rated module current depending on the thermal impedance and cooling connection (e.g. 550 A).

Gate-emitter (IGBT) / Gate-source (MOSFET) threshold voltage / leakage current Determined for TRT and Tmax

Assurance of basic functional requirements

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Module tests (QM)Ensuring fault free DUTs, met requirements & functional accuracy

Collector-emitter (IGBT) / Drain-source (MOSFET) reverse leakage current Determined for TRT and Tmax

Forward voltage UCE,sat (IGBT), UDS (MOSFET), UF (Diodes) Determined for TRT and Tmax

IPI VI / OMA OMA (Optical Microscope Assessment),

IPI/VI (Initial Physical Inspection, Visual Inspection)

Assurance of basic functional requirements

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Characterization tests (QC)Precursor to environmental and life testing

QC – 01 Determination of parasitic stray inductance (Lp)IEC60747-15:2012 Chapter 5.3.2 - double pulse test QC – 02 Determination of thermal resistance(Rth value) - DIN EN 60747-15:2012 Chapter 5.3.6

Setting reference points

CuCeramic insolator: DCB

Cu

Si

Baseplate(Al, Cu, …)

Solder

Solder

CuCeramic insolator: DCB

Cu

SiSolder

Tvj

Heat Sink Temperature

Ts

TIM

2.5mm

2±1mm

Baseplate (Al, Cu) in cooling fluid

CuSolder

Ceramic insolator: DCB, AMBCu

SolderSi

Tvj

Tcool,in Tcool,out

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QC – 03 Determination of short circuit withstand capability

Aligning measurement setups

HC

HE

G

E

C

12V

Ron

Roff

Gat

eD

river

DUT

HC

HE

G

E

C

CurrentSense

ISC

IC

Osciloscope

Type 1 short-circuit (HSF: Hard-Switch-Fault):Inductances in the measurement setupshall be dimensioned so low that the DUTdoes not reach the saturation range atany point in time.

Type 2 short-circuit (FUL: Fault-Under-Load):Inductances in the measurement setupshall be dimensioned such that the DUT'sdesaturation phase is reached earliestafter 5 µs.

Pulse duration tp and junction temperature Tvj:tp: 10 % rising edge ISC1 – 10 % falling edge ISC1Tvj: Tvj at the time of 10 % rising edge ISC1

Pulse duration tp and junction temperature Tvj:tp: 20 % rising edge Vzk –10 % falling edge ISC2Tvj: Tvj at the time of 20 % rising edge Vzk

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QC – 04 Determination of isolation behavior

Blocking capability test, insulation resistance test

QC – 05 Determination of mechanical data

Determination of settling properties, heat conducting pastes

Fixed test conditions, data sheet confirmation check

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Environmental tests (QE)Contact / construction sustainability through storage, vibration & shock

QE – 01 Thermal shock (TST) QE – 02 Contactability (CO) QE – 03 Vibration (V) QE – 04 Mechanical shock (MS)

Resistance to mechanical stressesReliable contact & vibration / shock robust construction

Related standards:IEC 60749-25:2003

Test facility – air/air

Test sequence – mounting w.r.t. instructions

Test condition – Table 1

Fail criteria – module tests + Rth,j,c,s monitoring

Table 1: TST test parameters Minimum loading temperature value Tstg,min −40 °C−10

0 Maximum loading temperature value Tstg,max +125 °C0

+15 Transition time tchange < 30 𝑠𝑠 Minimum dwell time at maximum/minimum temperature tdwell > 15 𝑚𝑚𝑚𝑚𝑚𝑚 Minimum number of cycles without failure NC > 1 000

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QL – 01/02 Power cycling (PCsec / PCmin)

Related standards: IEC 60749-34:2011

Life Tests (QL)Test to fail – check deviation from lifetime curve

Near chip interconnect wear-out (PCsec)Chip remote interconnect wear-out (PCmin)

tcycle

ΔTvj

t

T

toffton

Tc/s,max

Tvj,max

ton

Tvj

Tc/s

I

tIL

Tc/s,min

Table 1: EOL criteria PCsec

Parameter Change in start

value

Forward voltage IGBT: UCE,sat MOSFET: UDS Diode: UF

+ 5 % a

Increase in virtual junction temperature swing ∆Tvj + 20%

a Note: also see notes on the settling process under test conditions

Table 1: Module-specific test parameters PCsec Parameter

Virtual junction temperature swing (starting value for test after settling process)

∆Tvj, start

Load current IL Load current on-time (heating duration) tON Load current off-time (cooling duration) tOFF Minimum virtual junction temperature Tvj,min Maximum virtual junction temperature at start of test Tvj,max Coolant temperature Tcool Gate-voltage UG

Table 1: Limit values for test parameters PCsec Parameter Value

Load current on-time tON < 5 s Load current level IL > 0.85∙ICN

a, b Gate-voltage UG Typically 15 V c a The load current level of > 0.85∙ICN shall only be selected for one sample point. b A value < 0.85∙ICN can be selected for the second and further sample points to enable a

suitable temperature increase difference to be set c The gate-voltage for the IGBT and MOSFET test can (e.g. if contact current densities become

too high) be less than 15 V if the desired temperature increase cannot be implemented with on-times of tON < 5 s due to the module's thermal properties. However, it shall always be guaranteed that the switch is permanently operated in the saturated range. In such cases, the gate-voltage which is used shall be accordingly adapted once at the start of the test and shall be documented in each case

tcycle

t

T

toff

Tc/s,max

Tvj,max

Tc/s

I

tIL

Tc/s,min

ΔTs/c

ton

Tvj

ΔTvj

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Life Tests (QL)Success run test – check according to industries best practice

Storage and transportation effects QL – 03 High temperature storage (HTS) QL – 04 Low temperature storage (LTS)

Chip passivation / edge seal stability to ionic contaminants QL – 05 High temperature reverse bias (HTRB)

Gate dielectric & interface integrity/quality check QL – 06 High temperature gate bias (HTGB)

Critical areas in the overall module structure QL – 07 High humidity, high temperature reverse bias (H3TRB)

Test link to specific module construction aspects

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Prerequisites to be taken into account (General Part)Requirements towards chips before use in modules & discrete assembly groups

Expectation: Chips qualified in accordance to the “Methodology” used in JP001A & AEC-Q101

Special additional process steps to enable the applicability in special configurations (i.e. chip-post-processing for double side contacts) require capability and robustness proof via DoE,TCAD-simulations & semiconductor vendor review comment.

Reduced test plan for discrete assembly groups

AEC-Q101/100 devices + QC-01 (stray inductance), QC-02 (thermal resistance) & QC-03(short circuit)

Definitions section, Test flows / sample size determination, Delta Qualification Matrix

Understand roles / responsibilities and interdependenciesalong the supply chain

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MN 5.7

Platform for AutomotiveSemiconductor Requirements

along the Supply Chain

Automotive Electronics CouncilComponent Technical Committee

GAAC – Global AutomotiveAdvisory Council

ITERC – TransportationElectronics Reliability Council

Initiation

Definition

Globalization

Standardization

Alignment

Intra-Organizational AlignmentInfrastructure Definition – Phase I

Alignment

Blueprint

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(x Chapter)

Platform for Automotive Semiconductor Requirements

along the Supply Chain

GAAC – Global AutomotiveAdvisory Council(x Chapter)

ITERC – TransportationElectronics Reliability Council(x Chapter)

Platform Host will be region specific

Alignment – Coordination

Intra-Organizational AlignmentInfrastructure Definition – Phase II (Region specific sub-structure)

x: US, EU, ASIA, …

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