khaled khalaf vojkan vidojkovic piet wambacq low-power … · 2019. 7. 17. · low-power millimeter...

Signals and Communication Technology

Khaled KhalafVojkan VidojkovicJohn R. LongPiet Wambacq

Low-Power Millimeter Wave Transmitters for High Data Rate Applications

Signals and Communication Technology

Series Editors

Emre Celebi, Department of Computer Science, University of Central Arkansas,Conway, AR, USAJingdong Chen, Northwestern Polytechnical University, Xi’an, ChinaE. S. Gopi, Department of Electronics and Communication Engineering, NationalInstitute of Technology, Tiruchirappalli, Tamil Nadu, IndiaAmy Neustein, Linguistic Technology Systems, Fort Lee, NJ, USAH. Vincent Poor, Department of Electrical Engineering, Princeton University,Princeton, NJ, USA

This series is devoted to fundamentals and applications of modern methods of signalprocessing and cutting-edge communication technologies. The main topics areinformation and signal theory, acoustical signal processing, image processing andmultimedia systems, mobile and wireless communications, and computer andcommunication networks. Volumes in the series address researchers in academia andindustrial R&D departments. The series is application-oriented. The level ofpresentation of each individual volume, however, depends on the subject and canrange from practical to scientific.

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More information about this series at http://www.springer.com/series/4748

http://www.springer.com/series/4748

Khaled Khalaf • Vojkan Vidojkovic •

John R. Long • Piet Wambacq

Low-Power Millimeter WaveTransmitters for High DataRate Applications

123

Khaled KhalafIMECLeuven, Belgium

Vojkan VidojkovicIntelDuisburg, Germany

John R. LongUniversity of WaterlooWaterloo, ON, Canada

Piet WambacqSSET DepartmentIMECLeuven, Belgium

ISSN 1860-4862 ISSN 1860-4870 (electronic)Signals and Communication TechnologyISBN 978-3-030-16652-6 ISBN 978-3-030-16653-3 (eBook)https://doi.org/10.1007/978-3-030-16653-3

Library of Congress Control Number: 2019936285

© Springer Nature Switzerland AG 2019This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or partof the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations,recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmissionor information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilarmethodology now known or hereafter developed.The use of general descriptive names, registered names, trademarks, service marks, etc. in thispublication does not imply, even in the absence of a specific statement, that such names are exempt fromthe relevant protective laws and regulations and therefore free for general use.The publisher, the authors and the editors are safe to assume that the advice and information in thisbook are believed to be true and accurate at the date of publication. Neither the publisher nor theauthors or the editors give a warranty, expressed or implied, with respect to the material containedherein or for any errors or omissions that may have been made. The publisher remains neutral with regardto jurisdictional claims in published maps and institutional affiliations.

This Springer imprint is published by the registered company Springer Nature Switzerland AGThe registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland

https://doi.org/10.1007/978-3-030-16653-3

Acknowledgements

We would like to thank all those who made this work possible, including butcertainly not limited to the support from IMEC technical and management teams.

v

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 60 GHz Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2 Phased Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 Link Budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.4 PA Power Back-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.5 Organization of the Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Design Considerations for High-Datarate Low-Power60 GHz TX Front-Ends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1 PA Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1.1 Width Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1.2 Power Combining and Stacking . . . . . . . . . . . . . . . . . . . . 122.1.3 Balanced Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.1.4 Cgd Neutralization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.1.5 Deep Class-AB Operation . . . . . . . . . . . . . . . . . . . . . . . . 17

2.2 Output Matching Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.2.1 Topology Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.2.2 Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222.2.3 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.2.4 Effect on PA Performance . . . . . . . . . . . . . . . . . . . . . . . . 26

2.3 Multi-stage PA Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282.4 Upconversion Mixer Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3 60 GHz TX Front-Ends in Advanced CMOS Technologieswith Improved Back-Off Efficiencies . . . . . . . . . . . . . . . . . . . . . . . . . 353.1 A TX Front-End in 40 nm-LP CMOS with Three-Stage

Class-AB PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353.1.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353.1.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.1.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

vii

3.2 A 4-Antenna Path TX Front-End with Two-Stage Class-A/ABPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403.2.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403.2.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423.2.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.3 A 28 nm-HPM TX Front-End with 11.5% PA Back-OffEfficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483.3.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503.3.2 Common-Mode Oscillations . . . . . . . . . . . . . . . . . . . . . . . 503.3.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523.3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4 Digitally-Modulated Polar Transmitters in 40 nm CMOS . . . . . . . . 554.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554.2 Architecture and System Trade-Offs . . . . . . . . . . . . . . . . . . . . . . . 57

4.2.1 60 GHz Polar TX Architecture . . . . . . . . . . . . . . . . . . . . . 584.2.2 Signal Behavior and System-Level Trade-Offs . . . . . . . . . . 59

4.3 A 5-bit 5 GS/s RF-DAC-Based Polar TX with –29.3 dBQPSK EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634.3.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634.3.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684.3.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.4 A 4-bit 10 GS/s RF-DAC-Based Polar TX with 15.3%Average PA Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794.4.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794.4.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844.4.3 Analysis and Discussion. . . . . . . . . . . . . . . . . . . . . . . . . . 914.4.4 Comparison with State-of-the-Art . . . . . . . . . . . . . . . . . . . 944.4.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

5 Summary and Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975.2 Possible Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Appendix: Loaded Transformer Input Impedance . . . . . . . . . . . . . . . . . 101

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

viii Contents

Abbreviations

AM Amplitude modulationBB BasebandBBBW Baseband bandwidthBW BandwidthDAC Digital-to-analog converterDCO Digitally controlled oscillatorDE Drain efficiencyENOB Effective number of bitsEVM Error vector magnitudeFR Full rateFSPL Free space path lossLNA Low-noise amplifierLO Local oscillatorLSB Least significant bitNF Noise figureOFDM Orthogonal frequency division

multiplexingOSF Oversampling factorP1dB Output-referred 1 dB compression pointPA Power amplifierPAE Power-added efficiencyPAPR Peak-to-average power ratioPD PredistortionPM Phase modulationRFBW Radio frequency bandwidthRX ReceiverSC Single carrierSNR Signal-to-noise ratioSNRq Signal-to-quantization-noise ratioSPI Serial peripheral interface

ix

TL Transmission lineTX TransmitterVCO Voltage-controlled oscillatorVGA Variable-gain amplifierZOH Zero-order hold

x Abbreviations

Nomenclature

h Angle‚ Wavelength/ Phaseu Phase… 3.14gd Drain efficiencyf Frequencyt Timed DistanceI In-phase signalQ Quality factor or quadrature signalk Coupling factor or Boltzmann constantT Temperature in kelvinB Bandwidth in hertzA AmplitudeN Number of bitsNA Number of bits in the amplitude pathNPh Number of bits in the phase pathgm TransconductanceAv Voltage gainGp Power gainGmax Maximum available gainGmsg Maximum stable gainCneut Neutralization capacitorKf Stability factorfT Transit frequencyPsat Saturation powerKvco Voltage-controlled oscillator gain

xi

List of Figures

Fig. 1.1 Wireless data trends: a total worldwide mobile data traffic[Cis11, Cis15, Eri12, Eri13, Eri14, Eri15], and b 802.11WLAN and 3GPP cellular network datarates [Wikb, Wika,Wikc] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Fig. 1.2 IEEE 802.11ad standard frequency band with 4 channelsof 2.16 GHz each and a sampling rate of 1.76 GHzin single-carrier communication mode . . . . . . . . . . . . . . . . . . . . 2

Fig. 1.3 60 GHz applications: Examples of high datarate connectivityamong devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Fig. 1.4 Directive beam controlled by phase-adjusted antennaarrays [Khalaf15b] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Fig. 1.5 Phase shift locations in phased-array direct-conversiontransmitter: a at RF, b at LO, c in the analog domainand d in the digital domain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Fig. 1.6 Link budget calculations assuming 5 dBm PA output power,8 dB RX NF and 15 dB output SNR: a FSPL at 60 GHz,and b possible communication distances versus the numberof antenna paths in both the TX and RX neglecting oxygenattenuation and assuming no rain conditions. . . . . . . . . . . . . . . . 7

Fig. 1.7 Illustration of the need for power back-off: a the input signalpeaks are lower than the compression point causingno distortion, and b the input signal peaks are largerthan the compression point causing signal clipping . . . . . . . . . . 7

Fig. 2.1 A simple PA with common-source transistor biasedin class-A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Fig. 2.2 A simple transistor small-signal model . . . . . . . . . . . . . . . . . . . . 11Fig. 2.3 Simulated performance of a single-transistor common-source

PA versus its width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Fig. 2.4 Increasing the output power using a series combiner

or b stacking configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Fig. 2.5 Balanced (push pull) configuration . . . . . . . . . . . . . . . . . . . . . . . 14

xiii

Fig. 2.6 Cgd neutralized push pull amplifier . . . . . . . . . . . . . . . . . . . . . . . 14Fig. 2.7 Testbench used to characterize a single-stage PA . . . . . . . . . . . . 14Fig. 2.8 Choosing the neutralizing capacitor value for a push-pull

PA stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Fig. 2.9 Stability of a push-pull PA Stage a without and b with

neutralization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Fig. 2.10 Load pull simulations on a push-pull PA stage at 0.5 V Vbias:

a without and b with neutralization . . . . . . . . . . . . . . . . . . . . . . 17Fig. 2.11 PA operation at different biasing conditions: a class-A

and b class-AB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Fig. 2.12 Load pull simulations on a push-pull PA stage at 0.3 V Vbias:

a without and b with neutralization . . . . . . . . . . . . . . . . . . . . . . 19Fig. 2.13 Effect of changing the bias (from 0.3 to 0.8 V) on the optimum

load for maximum Gp, P1 dB and DE for a push-pull PAstage: a without and b with neutralization. Values are shownfor bias voltages 0.3, 0.4 and 0.8 V in the following format:0.3, 0.4–0.8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Fig. 2.14 Simulated performance at 0.48\135 load with neutralization:a versus Vbias, and b versus output power at 0.5 V (solid)and 0.3 V (dotted) Vbias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Fig. 2.15 Current consumption at 0.48\135 load and different gatebias voltages with neutralization . . . . . . . . . . . . . . . . . . . . . . . . . 20

Fig. 2.16 Simulated AM-PM performance: a versus Pin at differentVbias values, and b at P1 dB referred to small-signaloutput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Fig. 2.17 PA output matching using a a pi network andb transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Fig. 2.18 a Testbench used for the design of the PA output balun,and b its variable transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Fig. 2.19 Sweeping L1, L2 and k: a without C1 and k is sweptfrom 0.2 to 1 in steps of 0.2 (k = 1 is in a dotted line),and b with C1 while k stops at 0.8. . . . . . . . . . . . . . . . . . . . . . . 24

Fig. 2.20 Sweeping L1, L2 and C1 for 0.48\135 input impedancewith minimum loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Fig. 2.21 1:1 transformer layout with M8 (left red) primary and M9(right blue) secondary, and M1–M7 (green) ground shield . . . . . 26

Fig. 2.22 Testbench for simulating the effect of the output transformeron the last PA stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Fig. 2.23 Performance of PA including matching network at 0.5 V Vbiasversus Pin: a Pout and Gp, and b Idc and drain efficiency . . . . . 27

Fig. 2.24 Performance of PA including matching network at 0.3 V Vbiasversus Pin: a Pout and Gp, and b Idc and drain efficiency . . . . . 27

Fig. 2.25 Cascade analysis using 0.5 V-based driver at different laststage gate bias voltages: a 0.5 V, and b 0.3 V . . . . . . . . . . . . . . 28

xiv List of Figures

Fig. 2.26 Gp of the 40 lm neutralized driver stage versus its gatebias voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Fig. 2.27 Determining the optimum load impedance for the driver(conjugate match) using Gp circles . . . . . . . . . . . . . . . . . . . . . . . 30

Fig. 2.28 Testbench used to find the optimal interstage transformerdesign parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Fig. 2.29 PA simulation with 0.5 V driver bias versus the input power:a at 0.5 V output stage bias, and b 0.3 V output stage bias . . . . 31

Fig. 2.30 Gilbert upconversion mixer schematic . . . . . . . . . . . . . . . . . . . . 31Fig. 2.31 S-parameter simulations of a 60 lm/60 nm transistor: a gm

and gm/go, and b Idc and gm/Id . . . . . . . . . . . . . . . . . . . . . . . . 32Fig. 2.32 Testbench for upconversion mixer characterization. . . . . . . . . . . 33Fig. 2.33 Simulated I-Q mixer performance at 0.7\25 load. . . . . . . . . . . . 33Fig. 2.34 Total TX front-end performance at different second PA

stage gate bias voltage: a 0.5 V, and b 0.3 V. . . . . . . . . . . . . . . 34Fig. 3.1 The benchmark chip in 40 nm-LP CMOS . . . . . . . . . . . . . . . . . 36Fig. 3.2 The three-stage class-AB TX front-end schematic . . . . . . . . . . . 36Fig. 3.3 The super source-follower upconversion mixer schematic . . . . . 37Fig. 3.4 Class-AB chip photo in 40 nm-LP: a full chip, and b TX

zoom-in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Fig. 3.5 Class-AB performance versus input power: a TX output

power and conversion gain, and b PA power consumptionand drain efficiency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Fig. 3.6 Class-AB TX performance: a versus PA bias settings,and b output PSD with 16-QAM input signal . . . . . . . . . . . . . . 39

Fig. 3.7 a Measurement setup, and b constellations . . . . . . . . . . . . . . . . . 39Fig. 3.8 The 4-antenna path 40 nm-LP chipset architecture [Brebels16]:

a TX, and b RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Fig. 3.9 The two-stage class-A/AB TX front-end schematic . . . . . . . . . . 41Fig. 3.10 Layout of the used transformers: a last-stage 1:1 transformer,

and b intermediate-stage 2:1 transformer . . . . . . . . . . . . . . . . . . 42Fig. 3.11 Simulated performance of the transformers: a 1:1 transformer,

and b 2:1 transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Fig. 3.12 TX chip photo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Fig. 3.13 Measurement setup for the probed TX chip . . . . . . . . . . . . . . . . 43Fig. 3.14 TX performance versus input power: a output power and

conversion gain, and b PA power consumption and PAE. . . . . . 44Fig. 3.15 TX performance versus PA bias settings when both stages

use the same values: a output power and conversion gain,and b maximum and 5 dB back-off PAE . . . . . . . . . . . . . . . . . . 44

Fig. 3.16 TX performance versus frequency: a compression and gainversus output frequency, and b gain versus baseband inputfrequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

List of Figures xv

Fig. 3.17 PCB module for wireless characterization: a flipped chipwith antenna feeds on the front side, and b back side with4 � 2 patch antenna array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Fig. 3.18 TX performance with integrated patch antennas and measuredwith a horn antenna: a output power versus the numberof activated TX antenna paths, and b 16-QAM PSD whenall 4 antenna paths are on and the PA operates in class-AB . . . . 46

Fig. 3.19 a Block diagram of the demonstration setup, and b outputconstellations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Fig. 3.20 Wireless link bit-error rate versus distance with a packet sizeof 32768 symbols: a using QPSK signal, and b using 16-QAMsignal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Fig. 3.21 Technology comparison for a minimal-length common-sourcetransistor with 30 lm width of: a fT versus current density,and b Gmsg and current density versus gate bias . . . . . . . . . . . . 48

Fig. 3.22 Technology comparison of Gmsg and Gmax for a minimallength 30 lm width neutralized amplifier . . . . . . . . . . . . . . . . . . 48

Fig. 3.23 Technology comparison for a minimal-length neutralizedamplifier with an optimum load and the same aspect ratio:a Psat and P1dB, and b Gp and DE . . . . . . . . . . . . . . . . . . . . . . 49

Fig. 3.24 The technology comparison of Fig. 3.23 with a Vbias relativeto the P1dB dip: a Psat and P1dB, and b Gp and DE . . . . . . . . 49

Fig. 3.25 Gilber upconversion mixer schematic with current-sourcebiasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Fig. 3.26 Testbench used to specify the minimum biasing resistorrequired to prevent common-mode oscillations . . . . . . . . . . . . . . 51

Fig. 3.27 Simulation of the Kf stability factor using the testbenchof Fig. 3.26 with different bias resistors: a Kf and b jDjparameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Fig. 3.28 Simulation of additional stability factors using the testbenchof Fig. 3.26 with different bias resistors: a l and b B1f . . . . . . . 51

Fig. 3.29 Testbench used to verify the effectiveness of biasing resistorin preventing common-mode oscillations with transientsimulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Fig. 3.30 Step response of the testbench of Fig. 3.29 at the single-endedPA input node with different biasing resistor values . . . . . . . . . . 52

Fig. 3.31 The 28 nm-HPM transceiver chip photo . . . . . . . . . . . . . . . . . . . 53Fig. 3.32 Performance of class-A and AB with Pin sweep at 62 GHz:

a output power and conversion gain, and b PA drainefficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Fig. 3.33 Measured fundamental response and third-orderintermodulation distortion for class-A and AB biasing . . . . . . . . 53

Fig. 4.1 a Conventional linear-PA-based I-Q TX, b digital cartesianand c digital polar TX architectures based on RF-DAC’s . . . . . . 56

xvi List of Figures

Fig. 4.2 Top-level digital polar transmitter block diagram . . . . . . . . . . . . 58Fig. 4.3 Simplified block diagram of the MatlabTM model used

for the transmitter side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Fig. 4.4 PSD of a input I-Q signal (before polar conversion)

and b amplitude signal after polar conversion with infiniteresolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Fig. 4.5 a PSD of phase path input signal sinðuÞþ jcosðuÞ,and b its upconverted representation in time domainwith infinite resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Fig. 4.6 16-QAM: a digital amplitude signal going to the chip,and b its histogram compared to QPSK . . . . . . . . . . . . . . . . . . . 61

Fig. 4.7 Simulated effect at 8 bits in the phase path (i.e., Nph)and different amplitude bits (i.e., NA) of: a phase path inputbandwidth and b amplitude-phase paths delay mismatchat 5 GHz phase-path bandwidth, together with the RF-DACresolution, on EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Fig. 4.8 Simulated alias attenuation at the TX output with 3 GHz phasepath bandwidth: a at 10 GS/s, and b versus the samplingrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Fig. 4.9 Simulated replicas with 3 GHz phase path bandwidth at 10GS/s: a in the amplitude path, and b in the phase path . . . . . . . 63

Fig. 4.10 Transformer-coupled two-stage PA with 5-bit RF-DAC . . . . . . . 64Fig. 4.11 The 5-bit RF-DAC top a layout and b cell distribution . . . . . . . 65Fig. 4.12 a Schematic and b layout of the gate-switched RF-DAC

unit cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Fig. 4.13 Simulated effect of Rb on the RF-DAC cell performance

at 60 GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Fig. 4.14 Voltage feedback upconversion mixer . . . . . . . . . . . . . . . . . . . . 67Fig. 4.15 Voltage feedback mixer input amplifier (AMP block

in Fig. 4.14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Fig. 4.16 Digital interface circuit for the 5-bit RF-DAC high-speed

inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Fig. 4.17 LO distribution chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Fig. 4.18 Chip micrograph of the 5-bit 5 GS/s testchip . . . . . . . . . . . . . . . 69Fig. 4.19 Chip micrograph of the 5-bit 5 GS/s testchip . . . . . . . . . . . . . . . 70Fig. 4.20 The 5-bit 5 GS/s PCB with its input-output connections . . . . . . 70Fig. 4.21 Simplified measurement setup of the 5-bit 5 GS/s testchip . . . . . 71Fig. 4.22 a Measured (meas), reproduced (sim1) and expected (sim2)

output powers and expected efficiency (eff) versus Pin.b Measured, reproduced and expected values of S22 . . . . . . . . . 72

Fig. 4.23 TX bandwidth behavior at a RF and b baseband . . . . . . . . . . . . 73Fig. 4.24 Static RF-DAC characterization versus switching code

using a single 200 MHz tone and b a QPSK signal . . . . . . . . . . 73

List of Figures xvii

Fig. 4.25 a Polar and linear mode EVM versus signal bandwidth,and b Re-measured QPSK EVM in polar mode with DC offsetcancellation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Fig. 4.26 Improvement of a linear-mode (i.e., at maximum RF-DACcode) and b polar-mode QPSK signals EVM versus Pin afterDC offset compensation at FR/8. Vin;TX;rm is the rms TX inputvoltage at the chip (i.e., mixer) input port . . . . . . . . . . . . . . . . . 75

Fig. 4.27 Polar and linear mode EVM versus Pin at FR/8 for a QPSKwith DC offset compensation and b 16-QAM without DCoffset compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Fig. 4.28 16-QAM signal EVM at FR and FR/8 rates without DC offsetcompensation due to: a delay mismatch between the amplitudeand phase paths, and b RF-DAC resolution. The EVM value atfully synchronized amplitude and phase signals and at 5-bitresolution corresponds to the best value in Fig. 4.27b . . . . . . . . 76

Fig. 4.29 Full-rate QPSK output PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Fig. 4.30 PSD of the linear and polar modes at a onset of saturation

and b higher power at FR/8 rate. . . . . . . . . . . . . . . . . . . . . . . . . 77Fig. 4.31 Full-rate (i.e., 1.67 Gsymbols/s) constellations in polar

mode of: a QPSK (with �19:2 dB EVM) and b 16-QAM(with �16:2 dB EVM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Fig. 4.32 FR/8 (i.e., 208.33 Msymbols/s) constellations in polarmode with DC offset compensation of: a QPSK (with �27:5dB EVM) and b 16-QAM (with �24:2 dB EVM) . . . . . . . . . . . 78

Fig. 4.33 FR/8 (i.e., 208.33 Msymbols/s) constellations in polar modewith DC offset compensation and amplitude predistortion of:a QPSK (with �29:3 dB EVM) and b 16-QAM (with �23 dBEVM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Fig. 4.34 Transformer-coupled two-stage PA with 4-bit RF-DAC . . . . . . . 80Fig. 4.35 Layout of the PA with 32 � 64 lm2 RF-DAC. . . . . . . . . . . . . . 80Fig. 4.36 The differential RF-DAC floorplan . . . . . . . . . . . . . . . . . . . . . . . 81Fig. 4.37 Source switched RF-DAC unit cell a schematic

and b layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82Fig. 4.38 Gilbert upconversion mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Fig. 4.39 Digital interface circuit for the 4-bit RF-DAC high-speed

inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Fig. 4.40 Full circuit diagram of the 4-bit 10 GS/s polar TX testchip . . . . 84Fig. 4.41 Chip micrograph of the 4-bit 10 GS/s testchip with 0.18 mm2

core and 2.38 mm2 total area . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Fig. 4.42 Simplified measurement setup of the 4-bit 10 GS/s testchip . . . . 85Fig. 4.43 TX performance versus Pin at maximum RF-DAC code:

a Pout and conversion gain, and b PA drain efficiency . . . . . . . . 86Fig. 4.44 TX performance versus a LO and b baseband input

frequencies at maximum RF-DAC code . . . . . . . . . . . . . . . . . . . 86

xviii List of Figures

Fig. 4.45 RF-DAC static behavior: a AM-AM and AM-PM, and b S22and PA drain efficiency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Fig. 4.46 Polar TX dynamic behavior: a amplitude-phasesynchronization, and b performance versus Pin . . . . . . . . . . . . . . 88

Fig. 4.47 RF-DAC a code shift behavior and b its performanceat the remaining number of quantization levels. . . . . . . . . . . . . . 89

Fig. 4.48 RF-DAC: a PD1 predistortion behavior and b QPSKpredistorted input codes with PD1 . . . . . . . . . . . . . . . . . . . . . . . 90

Fig. 4.49 Output PSD with and without PD1 predistortion . . . . . . . . . . . . 91Fig. 4.50 Measured QPSK and 16-QAM constellations . . . . . . . . . . . . . . . 92Fig. 4.51 a Simulated and measured EVM versus the number of used

top RF-DAC levels, and b simulated effect of signal leakageon EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Fig. 4.52 RF-DAC a PD2 behavior, and b its simulated performanceon top of measured and simulated data withoutpredistortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Fig. 4.53 a Applying a voltage step on the ideal line of PD2,and b its influence on EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Fig. 4.54 RF-DAC a PD3 behavior, and b its simulated performanceon top of measured and simulated data withoutpredistortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Fig. 5.1 Implemented TX architectures: a conventional analogCartesian and b digital polar with mixer upconversion . . . . . . . . 98

Fig. 5.2 Potential TX architectures: a digital Cartesian and b digitalpolar with VCO injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Fig. A.1 a Equivalent transformer model and b when loadedwith a complex impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

List of Figures xix

List of Tables

Table 2.1 Effect of neutralization on equivalent PA input and outputresistance and capacitance values . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 3.1 Comparison with state-of-the-art implementations . . . . . . . . . . . 40Table 3.2 Comparison with state-of-the-art implementations . . . . . . . . . . . 47Table 3.3 Comparison of TX front-end with previous

implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Table 4.1 Efficiency comparison of a linear PA and polar architectures,

all operating at 5 dB back-off from the P1dB (linear PA)or from saturation (polar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 4.2 TX performance summary at maximum RF-DAC code . . . . . . . 87Table 4.3 Modulated polar TX performance summary with and without

predistortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Table 4.4 Simulated EVM of PD2 and PD3 AM-AM predistortion

techniques assuming ideal AM-PM calibration and signalleakage compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 4.5 Comparison with state-of-the-art . . . . . . . . . . . . . . . . . . . . . . . . 95Table 5.1 Comparison between different TX architectures for minimum

TX power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

xxi

Chapter 1Introduction

The on-going increase in the amount of wireless data traffic [Cis15] preserves thedemand for higher wireless datarates. The growth in mobile data traffic has increasedby 22x between 2010 and 2015 (see Fig. 1.1a), and it is expected to increase by 10xbetween 2015 and 2021 [Eri15]. Datarates in wireless communications have alsoincreased exponentially, as shown Fig. 1.1b for cellular and wireless LAN standards.

Frequency bands with a width between between 3.5 and 9GHz are allocated indifferent regions for unlicensed usage at 60GHz [Agi13]. This allows multi-Gbit/swireless communication, enabling a lot of applications such as wireless streamingof high definition video and fast download of high definition content. For example,a typical HD movie is about 3–4.5GB [App]. It takes only 30s to download such amovie with 1Gbit/s datarate. Another example is wireless HD streaming, where anuncompressed 1080p video size is about 95–158MB/s [Wikd]. This corresponds todatarates from 0.76Gbit/s to 1.26Gbit/s, which is feasible at 60GHz.

A low-power integrated radio solution is a key enabler for 60GHz operation inmobile applications. The transmitter (TX) side usually consumes more than thereceiver (RX) in a conventional wireless communication link. The power amplifier(PA) is usually the most power hungry block in the TX, where it holds the largestsignal before the antenna and operates at the highest frequency in the transmissionchain. The main objective of this work is to explore low-power techniques for theimplementation of 60GHz transmitters. Digital CMOS technology is adopted in thiswork, targeting a low-cost single-chip CMOS transceiver solution with analog anddigital functionalities for consumer applications. This represents more challenge inthe circuit design as compared to other technologies due to the lower value of theavailable supply voltage and maximum frequency capabilities.

© Springer Nature Switzerland AG 2019K. Khalaf et al., Low-Power Millimeter Wave Transmitters for HighData Rate Applications, Signals and Communication Technology,https://doi.org/10.1007/978-3-030-16653-3_1

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https://doi.org/10.1007/978-3-030-16653-3_1

2 1 Introduction

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Fig. 1.1 Wireless data trends: a total worldwide mobile data traffic [Cis11, Cis15, Eri12, Eri13,Eri14, Eri15], and b 802.11 WLAN and 3GPP cellular network datarates [Wikb, Wika, Wikc]

1.1 60GHz Operation

Communication in the 60GHz band at multi-Gb/s wireless datarate is regulated bythe IEEE 802.11ad standard [IEE12]. As shown in Fig. 1.2, the standard defines 4channels of 2.16GHz each in the frequency band between 57 and 66GHz. It hasboth single-carrier (SC) and OFDM modes with a sample rate of 1.76GHz and2.64GHz, respectively. Coded datarates of up to 4.62 and 6.76Gb/s are defined forπ/2-16QAM SC and 64-QAM OFDM modulations, respectively. SC modulation ispreferred over OFDM for its power saving and low cost (due to the lower signalpeak-to-average power ratio) [Bourdoux08b]. At 1.76Gsymbols/s in SC modula-tion, raw datarates reach 3.52Gb/s and 7Gb/s in QPSK and 16-QAM modulations,respectively. Higher datarates can be achieved at higher constellations or with chan-nel bonding. IEEE802.11ad also supports fast session transfer to other IEEE802.11standards operating in the 2.4 and 5GHz bands for backward compatibility.

High datarate short-range communication is one of the main target applicationsfor the 60GHz band due to the large free-space path loss. Hence, users can reuse thesame channels even in the same room without throughput degradation. Figure 1.3shows an example of these applications, where the target is to provide multi Gbit/swireless connectivity among displays, PCs and handheld portable devices. 60GHzconnections also don’t penetrate walls. So, information security is physically guar-anteed for indoor appliances. Several applications are labeled with mass market and

Fig. 1.2 IEEE 802.11adstandard frequency bandwith 4 channels of 2.16GHzeach and a sampling rate of1.76GHz in single-carriercommunication mode

57GHz 66GHz2.1GHz

1.76GHz

1 2 3 4

1.1 60GHz Operation 3

Fig. 1.3 60GHz applications: Examples of high datarate connectivity among devices

large volume potential, such as kiosk allowing fast download of multi-Gbyte contentto smartphones and tablets, wireless docking stations, wireless USB and HDMI.

1.2 Phased Arrays

Multiple phase-adjusted antenna paths can be used to increase the transmitted powerand overcome signal losses at 60GHz (see Fig. 1.4). This is assisted by the smallerantenna footprint compared to the low-GHz range applications. The signal alsobecomesmore directive due to the use ofmultiple antennas, which requires electronicbeam steering for easier TX-RX synchronization. Controlling the phase differencebetween the different paths can be used to represent true time delay for controllingthe beam direction (i.e., scan angle).

As shown in Fig. 1.4, the beam direction can be controlled by the phase (or time)difference between the antenna elements, where:

d × sin(θ)

λ= �t

To= �t × fo (1.1)

4 1 Introduction

Fig. 1.4 Directive beam controlled by phase-adjusted antenna arrays [Khalaf15b]

In Eq. 1.1, To is the signal period and fo (1/To) is the signal frequency. Therefore,a relationship of antenna phase difference can be obtained:

2πd × sin(θ)

λ= �t × ωo = �φ (1.2)

Forλ/2 spaced antennas (for efficient transmissionwith less side lobes), the phaseshift difference between two adjacent antennas becomes:

�φ = �t × ωo = πsin(θ) (1.3)

For example, 127.3◦ of phase difference between two antenna paths placed at adistance of λ/2 is required to achieve a 45◦ beam angle. This is equivalent to a 5.9pstrue time delay between the two paths.

Figure 1.5 shows the possible locations of phase shifters in a transmitter. A directconversion TX architecture is used for its low power advantage and compactness.Phase shifting can be implemented in the RF signal path (e.g., before the PA), inthe local oscillator (LO) path, before the mixer in the analog domain or before thedigital-to-analog converter (DAC) in the digital domain. The closer phase shiftingis to the antenna, the less blocks are duplicated. This saves in power consumptionand silicon area. However, phase shifters in the RF are more bulky and lossy. Thisrequires extra RF amplification that consumes more power. It is also more difficultto control amplitude variations over different phase shift values. Therefore, choosingbetween analog and RF beamforming is not straightforward. Phase shifters in the LOpath are less attractive. Although it deals with a single tone rather than a broadbandsignal, it requires an implementation at RF together with multiplying the mixers andPA. Therefore, beside providing more area and power consumption, it adds to the

1.2 Phased Arrays 5

(a)

(b)

(c)

(d)

Fig. 1.5 Phase shift locations in phased-array direct-conversion transmitter: a at RF, b at LO, c inthe analog domain and d in the digital domain

complexity of LO distribution to multiple antenna paths and affects phase noise. Ahybrid solution that tries to combine benefits of different solutions is also possible[Raczkowski12].

6 1 Introduction

1.3 Link Budget

A basic link budget analysis can estimate the required transmit power for a certaincommunication distance. At the receiver, the input thermal noise power is kTB (i.e.,−174dBm + 10× log(B), where B is the signal bandwidth in hertz) assuming thelow-noise amplifier (LNA) input is conjugately matched to the antenna impedance.Therefore, the receiver sensitivity is:

PRX,min = −174 + 10 × log(B) + NF + SN Rout (1.4)

whereNF is the receiver noisefigure andSNRout is the target receiver output signal-to-noise ratio. In a phased array receiver with N antenna paths, the output signal poweris increased by either 10× log(N) or 20× log(N) compared to the input power ata single port depending on the architecture, while the noise is either increased by10× log(N) or averaged out, respectively. Therefore, the receiver sensitivity is in anycase improved by 10× log(N).

PRX,min = −174 + 10 × log(B) + NF + SN Rout − 10 × log(N ) (1.5)

For an RF bandwidth of 1.76GHz and assuming a noise figure of 8dB and an out-put SNR of 15dB, the receiver sensitivity becomes −58.5dBm for a single antenna-path system. The free space path loss (FSPL) at 60GHz is large due to the smallwavelength (5mm), and can be calculated as follows:

FSPL = 20 × log(λ

4π × d) (1.6)

Figure 1.6a shows that signal losses between 68 and 88dB are obtained at 60GHzfor communication distances between 1 and 10m. Additional signal losses due toatmospheric contributors such as oxygen attenuation and rain conditions are alsopresent [Yujiri03], which is more prominent in longer communication distances.Figure 1.6b shows the possible communication distances at an average transmittedsingle antenna-path power of 5dBmwith different number of antenna paths assuminga similar value (N) in both the transmitter and receiver.At the transmitter side, the totaltransmitted signal power from N antenna paths is 20× log(N), where 10× log(N)is due to the power recombination in air (after being split among the paths) and anadditional 10× log(N) is due to the air constructive interference when the signalsare in-phase. For short-range communication below 10m, 4 antenna paths can beused at both the TX and RX reaching 4.8m at 5dBm average PA output power, whiledistances of more than 100m are possible with 32 antenna paths.

1.4 PA Power Back-Off 7

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Fig. 1.6 Link budget calculations assuming 5dBm PA output power, 8dB RXNF and 15dB outputSNR: a FSPL at 60GHz, and b possible communication distances versus the number of antennapaths in both the TX and RX neglecting oxygen attenuation and assuming no rain conditions

1.4 PA Power Back-Off

Higher datarates can be achieved if more bits are transmitted in a symbol. In IEEE802.11ad standard, signle-carrier QPSK modulation is used to cross the 1.5Gb/sboundary and 16-QAM is used to achieve 4.62Gb/s datarate. One drawback of usinghigher-order modulation signals (e.g., 16-QAM) is the large ratio between its peakand average signal levels. This means that a power amplifier has to transmit at muchlower power levels than what it is capable of, in order to guarantee a linear transferfunction. As shown in Fig. 1.7, clipping may occur if the signal peak is higher thanthe compression point (P1dB) of the PA. In a class-A PA, this means that a largeamount of DC power is used to generate a small AC signal, leading to much lowerefficiency. For example, the drain efficiency of a class-A PA operating at 5dB back-off is often as low as 1 to 5to 30% in saturation can be achieved, as will be shown

Fig. 1.7 Illustration of the need for power back-off: a the input signal peaks are lower than thecompression point causing no distortion, and b the input signal peaks are larger than the compressionpoint causing signal clipping

8 1 Introduction

in Chap. 3. Therefore, the PA pays the price of increasing the modulation index inboth output power and power consumption.

A QPSK signal will also experience variable envelopes due to signal filteringin the digital domain to shape the signal and confine its frequency usage. Typicalpeak-to-average power ratio (PAPR) values at a filter roll-off factor (r) of 0.25 are2dB, 4.9dB, 6.8dB and 7.5dB for BPSK, QPSK, 16-QAM and 64-QAM signal,respectively. The actual power back-off can be less than the signal PAPR due to thelow probability of high peaks, which results in negligible degradation of the signalquality (e.g., bit-error rate)when slightly distorted (e.g., by clipping) [Bourdoux08b].A value of 5dB output power back-off is used as a benchmark in the rest of this work.

1.5 Organization of the Book

The book mainly covers two topics aiming at achieving low-power TX front-endimplementations for 60GHz applications. The first topic focuses on the conven-tional direct conversion TX architecture and improves its maximum and back-offPA efficiencies. The second topic introduces the polar architecture for mm-wavefrequencies, where a 60GHz RF-DAC is used for amplitude modulation. Chapter 2discusses few design considerations for highly-efficient 60GHz TX front-ends andshows its design procedure including a multi-stage class-A/AB PA preceded by anI-Q upconversion mixer. Three chips in 40nm-LP and 28nm-HPM CMOS tech-nologies are presented in Chap. 3 together with their measurement results showingmaximum and back-off TX efficiency improvements. Chapter 4 shows system con-siderations for mm-wave polar TX, describes the TX architecture, and presents twochips in 40nm-GP CMOS with their circuit description and measurement results.The final conclusions are drawn in Chap. 5 together with other proposals for futurework to achieve even further reduction in the TX power consumption.

Chapter 2Design Considerations for High-DatarateLow-Power 60GHz TX Front-Ends

High datarates can either be achieved by increasing the channel bandwidth or thesystem modulation complexity or both. As mentioned in Chap. 1, the 802.11adstandard using the 60GHz band provides large bandwidth that allows for a datarate of1.76Gb/s if one channel is used for transmission with BPSK modulation. Increasingthe datarate further requires bonding more channels or increasing the modulationcomplexity. Beside being limited by the system signal-to-noise ratio (SNR), higherorder constellations cause the transmitted signal to show a variable envelope. Thehigher the order is, the larger the signal peaks are compared to its average value.So, beside the large RF bandwidth requirement in the transmitter front-end, the PAneeds to be linear to accommodate this variable envelope signal without distortion.The most linear class of a PA is class-A. So, throughout the book, we take class-A asa reference, and compare with it whenever needed to justify the use of another classor TX architecture.

2.1 PA Considerations

In this section, we go through the initial design trade-offs of a mm-wave PA inadvanced technologies.

2.1.1 Width Selection

A common-source transistor is the simplest PA active cell. The input impedance canbe conjugatelymatched tomaximize the power gain. The output impedance can eitherbe optimized for maximum power gain (using conjugate matching) or for maximum


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10 2 Design Considerations for High-Datarate…

output power (using load-pull simulations). In the following analysis, we assume thatthe capacitance at the transistor output is compensated by an inductive componentat the frequency of interest. A PA operating in class-A and delivering its maximumoutput power should have an output resistance that allowsmaximum possible voltageand current swings. Figure 2.1 shows an example, where the output voltage is ideallyallowed to swing to 2*VDD (peak to peak). For maximum output power in class-A,the output current should be allowed to swing to 2*IDD. This requires Rout to beVDD/IDD. This value is intentionally causing some reflections at the PA output tomaximize its power capability and is different from the case of conjugately matchedload (i.e., when maximizing the power gain), where RL,opt would equal ro and Rout

is ro/2.The DC power consumption (PDC) is VDD*IDD. The AC power delivered to the

load, assuming peak voltage and current values, is:

Pout = υout ∗ iout2

= υ2out

2Rout= i2out ∗ 2Rout (2.1)

For a class-A PA to be optimized for maximum output power, the current signalkeeps following the voltage signal with a slope (i.e., Rout) of VDD/IDD. At maximumoutput power, υout and iout are VDD and IDD, respectively. Thus the output powerbecomes:

Pout,max,A = VDD ∗ IDD

2(2.2)

This causes the maximum drain efficiency (DE or ηD) to be constant and inde-pendent of any design parameter in a class-A amplifier, where:

ηD,max,A = Pout,max,A

PDC= 1

2= 50% (2.3)

Thus, by increasing the transistor width at the same biasing conditions (i.e., supplyand gate voltage), the DC power consumption and the output power increase linearly(see Eq. 2.2), while the drain efficiency remains constant.

In

VDD

ro RL,opt In

VDD

RL,opt,eq Rout=

Cb Cb

Fig. 2.1 A simple PA with common-source transistor biased in class-A

2.1 PA Considerations 11

In order to estimate the small-signal power gain, the following equation can beused:

Gp = PoutPin

= υ2out/2Rout

υ2in/2Rin

= A2v ∗ Rin

Rout= g2m R

2out ∗ Rin

Rout= g2m Rin Rout (2.4)

For the small-signal model of Fig. 2.2, the input impedance is rg+1/jωCgs.The input admittance can then be written as follows:

Yin = jωCgs + (ωCgs)2rg

1 + (ωCgsrg)2(2.5)

Assuming that the input pole is much higher than the operating frequency, thedenominator reduces to 1. Thus, the input resistance becomes:

Rin = 1

rg

1

(ωCgs)2(2.6)

rg is inversely proportional to the transistor width and Cgs is proportional to thewidth, causing Rin to be inversely proportional to the width. For the output resistance,ro is inversely proportional to the DC current and the transistor width. If the PA isconjugately matched at the output, Rout is ro/2 and is inversely proportional to thewidth. If the PA is optimized for maximum output power, Rout is VDD/IDD, whichis also inversely proportional to the DC power consumption and transistor width.Therefore, for Gp, gm is proportional to the transistor width, while Rin and Rout areinversely proportional to the width. Thus, Eq. 2.4 concludes that the small-signalpower gain remains constant with the transistor width.

As shown in Fig. 2.3, a simulation of a minimal length single common-sourcetransistor in 28nm technology confirms the above-mentioned conclusions and showsa linear maximum output power (the compression point is also expected to have thesamebehavior), constantmaximumpower gain and (almost) constant drain efficiencyversus transistor width. Thus, the choice of the PA transistor width only depends onthe required output power. In a practical design, the maximum width will be limitedby the interconnect parasitics and the matching network losses. These losses aredue to the resulting very low transistor output impedance levels, which require largeimpedance transformation ratios.

Fig. 2.2 A simple transistorsmall-signal model

G D

S

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gmVgs


Fig. 2.3 Simulatedperformance of asingle-transistorcommon-source PA versusits width

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10

15

20

25

30 60 90 120 150 180 210 240

Psat_dBmGmaxIdc_ssPsat_mW

Psat

(dBm

), G

max

(dB)

Total Width (µm)

Idc(m

A), Psat (mW

)

2.1.2 Power Combining and Stacking

When the maximum transistor width is achieved and the output power still needs tobe increased, a series combiner can be used as shown in Fig. 2.4a. In this case, thetotal output resistance of the combined PA is double that of each single PA. Whileboth PA’s use the same supply, the DC power consumption and the maximum outputpower are doubled. Thus, the combined PA has the same maximum drain efficiencyof the single PA.When the PA inputs are connected in parallel, the input power is splitbetween the two PA’s. Each PA amplifies the signal with the same power gain, thenthe output powers are combined. Thus, the total power gain of the combined PA’sis the same as that of the single PA. Another advantage of power combining is thepossibility to switch part of the combined sections off [Zhao12a], which saves somepower when large output power is not needed according to the application scenario.The main disadvantages of power combining are the doubled occupied PA area andthe introduced losses due to the input splitter and the output combiner. Losses atthe input only affects the power gain, while losses at the output affects power gain,maximum output power and drain efficiency. Power combiner losses of less than1dB at mm-wave are reported [Zhao13].

If two transistors are stacked (see Fig. 2.4b) at twice the supply voltage, the DCpower consumption and the maximum output power are doubled at the same drainefficiency. Practically, this depends on howefficient the current signal is injected fromthe common-source transistor to the Cascode (common-gate) transistor. Assumingideal current injection to the Cascode transistor, the stacked configuration has thesame gm as the single transistor. Neglecting the gate-drain capacitance of the transis-tor (Cgd =0), the stacked configuration will not change the input network of the PA.Thus, Rin remains the same. As the output resistance of the stacked configurationbecomes larger, the power gain is also larger (see Eq. 2.4). Practically, Cgd existsshowing reduced power gain for the single transistor PA. This shows another advan-tage of stacking as it adds extra isolation between its input and output ports, whichimproves the PA gain and stability. A tuning element may be required to cancel theeffect of the parasitic capacitance at the common node between the two transistors.This can affect the PA bandwidth, which is required to be larger than 9GHz for802.11ad applications. Another concern is to keep control over the circuit’s reliabil-


RLPA1

PA2

VDD

VDD

In

OutVbias

2*VDD(a) (b)

Fig. 2.4 Increasing the output power using a series combiner or b stacking configurations

ity and variability, especially for the Cascode transistor, which has a maximum drainvoltage of 4*VDD.

2.1.3 Balanced Operation

If two similar transistors are excited differentially with an input source (see Fig. 2.5),the input voltage, and thus the output current per transistor is divided by two. Thetotal differential output voltage is iout/2*2Rout, i.e. equal to the output voltage ofa single transistor at the same input voltage. In this push pull configuration, theinput and output resistances are doubled. From Eq. 2.4, we see that the power gainof a differential configuration is the same as that of a single-ended one. At themaximum output power (i.e. saturation) in class-A, the output voltage and currentper transistor reachVDD and IDD, respectively. The total output current in the balancedconfiguration is the same (i.e., IDD), while the total output voltage is doubled (i.e.,2VDD). Therefore, referring to Eq. 2.2, the total maximum output power (i.e., atsaturation) is doubled. As the DC power consumption is doubled, the PA drainefficiency remains constant. So, in summary, the balanced configuration doubles thePA output power at the same gain and drain efficiency. Other advantages includecommon-mode rejection and the possibility to consider Cgd neutralization in the PA,as will be explained in the following section.

2.1.4 Cgd Neutralization

Neutralizing the gate-drain parasitic capacitance (Cgd) of a transistor (see Fig. 2.6)is usually used at mm-waves to cancel the miller effect [Chan09]. This increasesreverse isolation that improves stability, where a unilateral device is unconditionallystable if |S11|< 1 and |S22|<1 [Gonzalez96]. Neutralization also increases the power


+

-

+

-

Vout

i /2out

Vin

Rout

Routi /2out

Fig. 2.5 Balanced (push pull) configuration

gain of the device, where the maximum stable gain (Gmsg) is |S21|/|S12|. Ensuringstability in the last PA stage is important to withstand load impedance variations dueot the antenna. Power gain values of less than 10dB are usually expected at 60GHzdue to operation close to the transistor fT. Therefore, higher power gain in the lastPA stage is power efficient as it allows using smaller drivers.

The testbench of Fig. 2.7 is used to compare the push-pull PA configuration withand without Cgd neutralization. Here the PA is connected to ideal baluns and 50�

ports at the input and output. A 28nm minimum length transistor with ultra-lowthreshold voltage (around 380mV) and 1u*108 total width is used in the PA. The PAis initially biased at 0.5V, and the nominal operating frequency is 65GHz (4GHzpre-shift is used to account for the in-house model inaccuracy).

The required neutralizing capacitor value (Cneut) can be extracted from an S-parameter simulation using the testbench of Fig. 2.7. As shown in Fig. 2.8, a capac-itance value of 28 fF achieves the highest stability factor (Kf), and thus, is the best

Fig. 2.6 Cgd neutralizedpush pull amplifier

In Out

Cneut

Fig. 2.7 Testbench used tocharacterize a single-stagePA

Vbias

VDD50

IdealBalun

IdealBalun


Fig. 2.8 Choosing theneutralizing capacitor valuefor a push-pull PA stage

estimation for the transistorCgd. The plot also shows themaximumstable gain (Gmsg),which is the maximum achievable power gain at Kf value of ‘1’. When the transistoris neutralized, S12 is minimum andGmsg is maximized. Themaximum available gain

Gmax takes the actualKf value into account,whereGmax isGmsg × (K f −√K 2

f − 1).

Therefore, when Kf is larger than ‘1’, Gmax starts to reduce below Gmsg. Choosinganother value for Cneut targeting higher Gmax reduces the unconditionally-stable fre-quency range and may lead to the risk of PA instability with process variations.

Figure 2.9 shows Gmsg, Gmax and Kf versus frequency before and after usingneutralization. In the non-neutralized version (i.e., Fig. 2.9a), a 14� resistor is placedin series to the input port to stabilize the PA at the frequency of interest. However,the stability factor goes below ‘1’ and the circuit is potentially unstable at lowerfrequencies. Two 28 fF capacitors to neutralize Cgd ensures stability over a widerange of frequencies, as shown in Fig. 2.9b. Moreover, it increases the maximumstable gain in this example from 11.4 to 20.5dB, leaving 14.9dBmaximum availablegain, which is 4.9dB higher than the case without neutralization. These gain valuesassume conjugately matched input and output terminals, and the final gain benefit ofthe neutralized version will change after choosing the optimum load value.

Figure 2.10 shows the circles of power gain (Gp), output-referred 1-dB compres-sion point (P1dB) and drain efficiency (DE) on the Smith chart, and compares thepreviously used amplifier with and without neutralization. In Fig. 2.10a without neu-

(a) (b)

Fig. 2.9 Stability of a push-pull PA Stage a without and b with neutralization


tralization, the maximum power gain point (i.e., at conjugately matched input andoutput ports) is 10dB, the maximum output 1dB compression point is 12.9dBm andthe maximum drain efficiency (the input power is swept up to 25dBm) is 65.8%.Circle steps are 1dB in P1dB and Gp circles, and 5% in drain efficiency circles. Asthe nominal threshold voltage is around 380mV, the PA is initially biased in class-A, then goes to class-AB when driven in saturation, allowing maximum efficiencyvalues above 50%.

In Fig. 2.10b when neutralization is used, the maximum gain value increases to14.9dB, the maximum compression becomes 12dBm and the maximum drain effi-ciency is 57.6%. The neutralization capacitors are seen as extra loading path to thePA output ports. Therefore, the output resistance of a neutralized PA is reduced whenthe source impedance is taken into account. This causes a limited (0.9dB in this case)effect on themaximumP1dB. Themaximum efficiency is also reduced together withthe output power at the same DC power consumption. However, the linearity andefficiency advantage of the PA without neutralization cannot be simultaneously uti-lized without sacrificing power gain. This is because of the different load impedancesrequired for each criterion (see Fig. 2.10a). The 14� resistance added at the inputjust pulls the PA from conditional stability to the unconditional-stable region with-out a large stability margin. Therefore, the load reflection coefficient is just belowunity, and the optimum load for maximum power gain (i.e., conjugate of the outputimpedance) is placed close to the Smith chart edge. Adding more resistance to pro-vide a higher stability margin and pushing the maximum gain load towards the chartcenter will cause a significant degradation of the maximum achievable power gainvalue. Thus, in any case, a trade-off needs to be made between gain and linearityin the non-neutralized PA. Lower gain implies higher output power in a previousgain stage, causing the efficiency advantage of the non-neutralized PA stage to beobsolete. On the other side, neutralization provides a high stability margin and amaximum power gain load impedance placed far from the Smith chart edges withoutsacrificing gain. As shown in Fig. 2.10b, the optimum load impedance points for Gp,P1dB and DE are located close to each other, allowing to achieve their maximumvalues simultaneously without a significant trade-off.

Table 2.1 compares the simulated input and output parallel equivalence of theresistance and capacitance of our example PA with and without neutralization. Thetestbench of Fig. 2.7 is still used in this simulation. Z11 is used to determine theunloaded Rin andCin, where the output port is left open. Y22 is used for the unloadedRout and Cout, where the input port is shorted. The values are also compared witha practical PA load, where the input and output ports are conjugately matched forsimplicity. The available gain (Ga) and power gain (Gp) circles are used for thispurpose, which are equivalent to the simultaneous match source and load impedancevalues, respectively.

When the PA is only loaded with its transistor parasitics, the input resistancein the differential case is much affected by the Cgd path. Neutralization isolatesthe output network from the input, leading to a significant increase in the inputresistance. The neutralized input capacitance is reduced, where only 2Cgd are placedin parallel to Cgs instead of the miller equivalent (i.e., Cgs(1−Av)) when a high


(a) (b)

Fig. 2.10 Load pull simulations on a push-pull PA stage at 0.5V Vbias: a without and b withneutralization

Table 2.1 Effect of neutralization on equivalent PA input and output resistance and capacitancevalues

Unloaded PA Loaded PA (conjugate match)

Differential Stabilizeddifferential

Neutralized Stabilizeddifferential

Neutralized

Rin (�) 47.1 52.2 384.2 250 313.8

Cin (fF) 52.3 29.5 45.9 55.8 49.7

Rout (�) 76.4 67.5 76.4 72.8 44.3

Cout (fF) 41.8 54 55.6 131.2 50.9

output impedance is assumed [Gray09]. Neutralization is considered as an extraloading path to the output impedance. If the gate resistance is neglected, only extracapacitive components appear at the output due toCgd andCneut paths. A 14� resistoris used at the input port of the differential non-neutralized amplifier for unconditionalstability. The impedance values aremuch affected by the source and load impedanceswhen the amplifier is conjugately matched in the differential case due to the poorisolation between the input and output ports. On the other hand, the neutralized PAparameters are much less affected, except for the output resistance which is reduceddue to the source resistance seen through Cgd and Cneut paths.

2.1.5 Deep Class-AB Operation

One drawback of class-A PAs is the poor efficiency values at power back-off. Asmentioned in Chap. 1, this is required when dealing with variable envelope sig-


Vin

Vdc

Vth

Iout

Idc

0

t

t

Fig. 2.11 PA operation at different biasing conditions: a class-A and b class-AB

nals (i.e. complex modulation schemes with large modulation index), targeting highdatarates. Figure 2.11 shows the input voltage and output current waveforms of acommon-source PA configuration, where the input power level is adjusted for anequal output swing. When the transistor is biased in class-A, the DC current is fixedregardless the signal amplitude. In class-AB, on the other hand, the DC current isproportional to the signal amplitude. Thus, less power is consumed in class-ABwhenthe PA operates at back-off.

The effect of biasing the PA in deep class-AB on its performance can be viewedon the Smith chart by biasing the push-pull PA of Sect. 2.1.4 with 0.3V at the gate.Figure 2.12 shows the PA load-pull simulations with and without neutralization. InFig. 2.12a, themaximumpower gain, 1-dB compression point and drain efficiency are6.1dB, 17.8dBm and 75.5%without neutralization, respectively.With neutralizationin Fig. 2.12b, the maximum Gp, P1dB and DE are 11.2dB, 17.4dBm and 60%,respectively. The high efficiency values, especially in the case without neutralization,suggest that the PA is close to operation in class-B, where the maximum efficiencyis 78.5% [Cripps06]. This normally occurs when the current waveforms are closer toa square-wave shape, carrying higher harmonic components. At 60GHz, however,the second harmonic component is at 120GHz, which is difficult to pass, especiallyafter using passive networks (e.g. for matching). Thus, the output waveforms will befiltered, and these efficiency values are not expected to exceed the 50% range afterincluding the matching network.

Figure 2.13 shows how the optimum load points for maximum Gp, P1dB and DEchange when the bias voltage goes from 0.3 to 0.8V. As shown in Fig. 2.13b for theneutralized PA, the optimum load values for maximum Gp, P1dB and Gp at 0.5Vbiasing lie approximately on the trade-off line of other biasing voltages including0.3V bias. Thus, it is possible in a neutralized PA to choose the load impedancevalue (e.g., 0.48 ∠ 135 in this case) as a good compromise between all performanceparameters at all gate bias conditions.


(a) (b)

Fig. 2.12 Load pull simulations on a push-pull PA stage at 0.3V Vbias: a without and b withneutralization

(a) (b)

Fig. 2.13 Effect of changing the bias (from 0.3 to 0.8V) on the optimum load for maximum Gp,P1dB and DE for a push-pull PA stage: a without and b with neutralization. Values are shown forbias voltages 0.3, 0.4 and 0.8V in the following format: 0.3, 0.4–0.8V

Taking the load impedance value as 0.48∠135, Fig. 2.14a shows the neutralizedPA performance at different gate bias voltages. The P1dB reduction after 0.6V isbecause the optimum load for maximum P1dB moves away from the chosen loadimpedance. Below 0.4V, the PA goes into deep class-AB, where the gain curve startsto have its compression point extended then experience some expansion [Cripps02].This extends the gain compression to higher values at the expense of lower gain. Theminimum useful gate voltage is 0.3V, where the gain curve expands by <1dB (seeFig. 2.14b). Afterwards, the gain curve expansion will affect the signal quality (i.e.the system EVM and output PSD).


(a) (b)

Fig. 2.14 Simulated performance at 0.48∠135 load with neutralization: a versus Vbias, and bversus output power at 0.5V (solid) and 0.3V (dotted) Vbias

Fig. 2.15 Current consumption at 0.48∠135 load anddifferent gate bias voltageswith neutralization

Figure 2.14b compares between the 0.5 and 0.3V gate bias voltages when theinput power is swept to show the efficiency advantage of operating in deep class-ABwith variable envelope signals. At 5dB back-off from the input 1-dB compressionpower, the drain efficiency goes to 11.7% at 0.5V. When the PA is biased in deepclass-AB (i.e. 0.3V), the 5dB back-off efficiency is increased to 39%. The back-offefficiency improvement at 0.3V will be much reduced when taking the driver stageinto account, where a higher linearity will be required due to the reduced power gainin deep class-AB. Moreover, these efficiency values at 0.5 and 0.3V biasing will bereduced after matching losses are taken into account.

Figure 2.15 shows the current consumption of the neutralized stage at 0.48∠135load. The PA operates in class-A at 0.6V. At higher voltages, the bias current isconstant at least up to−5dBm, corresponding to the compression point, then it startsfollowing a class-AB behavior as the amplifier gets overdriven. At lower voltages, theclass-AB range is wider, where the current is constant up to approximately−10dBm.

Figure 2.16 shows the effect of input power (and bias voltage) on the amplifier’soutput phase (i.e., AM-PM distortion). The simulated effect of AM-PM distortionon EVM for a modified Rapp model is shown in [Kulkarni16], where a phase errorof 2◦ limits the EVM to −30dB. The phase error versus input power is most flat


(a) (b)

Fig. 2.16 Simulated AM-PM performance: a versus Pin at different Vbias values, and b at P1dBreferred to small-signal output

using a bias voltage between class-A and AB with more error in deep class-AB. Asthe signal experiences phase variations during operation, a phased array system willexperience uncertainty in its beam steering angle. A worst-case AM-PM phase errorof 1◦ to 5◦ between two antenna paths in a two-antenna-path system causes an errorin the beam direction of 0.3◦ to 1.6◦ (see Eq. 1.3).

2.2 Output Matching Network

The optimum load for the PA is usually not at 50�. Thus, in most cases, a matchingcircuit is required at the PA output to transform the 50� to the required load for thePA.

2.2.1 Topology Selection

Next to providing the required impedance transformation, the matching networkshould also allow biasing the PA appropriately. Thus, for example, a capacitorbetween VDD and the PA output is not allowed. The load resistance is also required tobe decoupled in DC. Transmission line solutions are avoided as they occupy a largelayout area. So, this leaves us with either LC, pi (i.e. L-C-L) or transformer match-ing. As the LC network has one less degree of freedom, only the pi and transformermatching networks are compared, as shown in Fig. 2.17.

The pi-matching network involves inductors, which are normally implementedwith higher quality factor (Q) than a transformer, and suggests that the pi-matchingnetwork has less losses. However, the finite quality factor of the pi-matching capac-itors and their connecting lines limits the pi-matching network loss advantage overthe transformer. Moreover, the two inductors of a pi-matching network are placed


FromPA

To50

FromPA

To50

L1

L2

L4

C1

L3C2

VDD

VDD

FromPA

To50

k2

L4

FromPA

To50

k1

L1 L2

L3

VDD

VDD(a) (b)

Fig. 2.17 PA output matching using a a pi network and b transformer

separately and take more area (almost double) than a transformer. Therefore, thetransformer is used for the design of the matching network. A differential PA config-uration is preferred to double the output power (see Sect. 2.1.3), and a single-endedoutput (see Fig. 2.17b) is used to avoid an external balun while measuring the outputpower with probes.

Note that it is usually necessary to include a capacitor at the transformer output(i.e. in parallel to the 50� load) as an extra degree of freedom. This is because thecoupling factor (k) cannot usually exceed 0.8 in bulk CMOS technologies, whichlimits the possible synthesized impedance values (see Sect. 2.2.2). The PA outputpad can be used directly (or after beingmodified) to serve as the required transformeroutput capacitance. At 60GHz, a 50 fF capacitance such as the output capacitanceof our neutralized PA can be tuned out with a 140pH inductor. Values that are lessthan 50pH are difficult to implement as they become very short and sensitive to anyignored parasitics. Values that are more than 350pH start to have their self-resonancefrequency close to 60GHz, which brings a lot of variation to the designed inductancevalue and risk to degrade the operation of the transformer.

2.2.2 Design Procedure

Once we have an optimum load point for the PA, 0.48∠135 for instance, then wecan design the matching network separately. The input impedance of the matchingnetwork loaded by50� should equal to the optimumPA load point.Here the balanced

2.2 Output Matching Network 23

configuration of Fig. 2.17b is used with a ground connection at the secondary sideto provide a single-ended output configuration.

Assuming an infinite quality factor and a resistive load, the input impedance ofthe transformer is (see Eqs. A.12 and A.13):

Zin = k2ω2L1L2RL

R2L + (ωL2)2

+ jωL1(1 − k2(ωL2)2

R2L + (ωL2)2

) (2.7)

These are two equations in three unknowns (i.e., L1, L2 and k) and can be solvedtogether with the transformer Gp to find the optimal transformer design parameters.

However, it can be shown that with a limited range of the coupling factor (k),not all impedance values can be synthesized. Therefore, an extra capacitance at thebalun output may be required. The testbench of Fig. 2.18a is used to simulate theinput impedance of the PA output matching network including a balun and an outputcapacitor (C1) loaded by 50� at 65GHz. The transformer used in this simulation isshown in Fig 2.18b, where it represented by primary and secondary lossy inductorsL1 and L2, and a coupling coefficient. If the series resistance (r1 or r2) is written asa function of the quality factor (i.e., r=ωL/Q), then the transformer can be modeledby L1, L2, Q1, Q2 and k.

Figure 2.19a shows a sweep of L1, L2 and k with infinite Q1 and Q2. The induc-tance values are swept from 50 to 35pH and k is swept from 0.2 to 1 in steps of0.2. If the coupling coefficient of ‘1’ (the dotted line) is not available and k can onlygo up to 0.8, we see that there will be a wide range of impedances that cannot beimplemented. In Fig. 2.19b, a C1 value of 50 fF is used with a maximum k of 0.8,and we see that most of the inductive impedances are now possible to implementthanks to the extra degree of freedom.

Assuming initial values for k and Q helps to design the transformer with sufficientaccuracy. These can be extracted from a first simulation of a transformer in the targettechnology. The transformer inherent losses are inversely proportional to k and Q[Long00]. Therefore, the minimum possible matching loss can be obtained froma Gmax simulation, where the matching network input and output are conjugately

IdealBalun 50C1

Matchingnetwork

(a)

kL1/2

kr1/2

L1/2

r1/2

L2/2

r2/2

L2/2

r2/2

(b)

Fig. 2.18 a Testbench used for the design of the PA output balun, and b its variable transformer


(a) (b)

Fig. 2.19 Sweeping L1, L2 and k: a without C1 and k is swept from 0.2 to 1 in steps of 0.2 (k=1is in a dotted line), and b with C1 while k stops at 0.8

matched. coupling coefficients from 0.45 to 0.75 and quality factors between 10 and20 are expected for octagonal transformers with turns ratios of 1 or 2 in bulk CMOSwhen using the two top metal layers. A Gmax value of −0.76dB is simulated usingthe testbench of Fig. 2.18a with k of 0.7 and Q of 15. Thus, this is the minimumexpected losses for a matching network with these specifications.

The next step is to find the value of L1, L2 and C1 to achieve the target impedanceat the input when loaded with 50�. Equating the real and imaginary values of thetarget impedance to the real and imaginary parts of the matching network inputimpedance will result in two equations in three unknowns. This means that there aredifferent combinations of L1, L2 and C1 that can provide the target input impedance.A losslessmatching networkwill have its output port conjugatelymatched if the inputport also has a conjugate match [Gonzalez96]. However, our matching network hascertain losses due to the finite Q, and the output port is not necessarily matched if theinput port is. Thus, the different parameter combinations will have different outputimpedance values, and they will differ in the total matching network loss due to thereflections at the output 50� port.

One way is to simulate the input impedance (or reflection coefficient S11) andchoosing L1, L2 and C1 values that provide the target 0.48∠135 value, then com-paring their Gp. An easier way is to use the conjugate value of 0.48∠135 in the inputport instead of 50�, then simulating for maximum S21. In this case, the final L1,L2 and C1 values will provide the target impedance while matching the output to50� to minimize the total matching network losses. The second method implementsa matching network with the lowest possible losses for our neutralized PA, wherethe target load impedance is so close to the amplifier’s output impedance. However,if the target impedance is far from the amplifier’s output impedance, then input portof the matching network testbench (Fig. 2.18a) should hold the amplifier’s outputimpedance value. Then the matching network parameters should be swept for the


Fig. 2.20 Sweeping L1, L2 and C1 for 0.48∠135 input impedance with minimum loss

target impedance, then the values providing the maximum S21 should be selected.Figure 2.20 shows a simulation of the second method, where the target impedanceis the same as the PA output impedance in a our neutralized PA (0.48∠135). A max-imum value of −0.805dB is simulated for S21 with L1, L2 and C1 values of 54pH,60pH and 80 fF, respectively. S21 takes into account both reflections at the input, atthe output and the inherent loss in the transformer. Gp takes only the inherent lossand the output reflections into account, and a value of −0.79dB is simulated for thechosen matching network parameters (i.e., only 0.015dB and 0.03dB are due to theinput and output reflections, respectively).

2.2.3 Layout Considerations

Implementing stand-alone inductors or transformers atmm-waves is usually straight-forward. The main concern is how applicable the design is when instantiated in therest of the circuit layout. Therefore, the passive component is best simulated anddrawn in a surrounding ground ring that shields the transformer from the surround-ing layout components. The passives are usually designed in the top available metallayers to maximize the distance (around 2µm) to the lossy substrate. A distanceof 5–10µm between the transformer and the ground shield is usually sufficient tominimize the effect on the quality factor. Figure 2.21 shows an example of a 1:1transformer layout implemented in M8 andM9 top metal layers with 1µm thicknesseach and 2.5µm distance from M8 to the substrate. Primary and secondary induc-


Fig. 2.21 1:1 transformerlayout with M8 (left red)primary and M9 (right blue)secondary, and M1–M7(green) ground shield

tance values of 50pH are extracted for this transformer with an electromagnetic-wave(EM) simulator with a track width of 3µm. The 36x36µm2 outside dimension (OD)layout shows quality factors of 18.1 and a coupling coefficient of 0.64. This bringsa Gmax (i.e., minimum inherent loss) value of −0.76dB. A similar Gmax value isobtained when the transformer model of Fig. 2.18b is used with k and Q of 0.64and 18.1, respectively. This gives an indication of the high modeling accuracy of thetransformer with only L’s, Q’s and k.

A practical layout would also include extra connections to other blocks (e.g., thePA output or the pad), which can either be simulated in an EM simulator separatelyor included in the transformer layout. Top aluminum metal layers could also be usedto route the supply coming from one side of the chip to the other side. It is also best totake such lines into account if they cross the transformer. More than one iteration isusually required to achieve the target impedance with the actual transformer takingall additional input, output and crossing lines into account.

2.2.4 Effect on PA Performance

Figure 2.22 shows the testbench used for simulating the effect of the transformeron the PA performance. The output ideal balun of Fig. 2.7 is replaced with thematching network consisting of the extracted transformer of Fig. 2.21 and a parallel80 fF capacitor (Cout). The practical optimal impedance value for the PA should be


Vbias

VDDReal Fixed

BalunIdealBalun

80fF

5050

Fig. 2.22 Testbench for simulating the effect of the output transformer on the last PA stage

(a) (b)

Fig. 2.23 Performance of PA including matching network at 0.5V Vbias versus Pin: a Pout andGp, and b Idc and drain efficiency

obtained after parasitic extraction. Here we keep using a schematic representation ofthe PA to evaluate the effect of the matching network only.

Figure 2.23 shows the simulation results with an output-referred 1-dB compres-sion point of 10.73dBm, a saturated output power (Psat) of 15.49dBm, power gain of13.72dB and a maximum drain efficiency of 54.1%. At 5dB output power back-off(i.e., 6dB Pin back-off), the drain efficiency is 7.8%. The output power is reducedby approximately 1dB compared to the case without a transformer (see Fig. 2.14a),which shows that only 0.24dB is lost in thematching network reflections. Fine tuningcan still be performed after all the PA parts are extracted.

(a) (b)

Fig. 2.24 Performance of PA including matching network at 0.3V Vbias versus Pin: a Pout andGp, and b Idc and drain efficiency


Theperformance at 0.3Vgate bias voltage is also evaluated.As shown inFig. 2.24,P1dB is 14.1dBm, Gp is 9dB, maximum DE is 52.2% and the drain efficiency at5dB back-off is 31.2%.

2.3 Multi-stage PA Design

The main purpose of the driver stage is to provide enough power gain in the amplifierto overcome the limited linearity of previous stages (e.g., upconversion mixer orbaseband amplifiers). Adding another stage to the PA of Sect. 2.2.4 results in a totalpower gain of around 25dB taking around 2.5dB margin to account for extra lossesdue to the complete PA layout extraction. Taking an input matching network intoaccount, the total 2-stage PA gain can be estimated as 23dB. This value is enough(10dB higher than target compression) to mask an output P1dB of at least −4dBmin a previous stage assuming that a total output 1dB compression point of 9dBmis targeted. As this value is feasible to achieve, the number of driver stages can belimited to one in this example. Adding more gain stages than necessary has severaldrawbacks: it consumes more power and reduces the output bandwidth. Moreover,more back-off is used in the previous stages in order not to saturate the PA.This causesthe number of used levels of a digital-to-analog converter (DAC) at the beginningof the transmitter chain to be reduced. This leads to less effective number of bits(ENOB) in the DAC, causing its quantization error to potentially dominate the linkbudget.

The same neutralized configuration of the last PA stage can be reused here, wherea high power gain is preferred in the driver stage. Thanks to the power gain of thelast PA stage, the driver stage can use a smaller size to save power consumptionwithout dominating the total PA output compression. A cascade analysis can be usedto determine the initial design width of the driver stage transistor, where 0.5V gatebias is assumed for the PA. The 1dB compression point (before the output balun) andpower consumption values from the last stage can be scaled linearly with the widthand reused in the calculations of the driver stage. Figure 2.25 shows the result ofa cascade analysis, where 1.5dB is assumed for the interstage transformer loss. An

20

25

30

35

40

-4

0

4

8

12

0 20 40 60 80 100

Total P1dBDriver P1dBTotal DE

P1dB

(dBm

)

Driver Transistor Width (µm)

Total DE (%

)

Fig. 2.25 Cascade analysis using 0.5V-based driver at different last stage gate bias voltages: a0.5V, and b 0.3V

2.3 Multi-stage PA Design 29

Fig. 2.26 Gp of the 40µmneutralized driver stageversus its gate bias voltage

4

6

8

10

12

14

16

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Gm

ax (d

B)

Vbias (V)

optimum transistor width of 30µm is calculated, where the total PA drain efficiencyis maximized. A 40µm transistor is used to give more margin when the last PAstage operates with lower gate bias voltage. This leads to an total P1dB and DE of10.2dBm and 37.8% compared to 10.7dBm and 54.1%, respectively, before usingthe driver stage. The total estimated power gain including the driver, the interstagetransformer, the output stage and the balun are 26.9dB.

Figure 2.26 shows a simulation of the testbench of Fig. 2.7 with 50� output portand 40µm transistor size and 10.2 fF neutralization capacitor. Gmax is the mainspecification for the driver, and it is swept over gate bias voltage. Gmax remainsflat after a gate bias voltage of 0.5V. Therefore, it can be used for the driver stage,providing a matched power gain value of 14.8dB similar to the neutralized amplifierwith 3×36µm transistor width used in the last PA stage.

The driver stage is conjugately matched to maximize the power gain. A similarapproach to the design of the output stage balun is adopted in the design of the inter-stage transformers. Conjugatematchingwill ease the design, where only S-parametersimulations are sufficient to choose the transformer parameters. Gp circles (using thetestbench of Fig. 2.7 with 50� output port impedance) are used to determine theoptimum driver load. As shown in Fig. 2.27, a load impedance of 0.47∠48 is targetedfor the interstage transformer design.

The testbench of Fig. 2.28 is used to find the transformer parameters that achievethe required driver load impedance. A variable transformer (i.e., with variable L1,L2, Q1, Q2 and k parameters) is used before the first PA stage in a differential mode.The transformer L1 and L2 are swept to maximize S21 (with 0.47∠-48 impedanceat the input port) with k of 0.7 and Q of 15. This two-dimensional sweep is sufficientto achieve the target impedance in this case. L1 and L2 values of 100pH and 90pH,respectively, are obtained. An extracted transformer layout with 100pH primary andsecondary inductance simulates k andQvalues of 0.7 and17, respectively, resulting ininherent losses (i.e.,−Gmax) of 0.73dB. When used in Fig. 2.28 instead of the inputvariable transformer, the real input transformer leads to a total Gp value of 12.32dBfor the testbench. This shows that losses due to output reflections of the interstage


Fig. 2.27 Determining the optimum load impedance for the driver (conjugate match) using Gpcircles

Fig. 2.28 Testbench used to find the optimal interstage transformer design parameters

transformer are 0.67dB, where the simulated Gp without the input transformer is13.72dB (see Sect. 2.2.4).

The driver is simulated together with the interstage transformer and the last PAstage. Figure 2.29 shows the large-signal simulation, where P1dB, Psat, Gp andmaximum DE values of 10.3dBm, 15.3dBm, 26.9dB and 40.25% are achieved for0.5V bias. The power and gain values are the same as calculated from the cascadeanalysis. The drain efficiency is higher than calculated 37.8%, because the last PAstage operates in class-AB when overdriven and consumes less power when loadedby the driver stage. At 0.3V last stage gate bias, P1dB, Psat, Gp and maximum

2.3 Multi-stage PA Design 31

(a) (b)

Fig. 2.29 PA simulation with 0.5V driver bias versus the input power: a at 0.5V output stage bias,and b 0.3V output stage bias

DE values of 13.4dBm, 14.7dBm, 21.5dB and 38% are simulated. At 5dB outputpower back-off, the drain efficiency values are 5.1% and 16% for 0.5V and 0.3V,respectively.

2.4 Upconversion Mixer Design

The upconversion mixer is transformer coupled to the PA and consists of two mainparts: the baseband transconductor, and the RF switching (mixing) stage. Figure 2.30shows a basic Gilbert mixer implementation, where the transconductor is imple-mented by a common-source transistor, and the switches are driven by the 60GHzlocal oscillator (LO) signal.

The transconductor should provide a gm at least sufficient to overcome lossesin the switching stage. A very basic calculation can give an initial feeling of therequired gm. For a P1dB of 0dBm, the saturated output power is few dB’s higherdepending on the class of operation. A 50% efficient class-A differential amplifier(Psat is (2Vds)2/2Rout) would require a differential output resistance of 300� for aPsat of 5dBm assuming a Vds of 0.7V to accommodate two stacked transistors (the

Fig. 2.30 Gilbertupconversion mixerschematic

LO+ LO+

LO-BB+ BB-

MSW

Mtrans


(a) (b)

Fig. 2.31 S-parameter simulations of a 60µm/60nm transistor: a gm and gm/go, and b Idc andgm/Id

transconductor and the switch). The output AC current in the 300� load is 4.7mA.A gm of 5mS is required to provide that current at a maximum input voltage of 0.9V(peak differential) and assuming no losses. A gm of 14mS is used for the initialdesign to relax the mixer driver swing requirements (450mV peak differential) andaccount for some switching losses (25% current loss). A gm of 14mS provides avoltage conversion gain of 4x (i.e., 12dB) in 300� resistance. If the mixer input portis referred to 50�, an equivalent power gain of 3dB is estimated.

Concerning the design of the transconductor, a non-minimal length transistor isused to increase the output resistance and improve the current injection efficiencyinto the switch. Figure 2.31 shows the extracted parameters of a transistor with 60µm(1µm×30×2) total width and 60nm length. A tansconductance of 14mS is obtainedat a gate voltage of 365mV, where the transistor operates in moderate inversion witha Vdsat of 80mV. The simulation is performed at a drain-source voltage (Vds) of100mV togivemore headroom for themixer switch.Better efficiency canbe achievedat lower gate voltage, and a wider transistor will be required to get the same gm. Thegm is halved when this transistor is used in a differential Gilbert mixer configuration.Aswe use I andQmixers to achieve a single sideband output spectrum, the equivalentgm is doubled back to 14mS.

DC simulation of the mixer shows that a minimal length, 8µmwide transistor forthe switch with a gate bias of 0.5V provides 80mVVdsat for the switch and 140mVVds for the transconductor. A bigger switch has lower input resistance, improvingthe current signal injected from the transconductor (leading to a better power gain),but also reduces its output resistance causing power gain reduction.

Figure 2.32 shows the testbench used to characterize the mixer, where a full swing(i.e., 2VDD peak differential) signal is assumed at the LO port. An approach similarto the PA design is adopted, where (large signal) S-parameter simulations are used tofind the output impedance (conjugatematch), and loadpull simulations are performedto find the optimum load for maximum output power.

The simulated S22 is 0.9∠−25.75, and a power simulation at conjugate match(and 200MHz input signal) shows that the output-referred P1dB is −6.1dBm andGp is 5.5dB. The optimum load for maximum power is 0.7∠25, where Fig. 2.33

2.4 Upconversion Mixer Design 33

VDDIdealBalun

50

50

50

50 50 ,

50

50 ,

50

Vg,trans

Vg,sw

90

90

Fig. 2.32 Testbench for upconversion mixer characterization

Fig. 2.33 Simulated I-Q mixer performance at 0.7∠25 load

shows that the output power is saturated at 4.3dBm with P1dB of 0.4dBm and Gpof 4.1dB. The I-Q mixer achieves the target specifications with 6.6mA.

A similar approach to the one of Fig. 2.28 is used to design the transformer betweenthe mixer and the PA, where a variable transformer is used at the input of the PA toobtain the transformer parameters. L1, L2, Q and k of 220pH, 290pH, 15 and 0.6,respectively provide the required 0.7∠25 load to the mixer. A lower coupling factoris used as the transformer has a non-unity turns ratio. Figure 2.34 shows the total TXfront-end performance including the mixer and the PA. At 0.5V in the last PA stage,


(a) (b)

Fig. 2.34 Total TX front-end performance at different second PA stage gate bias voltage: a 0.5V,and b 0.3V

the total simulated P1dB is 10.5dBm, Psat is 15.2dBm, Gp is 29.5dB, maximumTX drain efficiency is 36.4% and the whole TX consumes 79.5mA at 5dB outputpower back-off. These values show that the P1dB is not affected by the mixer thanksto the high PA power gain. At 0.3V in the last PA stage, the total simulated P1dBis 13.4dBm, Psat is 14.7dBm, Gp is 24.1dB, maximum DE is 34.2% consuming60mA at back-off.

Chapter 360 GHz TX Front-Ends in AdvancedCMOS Technologies with ImprovedBack-Off Efficiencies

The work on low-power TX front-ends started from an initial design [Khalaf13]that can be used for benchmarking. The reference design includes a transformer-coupled three-stage balanced class-A PA stages and a current-bleeding Gilbert-cellupconversion mixer. The chip (see Fig. 3.1) is implemented in 40 nm-LP CMOStechnology and achieves a P1dB of 9.3 dBm and a Gp of 26 dB. The TX front-endconsumes 160 mW from a 1.1 V supply with maximum and 5 dB back-off PA PAEof 13% and 2%, respectively, and occupies an area of 220 × 90µm2.

In this chapter, we summarize three TX front-end implementations targeting lowpower. The first two designs are in 40 nm LP technology, where the first is part of asingle antenna-path TX/RX testchip and the second is part of a 4-antenna path phasedarray system. The third implementation uses the same approach of the second in a28 nm HPM single antenna-path TX/RX testchip.

3.1 A TX Front-End in 40 nm-LP CMOS with Three-StageClass-AB PA

The main target in this implementation is to reduce the power consumption of thePA, especially at 5 dB back-off where the PA normally operates. As discussed inSect. 2.1.5, the PA power consumption is scaled down with the signal swing in aclass-AB operation, allowing a higher efficiency at back-off. Therefore, the designis optimized for operation in deep class-AB.

3.1.1 Circuit Description

The transmitter prototype is shown in Fig. 3.2, where each stage has a neutralizedpush-pull amplifier as in Fig. 2.6. Neutralization is adopted in this design to ensurestability and overcome gain reduction when the PA operates in class-AB. Further


35


https://doi.org/10.1007/978-3-030-16653-3_3

36 3 60 GHz TX Front-Ends in Advanced CMOS Technologies …

Fig. 3.1 The benchmarkchip in 40 nm-LP CMOS

PA

gain enhancement is obtained in the PA by using 1:1 octagonal transformers, whichhave a simulated Q of 12, compared to 8 for rectangular ones.

A zero-IF architecture is used for the transmitter. The outputs of the in-phase (I)and quadrature (Q) mixers are added in the current domain before being coupled tothe PA. An on-chip subharmonically injection-locked quadrature voltage-controlledoscillator (QVCO) [Mangraviti12] injects the 60 GHz signal (LOI and LOQ) tothe mixer switches for direct upconversion. The baseband signal (BBI and BBQ) isinjected directly from the arbitrary wave generator.

As shown in Fig. 3.3, an upconversion mixer based on a super source-follower(SSF) transconductor is used in this design. This mixer provides significant powergain prior to the PA, while linearity is kept high due to the feedback in the supersource follower. The feedback amplifier is formed by the input source follower M1,the resistance R and the connection from the drain of M1 to the gates of M2 and

Class-AB PA1:2

SSF-BasedMixer

I

LO I

LOQ

Stage1 Stage2

1:2

T LO

T LO

1:11:2

TU

OXT

Stage3

BB

QBB

Fig. 3.2 The three-stage class-AB TX front-end schematic

3.1 A TX Front-End in 40 nm-LP CMOS with Three-Stage Class-AB PA 37

Fig. 3.3 The supersource-followerupconversion mixerschematic

LO+ LO+

LO-

MSW

M2

BB+M1

M3 M2

BB-M1

M3

VDD

R

N:1

Vb

M3. Transistor M2 is a current source and M3 copies the current in M2 multipliedby a factor N, which is the ratio between the widths of M3 and M2. The transcon-ductance is proportional to N/R and does not directly depend on the DC current asin a conventional Gilbert mixer. Also, M3 (64µm) carries less DC current than theinput transistor in the Gilbert mixer of the TX benchmark (168µm), which improvesthe output resistance. Therefore, compared to the Gilbert cell, the SSF-based mixertopology provides larger power gain at the same power consumption.

3.1.2 Measurement Results

The transmitter is part of a bigger chip that also includes receiver and frequency gen-eration paths. The receiver includes a two-stage pseudo-differential neutralized low-noise amplifier (LNA), a passive direct downconversion I-Qmixer and a variable-gainamplifier (VGA). The chip input local oscillator (LO) signal is generated externallyat 20GHz, then injection locks a 60GHzQVCOat the third harmonic after extractingthe 4 phases and signal buffering [Vidojkovic12]. Figure 3.4a shows the whole chipwith 0.7 mm2 core area. The IC is fabricated in a 40 nm-LP CMOS technology with7 metal layers. For measurements the IC is mounted on a PCB with bondwires usedfor all connections except for the mm-wave signals, which are probed on-die. Thebondwires parasitics are not deembedded from the measured data. A 1.1 V powersupply is used for all circuits. Figure 3.4b shows a zoomed-in photo of the TX path,which occupies 270 × 120µm2. The core area is larger than the benchmark chip


TX

RX

LO

(a)

PA

(b)

Fig. 3.4 Class-AB chip photo in 40 nm-LP: a full chip, and b TX zoom-in

Pout

(dB

m)

-10

-5

0

5

10

15G

p (dB)

10

15

20

25

V2in,TX,rms /50 (dBm)

-30 -25 -20 -15 -10 -5 0

PoutGp

(a)Pd

c (m

W)

20

40

6080

100

120

140

DE (%

)

0

2

46

8

10

12

V2 in,TX,rms /50 (dBm)

-30 -25 -20 -15 -10 -5 0

PdcDE

(b)

Fig. 3.5 Class-AB performance versus input power: a TX output power and conversion gain, andb PA power consumption and drain efficiency

due ot the use of octagonal transformers instead of the rectangular ones to reducelosses.

Figure 3.5 shows a summary of the TX performance. The transmitter has a con-version gain of 22 dB and an output P1dB of 10.2 dBm. The average dc powerconsumption in this work is a strong function of the input power due to operation indeep class-AB. At 5 dB back-off, it only consumes 60 mW compared to 160 mWfor the benchmark PA. This leads to more than 2× efficiency improvement at 5dBback-off (i.e., 5.7% PAE in this work compared to 2% in the benchmark PA). Withan additional 30 mW for the mixer power consumption, the TX front-end consumes90 mW compared to 190 mW in the benchmark chip.

Figure 3.6a shows a sweep of gain and P1dB versus the PA gate bias settingswhen all the three stages have the same values. The TX is capable of providinga conversion gain of up to 36 dB. The compression point saturates to 4 dBm athigher bias settings because the optimum load for maximum P1dB changes withbias (see Fig. 2.13b), where the PA design is optimized for operation in deep class-AB. Figure 3.6b shows that the IEEE 802.15.3c spectral mask is satisfied whenapplying a standard-compliant 16-QAM modulated signal.

3.1 A TX Front-End in 40 nm-LP CMOS with Three-Stage Class-AB PA 39

P1dB

(dB

m)

0

2

4

6

8

10

12

Gp (dB)

10

15

20

25

30

35

40

Bias Settings0 10 20 30 40 50 60

PoutGp

(a)

Pout

(dB

m)

-60

-50

-40

-30

-20

-10

Frequency (GHz)55 56 57 58 59 60 61

RBW=3MHzVBW=300kHz

802.15.3c

(b)

Fig. 3.6 Class-AB TX performance: a versus PA bias settings, and b output PSD with 16-QAMinput signal

Tek 7102

(a)

3.5 Gb/s raw

7 Gb/s raw

(b)

Fig. 3.7 a Measurement setup, and b constellations

A worst-case EVM of −17 dB over the 4 60 GHz channels is measured when alink is made between the TX and RX of the same chip. Figure 3.7 shows the testsetup and the resulting QPSK and 16-QAM constellations.

Table 3.1 shows a summary of the measurement results and a comparison withother stage-of-the-art. The 5dB back-off efficiency is at least twice the values of otherimplementations. This shows the efficiency advantage of operation in deep class-ABat back-off.

3.1.3 Conclusion

Class-ABoperation is a simple and efficientway to improve the back-off efficiency ofmm-wave PAs due to the scalability of the power consumptionwith RF output power.The reduced gain due to lower gate bias is overcome in the prototype Tx front-end byseveral means. Neutralization increases gain and octagonal transformers yield lowerlosses. Also, the super source-follower-based upconversion mixer further improvesthe TX gain for the same power consumption. The TX achieves 22 dB conversion


Table 3.1 Comparison with state-of-the-art implementations

This work Benchmark Okada et al.[Okada11]

Siligaris et al.[Siligaris11]

Chan et al.[Chan10]

Boers[Boers10]

Technology 40 nm-LP 40 nm-LP 65 nm 65 nm 65 nm 65 nm

Supply (V) 1.1 1.1 1.2 1.2 1 1

Gain (dB) 22 26 18.3 18 20 30

P1dB (dBm) 10.2 9.3 9.5 8 8 6.8

PAEmax (%) 10.8 13 8.8 8 15 18

PAE5dB (%) 5.7 2 2.5 NA 2 2.3

Pdc (mW) 90 190 160.6 207 70 65 (PA)

gain and 10.2 dBm P1dB. The class-AB design has a PAE of 5.7%, which is 2.85×more than the benchmark class-A design. This leads to 100mW power saving in theTX, which consumes a total of 90 mW compared to 190mW in the benchmark TX.

3.2 A 4-Antenna Path TX Front-End with Two-StageClass-A/AB PA

This section presents an optimized TX front-end for use in a complete 60GHz phasedarray TX/RX 40nm-LP CMOS chipset [Vidojkovic13]. The target is to demonstrateshort range (<5 m) wireless connectivity for full 802.11ad datarate signals with 4antenna paths. The TX and RX architectures are shown in Fig. 3.8, where directconversion and analog beamforming approaches are adopted to provide electronicbeam steering with low power consumption. The RX front-end is the same as inSect. 3.1 with two-stage neutralized LNA and passive I-Q downconversion mixer.Frequency synthesis is based on integer-NPLLswith series coupling 60GHzQVCOs[Parvais10]. Phase shifting is combined with 4th-order low-pass filtering using gm-C-based biquadratic section in the baseband combiner [Szortyka15], while the TXuses separate signal splitting and phase shifting based on current-mode amplifiers[Szortyka12].


The TX front-end is shown in Fig. 3.9, where the SSF-based I-Q upconversion mixeris reused from Sect. 3.1. Two PA stages are used thanks to the active and passiveoptimization that yields a higher gain per stage. The design approach of Chap. 2 isapplied to the PA, where the last stage is optimized for operation in both class-A and

3.2 A 4-Antenna Path TX Front-End with Two-Stage Class-A/AB PA 41

4 2ΔΦ

ΔΦ

ΔΦ

ΔΦ

PLL

PLL

ref

4 2

4 2

4 2

44

44

444

44

4 4

44

4

4

44

4

4

4 4 4

2

I,Q

PA

LOBuffer

4

(a)

ΔΦ2 4

PLL44

ΔΦ2 4

ΔΦ2 4

PLL44

ΔΦ2 4

ref

4

4

44

4

4

4

4

4 4 4

I,Q

VGA

Biqad LPF

LNA

LOBuffer

(b)

Fig. 3.8 The 4-antenna path 40 nm-LP chipset architecture [Brebels16]: a TX, and b RX

Class-A/AB PA1:2

SSF BasedMixer

I

LO I

LOQ

Stage1

2:1

T LO

T LO

1:1T

UO

XT

Stage2 Q

BB

BB

Fig. 3.9 The two-stage class-A/AB TX front-end schematic

AB, while the first stage is conjugately matched. The PA input transformer ensuresa compromise between the power gain and linearity of the I-Q mixer. The PA usesneutralized push-pull amplifiers (See Fig. 2.6) progressively sized (minimal length51.2µm in the first stage and 144µm in the second stage) to achieve the target outputpower with maximum efficiency.

The octagonal 1:1 and 2:1 transformers used in the design are shown in Fig. 3.10.The 1:1 transformer uses vertical coupling with two parallel metal lines (i.e., M6 andM7) in its secondary to improve Q. The 2:1 transformer uses lateral coupling withtwo parallel metal lines (i.e., M7 and AP) for both its primary and secondary.


APM7M6

Width=5µmOutside dimension=55µm

(a)

Width=4.3µmSpacing=2µmOD=56.3µm

(b)

Fig. 3.10 Layout of the used transformers: a last-stage 1:1 transformer, and b intermediate-stage2:1 transformer

L (p

H)

90

100

110120

130

140

150

Q

0

5

10

15

Frequency (GHz)0 20 40 60 80 100

L1L2

(a)

L (p

H)

6080

100120140160180200

Q

0

5

10

15

Frequency (GHz)0 20 40 60 80 100

(b)

Fig. 3.11 Simulated performance of the transformers: a 1:1 transformer, and b 2:1 transformer

Figure 3.11 shows the simulated performance of both transformers. The 1:1 trans-former has an L1 (calculated as the imaginary part of Z11 divided by ω) of 103.6 pHand L2 of 107.9 pH with Q1 of 14.4, Q2 of 12.7 and k of 0.7. The 2:1 transformerhas an L1 of 148.8 pH and L2 of 65.2 pH with Q1 of 14.7, Q2 of 10.7 and k of 0.52.The inherent losses (i.e., with Gmax) of the transformers are 0.88 dB and 1.3 dB,respectively.


Figure 3.12 shows the complete TX die photo with the main blocks indicated. Thechip occupies 6 mm2 in 40 nm-CMOS and consumes a maximum total of 724 mWfrom a 1.1 V supply.

The measurement setup of the probed TX module is shown in Fig. 3.13, wherethe I-Q mixer baseband input is provided from an arbitrary-wave generator (AWG)and the 60 GHz TX output is sensed with a 150µm pitch GSG probe and analyzedwith a 60 GHz spectrum analyzer.

The TX performance for a probed single antenna path is shown in Fig. 3.14, wherethe analog baseband is designed to provide 0 dB gain. The TX achieves a P1dB and


FRONT-END

PLL1LOBUF

PLL2

OUT2 OUT1

OUT3 OUT4

I Q

IN

IN

6mm2

Fig. 3.12 TX chip photo

SPI Control + DC Supplies

60GHz Rohde&Schwarz FSUSpectrum Analyzer

(20KHz-67GHz)Tektronix

AWG 7102PA

OUT

Picoprobe67A-GSG-150um

PLL REF CLK

BasebandIN

0-880MHz

HP 8133APulse generator/divider

HP 83712BRF generator

(10MHz - 20GHz)

8dB attenuators

-35 to -5dBm

SMA connectors

1.6GHz

100MHz

Differential I-Q

Fig. 3.13 Measurement setup for the probed TX chip

gain values of 10.8 dBm and 31 dB, respectively, when the PA operates in class-A.In class-AB, the PA shows 8 dBm and 22.5 dB for P1dB and gain, respectively. TheDC power consumption of class-AB shows dependency on the input power startingfrom 17.1 to 46.2 mW compared to the (almost) fixed 76 mW of class-A. This PAefficiency performance is also shown, where a maximum PAE of 33% and 22.5% areachieved for class-A and AB, respectively. At 5dB back-off, PAE values for class-Aand AB are 4.9% and 7.4%, respectively.


Pout

(dB

m)

-20

-10

010

20

30

40

Gp (dB)

-20

-10

010

20

30

40

V2 in,TX,rms /50 (dBm)-35 -30 -25 -20 -15 -10 -5

Class-AClass-AB

(a)

Pdc

(mW

)

0

20

40

60

80PAE (%

)

0

10

20

30

40

V2 in,TX,rms /50 (dBm)-35 -30 -25 -20 -15 -10 -5

Class-AClass-AB

(b)

Fig. 3.14 TX performance versus input power: a output power and conversion gain, and b PApower consumption and PAE

P1dB

(dB

m)

4

6

8

10

12

14

Gp (dB)

10

15

20

25

30

35

Bias Settings0 5 10 15 20 25

P1dBGp

(a)

PAEm

ax (

%)

5

10

1520

25

30

35

PAE@5dB (%

)

3

4

56

7

8

9

Bias Settings0 5 10 15 20 25

PAEmaxPAE@5dB

(b)

Fig. 3.15 TX performance versus PA bias settings when both stages use the same values: a outputpower and conversion gain, and b maximum and 5 dB back-off PAE

As shown in Fig. 3.15, a lower gate bias range can allow the PA to operate deeperin class-AB with higher compression and back-off efficiency (at the expense of lessgain). The PA shows a gain range of 16 dB when the gate bias of both stages have thesame value. The figure also shows the trade-off between power, gain and efficiencywith different PA bias settings.

Figure 3.16 shows the TX frequency behavior. The TX shows compression valuesbetween 8.5 and 10.8 dBm over the output frequency range when the PA operates inclass-A. The output bandwidth is more than 6.2 GHz limited by frequency generation(simulated front-end bandwidth is >11 GHz), and the baseband input frequency is780 MHz limited by the analog baseband.

The chips are flipped and mounted on the front side of Nelco N4000-13 PCB’swith antenna feeds to a 4 × 2 array of patch antennas on the back side for wirelesscharacterization, as shown in Fig. 3.17.

Figure 3.18 shows the TX output characterized with a horn receiving antenna.When the 4 TX antenna paths are switched on, the output power is increased by 11.4dB (See Fig. 3.18a). An ideal value of 12 dB is expected due to spatial constructiveinterference, which is close to the achieved value. The output PSD is shown inFig. 3.18b when a full 802.11ad 16-QAM signal is transmitted through the TX and


P1dB

(dB

m)

6

8

10

12

14

16

18

Gp (dB)

20

25

30

35

Frequency (GHz)52 54 56 58 60 62 64

PoutGp

(a)

Gp

(dB)

10

20

30

40

Frequency (GHz)0 0.2 0.4 0.6 0.8 1 1.2

(b)

Fig. 3.16 TX performance versus frequency: a compression and gain versus output frequency, andb gain versus baseband input frequency

Chip

FRONT-SIDE

antenna feeds

(a)

Antennas

BACK-SIDE

(b)

Fig. 3.17 PCBmodule for wireless characterization: a flipped chip with antenna feeds on the frontside, and b back side with 4 × 2 patch antenna array

all the 4 TX antenna paths are switched on. The output is compliant with the maskspecified by the standard, while the PA operates in class-AB.

Figure 3.19a shows the TX-RX link setup, where both chips aremounted on PCBswith integrated patch antennas. The output QPSK and 16-QAM constellations areshown in Figure 3.19b for a full-rate 802.11ad signal, where EVM values between−13.1 dB and −15.2 are measured over the supported first three communicationchannels.

Figure 3.20 also shows the link performance versus the distance between the TXand RX modules. The 4-antenna path TX is able to achieve 4 m range with QPSKsignal, and 2m rangewith 16-QAMsignal. At packet size of 32768 symbols, a QPSKlink is demonstrated at a distance of 3.6 m with a BER of <10−3 without channel


Pout

(dB

m)

-20

-15

-10

-5

0

Number of Antennas1 2 3 4

PoutReferred to max

(a)

Pout

(dB

m)

-80

-70

-60

-50

-40

-30

-20

Frequency (GHz)55 56 57 58 59 60 61 62

802.11ad

RBW=3MHzVBW=300kHz

(b)

Fig. 3.18 TX performance with integrated patch antennas and measured with a horn antenna: aoutput power versus the number of activated TX antenna paths, and b 16-QAM PSD when all 4antenna paths are on and the PA operates in class-AB

(a)Constellations @ CH1 for QPSK

and 16QAM (32768 symbols)(b)

Fig. 3.19 a Block diagram of the demonstration setup, and b output constellations

with

LD

PC c

odin

g

withou

t LDPC co

ding

QPSK(a)

with LDPC coding

without LDPC coding16QAM(b)

Fig. 3.20 Wireless link bit-error rate versus distance with a packet size of 32768 symbols: a usingQPSK signal, and b using 16-QAM signal


Table 3.2 Comparison with state-of-the-art implementationsThis work Valdes-Garcia

et al. [VG10]Okada[Okada11]

Siligaris et al.[Siligaris11]

Tabesh et al.[Tabesh11]

Emami et al.[Emami11]

Class-A Class-AB

Technology 40nm-LP 0.12µm SiGe 65 nm 65 nm 65 nm 65 nm

Supply (V) 1.1 2.7 1.2 1.2 1.2 1

No. antenna paths 4 16 1 1 4 32

No. channels 3 4 4 4 4 2

Gain/path (dB) 31 22.5 35 18.3 18 NA NA

P1dB/path (dBm) 10.8 8 9 9.5 8 –1.5 (Psat) 6.4

PAEmax (%) 32.8 22.5 9 8.8 8 20 22

PAE5dB (%) 4.9 7.4 2.5 NA NA NA NA

PDC /path (mW) 181 146 237 186 277 34.2 56 (32 ant.),112 (8 ant.)

P1dB/PDC (%) 6.6 4.3 3.3 4 2.3 2.58 7.7 (32 ant.),3.9 (8 ant.)

RF BW (GHz) >6.2 NA NA 21 (stand-alone PA)

8 NA

BB BW (MHz) 780 1000 NA 830 NA NA

ESD Yes NA NA Yes Yes Yes

Area/path (mm2) 1.5 2.7 3.5 9.2/2 2.2/2 2.2

coding (i.e., at a 3.5 Gb/s datarate). For 16-QAM signals, low-density parity-check(LDPC) coding is required to get a similarBERat a distance of 0.7m.Coded dataratesare 2.31 and 4.62Gb/s, while raw datarates are 3.5 and 7Gb/s for QPSk and 16-QAMsignals, respectively.

A comparison of this TXchipwith other state-of-the-art implementations is shownin Table 3.2. The TX shows high TX efficiency and small footprint, while achievingat >8 dBm output compression point.

3.2.3 Conclusion

A two-stage transformer-coupled neutralized push-pull PA operating in both class-Aand AB is used in a 4-antenna path Tx/RX chipset. Reducing the number of stagesto the minimum allowed by the linearity requirement taking the load of precedingstages into account helps to get better efficiency and bandwidth. With two optimizedstages in the PA that are transformer-coupled to the upconversion mixer, an outputP1dB of 10.8 dBm is achieved in class-A with 31 dB gain, 32.8%maximum PA PAEin saturation, 4.9% PA PAE at 5 dB back-off and a simulated front-end 3 dB RFbandwidth of 11.5 GHz. The PA PAE back-off efficiency goes to 7.4% with 11 GHzRF bandwidth in class-AB, while P1dB, gain and maximum PA PAE are 8 dBm,22.5 dB and 22.5%, respectively.


3.3 A 28 nm-HPM TX Front-End with 11.5% PA Back-OffEfficiency

In this section, the TX front-end is migrated to 28 nm CMOS technology. Digitalcircuit benefit form technology scaling, and highly integrated radio solutions requirealso the analog and RF blocks to scale as long as the performance is acceptable. Inthis technology, the nominal supply voltage is 0.9 V compared to 1.1 V in 40 nm-LPtechnology, which will have a small impact on the output power capability of thetransistor. Figure 3.21 shows a comparison of the transit frequency (fT ) and Gmsgof a common-source transistor between both technologies using the its RF model.An in-house RF model is used for the 28 nm transistor for which a 4 GHz preshift istaken into account. The 380 GHz fT of 28 nm will be much reduced after taking thetransistor layout into account. The 28 nm transistor maximum stable gain (Gmsg) is12.2 dB in class-A and is 1 dB higher than the transistor of 40 nm-LP.

The neutralized amplifier of Fig. 2.6 is also compared in both technologies. Asshown in Fig. 3.22, the maximum Gmsg and Gmax for 28 nm are 20.9 dB and 15.1dB, respectively. These are 2.3 dB and 1 dB lower than in 40 nm-LP, respectively.

fT (

GH

z)

0

100

200

300

400

Idc/W (mA/um)0 0.2 0.4 0.6 0.8 1

40nmLP28nmHPM

(a)

Gm

sg (

dB)

0

5

10

15 Idc/W (m

A/um)

0

0.2

0.4

0.6

0.8

1

Vbias (V)0 0.2 0.4 0.6 0.8 1 1.2

40nmLP28nmHPM

(b)

Fig. 3.21 Technology comparison for a minimal-length common-source transistor with 30µmwidth of: a fT versus current density, and b Gmsg and current density versus gate bias

Gm

sg, G

max

(dB

)

-15-10-505

10152025

Vbias (V)0 0.2 0.4 0.6 0.8 1 1.2

40nmLP28nmHPM

Gmsg

Gmax

Fig. 3.22 Technology comparisonofGmsgandGmax for aminimal length 30µmwidthneutralizedamplifier

3.3 A 28 nm-HPM TX Front-End with 11.5% PA Back-Off Efficiency 49

A better comparison of the last PA stage between both technologies can beobtained if an optimal load impedance is used at its output. Figure 3.23 shows theresulting performance for minimal length transistors when the same aspect ratiois used in both technologies. Transistor widths of 144 µm and 108 µm with loadimpedances of 0.525∠120 and 0.48∠135 are used for 40 nm-LP and 28 nm-HPM,respectively.

A better conclusion can be drawnwhen the overdrive voltage is used for the x-axis.Therefore, the dip of P1dB in Figure 3.23 is used as a reference point for the biasvoltage. Figure 3.24 shows about 0.5 dB higher Psat and Gp in 40 nm-LP comparedto 28 nm-HPM. At overdrive voltages between 0.1 and 0.2 V, both technologies showcomparable compression and drain efficiency. The 40 nm-LP amplifier only has 3mW higher consumption than 28 nm-HPM at 0.2 V overdrive voltage, which givesmore confidence in the comparison approach.

Note that as discussed in Sect. 2.1.5, the high compression point values at very lowbias voltages are useless due to the large expansion. The gain expansion representsa nonlinearity similar to the gain compression that affects both EVM and the outputPSD. Therefore, the PA operation in deep class-AB is limited to <1 dB expansionin its gain curve.

dBm

10

12

14

16

18

Vbias (V)0.3 0.4 0.5 0.6 0.7 0.8 0.9

40nmLP28nmHPM

Psat

P1dB

(a)

Gp

(dB)

0

5

10

15

20

DE (%

)

45

50

55

60

65

Vbias (V)0.3 0.4 0.5 0.6 0.7 0.8 0.9

40nmLP28nmHPM

(b)

Fig. 3.23 Technology comparison for a minimal-length neutralized amplifier with an optimumload and the same aspect ratio: a Psat and P1dB, and b Gp and DE

dBm

10

12

14

16

18

Relative Vbias (V)-0.1 0 0.1 0.2 0.3 0.4

40nmLP28nmHPM

Psat

P1dB

(a)

Gp

(dB)

10

11

12

13

14

15

16

DE (%

)

45

50

55

60

65

Relative Vbias (V)-0.1 0 0.1 0.2 0.3 0.4

40nmLP28nmHPM

(b)

Fig. 3.24 The technology comparison of Fig. 3.23 with a Vbias relative to the P1dB dip: a Psatand P1dB, and b Gp and DE


Fig. 3.25 Gilberupconversion mixerschematic withcurrent-source biasing

LO+ LO+

LO-BB+ BB-

MSW

M trans

VCS M CS


ATXfront-end is implemented in 28 nm-HPMtechnology as part of a single antenna-path transceiver testchip that also includes an on-chip PLL with an I-Q 60 GHzVCO and LO distribution that also feeds an RX front-end. The PA is similar tothat of Sect. 3.2 (see Fig. 3.9), which includes two transformer-coupled stages withneutralized amplifiers in each. Transistor sizes of 30µ m and 120µ with minimallength are used in the first and second PA stages, respectively. Figure 3.25 showsthe used Gilbert upconversion mixer, where the transconductors are biased with acurrent source to reduce sensitivity to the gate bias voltage.

3.3.2 Common-Mode Oscillations

A high-ohmic resistor (Rb) is usually used at the center tap of the secondary wind-ing of each transformer preceding an amplification stage to prevent common-modeoscillations. A value of 18 k� is used in our implementations. Some applicationsrequire maximizing the TX switching speed, which implies controlling or reducingthe biasing resistor. The testbench of Fig. 3.26 is used to specify the required biasresistor, where a short circuit is used instead of the input transformer for simplicity.

Figure 3.27 shows Kf stability factor and |�| intermediate parameter at differentbias resistor values. The circuit is potentially unstable at 60 GHz without addingany resistance. The unconditional stability region gets wider with higher resistance.Figure 3.28 also shows additional stability factor parameters (μ and B1f) to confirmthe conclusions drawn using Kf.

A step on the gate bias voltage is used to check stability in time domain, where theamplifier’s input single-ended voltage is observed. As shown in Fig. 3.29, a 100 pHinductance is used to provide a resonance frequency close to 60 GHz. Figure 3.30


Vdc=Vbias/2

VDD

Real FixedBalun

50Ω50Ω Rb

Pad

50Ω CbLb

Fig. 3.26 Testbench used to specify the minimum biasing resistor required to prevent common-mode oscillations

Kf

0

1

2

3

4

5

Frequency (GHz)0 20 40 60 80 100

Rb=0

Rb=10

Rb=20Rb=30

Rb=100

Rb=1k

(a)Δ

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Frequency (GHz)0 20 40 60 80 100

Rb=0Rb=10Rb=20Rb=30Rb=100Rb=1k

(b)

Fig. 3.27 Simulation of the Kf stability factor using the testbench of Fig. 3.26 with different biasresistors: a Kf and b |�| parameters

μ

-0.5

0

0.5

1

1.5

Frequency (GHz)0 20 40 60 80 100


(a)

B1f

0

0.5

1

1.5

2

Frequency (GHz)0 20 40 60 80 100


(b)

Fig. 3.28 Simulation of additional stability factors using the testbench of Fig. 3.26 with differentbias resistors: a μ and b B1f

shows the resulting simulations, where the circuits shows an oscillatory behaviorwith an Rb of 0� then starts to damp at higher Rb values. At an Rb value of 100�,the circuit is damped and still provides fast switching.


VDDReal Fixed

Balun50Ω

Rb

100p

Pad

0-Vbias

Fig. 3.29 Testbench used to verify the effectiveness of biasing resistor in preventing common-modeoscillations with transient simulation

Vin

(V)

-2

-1

0

1

2

3

Time (ns)0 0.2 0.4 0.6 0.8 1

Rb=0 Rb=100(a)

Vin

(V)

0

0.2

0.4

0.6

0.8

Time (ns)0 0.1 0.2 0.3 0.4

Rb=10

Rb=100

Rb=1k

(b)

Fig. 3.30 Step response of the testbench of Fig. 3.29 at the single-ended PA input node withdifferent biasing resistor values


A chip photo is shown in Fig. 3.31, where a big part is used for test structures.The chip is designed for flip-chip configuration, but is also bonded for probed RFmeasurements. Compared to the 40 nm layout, the 28 nm technology only supportstransistor gates to be placed in one direction all over the chip.

The single-tone measured TX performance is shown in Fig. 3.32 at 62 GHz. Theinput power is swept and the results from two PA modes (i.e., class-A and AB) areappended for comparison. The TX in class-A provides a Psat of 13 dBm and P1dB of8.5 dBwith a conversion gain of 27.2 dB. ThemaximumPAdrain efficiency is 30.5%,while it goes to 3.2% at 5 dB back-off. In deep class-AB (with <1 dB expansion),the values go to 11.3 dBm Psat, 10.2 dBm P1dB and 20.2 dB conversion gain. Themaximum and back-off PA drain efficiencies are 29.8% and 11.5%, respectively. Theoutput 3 dB bandwidth exceeded the measurement range of 7.5 GHz, where >20GHz is simulated for the PA separately and 13 GHz is simulated for the whole TXfront-end. The average power consumption is 70 mW for class-A PA, 20–48 mW forthe PA in class-AB, and 25 mW for the upconversion mixer.


RX

PLLNOC

LODistr.

TX

1.15mm

3.19mm

SPI

Fig. 3.31 The 28 nm-HPM transceiver chip photo

Pout

(dB

m)

-20

-10

0

10

20G

p (dB)

10

15

20

25

30

V2in,TX,rms/50 (dBm)

-40 -35 -30 -25 -20 -15 -10 -5 0

Class-AClass-AB

(a)

DE

(%)

0

10

20

30

40

Pout (dBm)-20 -15 -10 -5 0 5 10 15

Class-AClass-AB

(b)

Fig. 3.32 Performance of class-A andABwith Pin sweep at 62GHz: a output power and conversiongain, and b PA drain efficiency

Fig. 3.33 Measuredfundamental response andthird-order intermodulationdistortion for class-A andAB biasing

Pout

(dB

m)

-60

-40

-20

0

20

V2in,TX,rms /50 (dBm)

-60 -50 -40 -30 -20 -10

Class-AClass-AB

A two-tone measurement is also performed to evaluate the third-order intermod-ulation distortion. Figure 3.33 shows the results of both class-A and deep class-AB.The TX shows an IM3 value of −35.7 dB at 5 dB back-off in class-A. The dipin class-AB is usually not effective as it is partially compensated by the 5th orderintermodulation distortion component. Therefore, the TX shows an intermodulationdistortion better than −27.2 dB in class-AB.


Table 3.3 Comparison of TX front-end with previous implementations

This work Section 3.2 Section 3.1

Class-A Class-AB Class-A Class-AB Class-AB

Technology 28 nm-HPM 40 nm-LP 40 nm-LP

Supply (V) 0.9 1.1 1.1

Psat (dBm) 13 11.3 14 10.3 11

P1dB (dBm) 8.5 10.2 10.8 8 10.2

Gain (dB) 27.2 20.2 31 22.5 22

PAEmax (%) 29.3 28.2 32.8 22.5 10.8

PAE5dB (%) 3.2 11.4 4.9 7.4 5.7

3.3.4 Conclusion

A TX front-end in 28 nm-HPM technology is explored in this section, where it isshown to have a comparable performance to the 40nm-LP implementation. Table 3.3summarizes the TX performance and compares with our previous implementations.The TX delivers a P1dB of 8.5 dB and Gp of 27.2 dB in class-A. The PA maximumand 5 dB back-off PAE are 29.3% and 3.2%, respectively, while operating from a 0.9V supply. In deep class-AB, the TX shows an intermodulation distortion better than−27.2 dB, while delivering P1dB and Gp of 10.2 dBm and 20.2 dB, respectively.The PA maximum and back-off PAE are 28.2% and 11.4%, respectively.

Chapter 4Digitally-Modulated Polar Transmittersin 40 nm CMOS

In this chapter, the polar transmitter architecture is explored at mm-waves as oneproposed disruptive architecture to achieve high PA efficiency at power back-off[Khalaf16]. Two chips will be presented in the following sections to validate thepolar behavior at mm-waves and show the design trade-offs.

4.1 Introduction

The high linearity of class-APAsmakes it a good candidate formm-wave transmitters[OKM+13, Saito13, Mitomo12, Siligaris11]. In deep class-AB, as shown in Chap. 3,some linearity is traded for higher back-off efficiency, reaching around 8% PA drainefficiency, providing about 2× efficiency advantage compared to class-A. As peakefficiencies of 30% are achievable (Chap. 3), there is still room for improvement,and the main challenge would be to keep an acceptable linearity for the TX system.

A disruptive TX architecture is required to achieve a dramatic reduction in the PApower consumption. The saturated PA drain efficiency of 30% is not easy to improvedue to the limited availability of signal shaping (e.g., to get a square wave output)at mm-waves. However, only a small portion of this efficiency is used at back-off,which is required for the variable envelope signals of high-order modulations (e.g.,QPSK and 16-QAM) for multi-Gb/s datarate communication. Therefore, our targetin this chapter is to utilize the maximum efficiency available in saturation, which ispossible through digital TX architectures.

Compared to a digital cartesian implementation, the digital polar architecture (seeFig. 4.1) does not require two PA’s (i.e., for I and Q modulation), leading to a morecompact design that is more favorable at mm-waves. The phase signal sin(ω0t +φ(t)) enters the PA, while the amplitude A(t) is extracted and applied to the PAthrough a separate modulation path. The digital polar architecture is proposed atmm-waves in this chapter and will be discussed in more detail.


55


https://doi.org/10.1007/978-3-030-16653-3_4

56 4 Digitally-Modulated Polar Transmitters in 40 nm CMOS

I

Q

PAP1dB

Back-off

(a)

I

QPsat

Back-off

I-Qto

A-Φ

AI

Q

sin(φ)

cos(φ) PsatBack-off

(b) (c)

Fig. 4.1 a Conventional linear-PA-based I-Q TX, b digital cartesian and c digital polar TX archi-tectures based on RF-DAC’s

As can be observed in Fig. 4.1, the digital polar architecture requires an extra I-Qto polar conversion block, which can be implemented in the digital domain. A digitalarchitecture also requires a higher data oversampling ratio compared to its analogcounterpart to reduce the output spectral images in the absence of output bandpassfilters. Thus, in order to evaluate the efficiency advantage of the digital polar archi-tecture over a linear PA before starting the implementation and to determine the extradigital signal processing (i.e. extra upconversion and I-Q to polar conversion) powerbudget, a first-order calculation is made based on the 4-antenna path implementationof Chap. 3 [Li15].

Table 4.1 shows a summary of the power and efficiency results of the chip inSect. 3.2. It also assumes imaginary modifications where the same chip is used ina digital polar configuration. Here the amplitude and phase data are extracted inthe digital domain, the PA is replaced with an RF-DAC and the rest (including theanalog baseband processing and upconversion mixers) is the same. When the linearPA operates at 5dB back-off from the 1-dB compression point of 10.8 dBm, the PAefficiency is 4.9%compared to themaximumvalue of 32.2% in saturation, and the PApower consumption is 78 mW. In the polar configuration, the RF-DAC has the sametotal size as the linear PA. The RF-DAC input includes only phase information, andtherefore it is allowed to operate in saturation. With a signal requiring 5 dB back-off,the amplitude modulates the RF-DAC such that the average output power is 5 dB lessthan the peak saturated power level of 14 dBm. This causes the average RF-DACsize to be 10−5/20 times (i.e. 0.56×) the full size, and the power consumption toreduce with the same factor. The PA operating efficiency is then 18.2% (where Poutis 9 dBm and Pdc is 0.56× 78 mW) in the polar configuration compared to 4.9% inthe linear one. The total TX output power in the polar configuration is 3 dB higher

4.1 Introduction 57

Table 4.1 Efficiency comparison of a linear PA and polar architectures, all operating at 5 dBback-off from the P1dB (linear PA) or from saturation (polar)Scenario Psat

(dBm)Pout perFE (dBm)

PA Pdc(mW)

PA PAE@Pout (%)

Totala Pout(dBm)

FE Pdc(mW)

Total Pdc(mW)

Totalefficiency (%)

Linear PA 14 5.8 78 4.9 17.2b 110 724 7.25

Polar @samePA size

14 9 43.7c 18.2 20.4 73.7 578.8 18.94

Polar @samePout,avg

10.8 5.8 20.9d 18.2 17.2 50.9 487.6 10.76

aIn the 4-antenna path system of Sect. 3.2bA measured value of 11.4 dB gain is considered instead of a theoretical value of 12 dB for the4-antenna pathscThe 5 dB back-off corresponds to an RF-DAC size of 0.56× the full sizedAssuming the same PAE@Psat of 32.2

than in the linear mode, which is the difference between Psat and P1dB. For the full4-antenna path system, the total TX efficiency goes to 18.94% in the polar modecompared to 7.25% in the linear mode. A fair evaluation of the power consumptionadvantage of the polar mode in this chip should include the same analysis at the sameTX average output power. Assuming the same peak saturated efficiency, the total TXpower consumption in the polar configuration reduces to 487.6 mW compared to724 mW at the same output power. In order for the digital signal processing to havea minor influence on the total power budget, a power consumption of 50 mW (10%of the total TX power consumption) is targeted. The contribution of this 50 mWbecomes less important as the TX output power increases (e.g., in larger-size phasedarray systems).

For IEEE 802.11ad, the main concerns when implementing a polar TX are theextended modulated signal bandwidth (which is expected here to be larger than 1GHz) and the need to synchronize the amplitude and phase paths with picosecondtime resolution.Moreover, high sampling speeds (e.g.,>5GS/s) are required to over-come out-of-band spectral images if a digital front-end is used in the implementation.Despite these restrictions, the 60 GHz TX should still provide higher efficiency thana conventional implementation with linear PAs.

Two testchips are implemented to explore the polar TX operation at 60 GHz.The main architecture and its system-level considerations are described in Sect. 4.2.Sections 4.3 and 4.4 present the 2 chips with their circuit implementation details andmeasurement results. Section 4.4 also includes an extra analysis for the contributionof circuit non-idealities to the EVM and a comparison to state-of-the-art.

4.2 Architecture and System Trade-Offs

Different polar TX architectures are used in the low-GHz range to provide, at powerback-off, higher transmit efficiencies than linear implementations. In this section,the architecture used in this realization is presented as well as system simulationsrequired to define certain block specifications.


1.76GS/s

1.76GS/s

1.76GS/s x OSFAmplitudePath

PhasePath

sin(φ)

cos(φ)

I-Qto

polar+

PD

PAI-Q Mixer

VCODSP

N bitsA

PhN bitsxOSF

Pulseshaping

Prototype IC

τ

LPF

Delay

RF-DAC

I

Q

Fig. 4.2 Top-level digital polar transmitter block diagram

4.2.1 60 GHz Polar TX Architecture

Figure 4.2 shows a block diagram of the polar TX, where the I-Q input informationis first upsampled at a specified oversampling factor (OSF) and pulse-shaped. It isthen converted to a polar representation in the digital domain, where predistortion(PD) can also be applied. Phase signals in the form of sin(ϕ) and cos(ϕ) are appliedto the input of the I-Qmixer, which upconverts the signal before it enters the PA. Theamplitude signal directly modulates an RF-DAC, which operates in saturation byadjusting the voltage swing of the phase signal at the mixer input. An RF-DAC thatcan be ideally modeled by switched current sources with a fixed supply voltage isused in this implementation. Operating at 6 dB back-off, one-half of the array in theRF-DAC is in the off state. It delivers one-quarter of its maximum output power to afixed load, and dissipates one-half of its maximum power consumption. Assuminga maximum drain efficiency of 30% in saturation, the RF-DAC is ideally expectedto have 15% average drain efficiency at 6 dB back-off. When the polar conversion isdisabled, the RF-DAC maximum amplitude codeword is used. The phase path thenreverts to the I-Q signal, and the TX operates in a Cartesian configuration. Thus, thisTX can be configured in either a digital polar mode where the PA operates in thenonlinear regime, or in the analog Cartesian mode with a linear PA. One objectiveof this work is to compare performance of the two configurations.

Oversampling is required to overcome aliases generated by the RF-DAC in thefinal stage [vZP07]. Moreover, the bandwidth of the phase signals is broadened bythe (nonlinear) IQ-to-polar conversion process, and requires a sampling rate of atleast twice the phase signal bandwidth. Aliases are attenuated by the finite TX RFbandwidth, and are controlled by lowpass filtering in the phase path ahead of theupconversion mixers. A variable time delay is required in the amplitude path tocompensate for timing mismatch between the amplitude and phase paths.

4.2 Architecture and System Trade-Offs 59

I-Qto

polar

Quant.

ZOH

x2AM-AMpredist.

AM-AMdist.Delay

ZOH

x2AM-PMpredist.

AM-PMdist.Delay

Outfor EVM

Outfor PSD

/2

Quant.

Window

I

Q

A

Ph

Amplitude resl’n(e.g., 4 or 5 bits)

Phase resl’n(e.g., 8 bits)

View moresignal BW

Circuit effect

LPF

Time mismatchmodel

Multiplication

DSPincluding

oversampling(e.g., x6)

andpulse

shaping

Fig. 4.3 Simplified block diagram of the MatlabTM model used for the transmitter side

4.2.2 Signal Behavior and System-Level Trade-Offs

A full 802.11ad transmit-receive chain with polar TX configuration including non-idealities such as amplitude-phase delay mismatch, lowpass circuit response andRF-DAC nonlinearity is simulated inMatlabTM with behavioral models. A simplifiedblock diagram for the transmitter model is shown in Fig. 4.3. Quantization and zero-order hold (ZOH) blocks represent a DAC. The amplitude information is required asan input for the AM-PM distortion or predistortion blocks. A window is used at thechain output to represent an idealRXfilter that removes the signal aliases beforeEVMis calculated. The input I-Q signal is prefiltered by a square-root raised cosine filterwith a 0.25 roll-off factor (see Fig. 4.4a). The amplitude and phase signals extractedafter polar conversion are shown in Fig. 4.4b and Fig. 4.5a, respectively. They confirmthe extended signal bandwidth inherent to the polar scheme. The phase signal in thetime domain after upconversion (not drawn in Fig. 4.3) is also shown in Fig. 4.5b. Itis seen to be equivalent to phase modulation of the LO signal. The constant-envelopephase signal drives the RF-DAC, which allows the DAC to operate in saturationwith maximum efficiency. The input signal is reconstructed at the RF-DAC output


−5 0 5−100

−80

−60

−40

−20

0

Frequency (GHz)

IQ P

SD (d

B/H

z)

(a)

−5 0 5−100

−80

−60

−40

−20

0

Frequency (GHz)

Ampl

itude

PSD

(dB/

Hz)

(b)

Fig. 4.4 PSD of a input I-Q signal (before polar conversion) and b amplitude signal after polarconversion with infinite resolution

−5 0 5−100

−80

−60

−40

−20

0

Frequency (GHz)

Phas

e PS

D (d

B/H

z)

(a)

10.37 10.373 10.376−2

−1

0

1

2

Time (us)

Upc

onve

rted

Phas

e (V

)

(b)

Fig. 4.5 a PSD of phase path input signal sin(ϕ) + jcos(ϕ), and b its upconverted representationin time domain with infinite resolution

after upconversion by the LO signal. However, non-idealities such as bandwidthlimitations of the circuits in the amplitude and phase paths, delay mismatch betweenthe amplitude and phase paths, and the RF-DAC non-idealities, have the potential todistort the output signal.

Figure 4.6a shows the amplitude signal in the time domain after scaling andquantizing (to 4 bits in this example), which represents the actual signal appliedto the chip input amplitude lines. In this case, the input signal is first quantized,where it gets rounded to (2NA − 1) levels. For example, during this quantizationstep all the signal peaks lying within the (maximum—LSB/2) are rounded to themaximum level that is then mapped to the maximum code. The same also occursat the minimum code. If needed, the average code can be calculated by averagingthe transmitted sequence after mapping. A training sequence at the beginning ofeach frame is used for channel estimation and digital processing in the receiver.In Fig. 4.6b, the probability distributions of the transmitted QPSK and 16-QAMsignals are shown versus the input amplitude code. The 16-QAM signal shows ahigher peak-to-average ratio (i.e., an average code of ‘7’) than the QPSK signal thathas an average code of ‘9’.

4.2 Architecture and System Trade-Offs 61

Inpu

t Cod

e

Time (μs)2.52.01.51.0

15

10

0

5

0.50

(a)

5

10

15

20

25

30

0 5 10 15

QPSK16QAM

Input Code

Dist

ribut

ion

(%) avg.

(b)

Fig. 4.6 16-QAM: a digital amplitude signal going to the chip, and b its histogram compared toQPSK

Figure 4.7 shows the simulated effect of system non-idealities on the transmit-ted output signal EVM. In Fig. 4.7a, the circuits lowpass response (modeled with asecond-order Butterworth filter) in the phase path degrades the signal EVM, espe-cially when the bandwidth drops below 2 GHz, where energy in the phase signal isconcentrated (see Fig. 4.5a). When there is no bandwidth limitation, the signal EVMis constrained by the RF-DAC resolution (NA in Fig. 4.2), where the phase path inputresolution (NPh in Fig. 4.2) is 8 bits. In this case, the EVM follows the quantizationsignal-to-noise ratio, i.e., SN Rq = 6 N + 1.76 dB, where number of bits (N) is theeffective resolution. With an infinite phase resolution, N is one bit higher than theRF-DAC physical resolution (NA in Fig. 4.2), because an extra sign bit exists inthe phase signal. The RF-DAC resolution is a trade-off between the EVM and RFperformance (i.e., gain, output power and efficiency) that is constrained by layoutparasitics. A resolution (NA) of 4 bits is used in this design, setting the SNRq to31.76 dB. Figure 4.7b shows the effect of a time delay mismatch between the ampli-tude and phase paths, which arises from the difference in signal delay between thecircuit blocks in the two signal paths. The minimal time step (i.e., time resolution)required to synchronize the two paths depends on the target EVM. For example,approximately 10 ps resolution is required to synchronize the two paths and realizea target EVM of −30 dB.

The effect of oversampling on the first alias attenuation is shown in Fig. 4.8for a 3 GHz filter in the phase path. Filtering the amplitude path directly limitsthe RF-DAC sampling speed, while filtering the phase path presents a trade-offbetween alias attenuation and signal EVM. Figure 4.8b shows the simulated aliasattenuation at different sampling rates, where more than 30 dB attenuation can beachieved at a sampling rate of 10 GS/s (i.e., 6× oversampling). The alias can befurther attenuated by the TX output bandwidth. The oversampling factor is a trade-off between attenuation of the first alias on one side and the DSP/DAC complexityand power consumption on the other side, where parallel data paths in the DSP areoften necessary to achieve high rates.


-50

-40

-30

-20

-10

0

0 2 4 6

EVM

(dB)

Phase path bandwidth (GHz)

6-bits5-bits4-bits3-bits

(a)

-50

-40

-30

-20

-10

0

0 40 80 120

EVM

(dB)

Delay mismatch (ps)

6-bits

3-bits

(b)

Fig. 4.7 Simulated effect at 8 bits in the phase path (i.e., Nph) and different amplitude bits (i.e., NA)of: a phase path input bandwidth and b amplitude-phase paths delay mismatch at 5 GHz phase-pathbandwidth, together with the RF-DAC resolution, on EVM

Frequency (GHz)

Pout

(dBm

) Aliasattenuation

(a)

-40

-30

-20

-10

0

0 5 10 15 20

Alia

s att

enua

tion

(dB)

Sampling rate (GS/s)

802.11adspectral mask

(b)

Fig. 4.8 Simulated alias attenuation at the TX output with 3 GHz phase path bandwidth: a at 10GS/s, and b versus the sampling rate

Figure 4.9 shows the simulated amplitude and phase replicas with 3 GHz phasepath bandwidth at 10 GS/s to shows their relative contribution to the alias attenuationat the TX output (shown in Fig. 4.8a). The phase signal replica is due to the DAC inthe phase path. The amplitude signal of Fig. 4.9a is only used in the model and doesnot represent a physical signal, as the zero-order-hold behavior of the RF-DAC onlyappears at the TX output when the amplitude and phase signals are already combinedby multiplication in time domain.

In a practical implementation, the amplitude pathwill have somebandwidth effect,which will reduce the alias attenuation further at the expense of EVM. At a samplingrate of 10 GS/s, the maximum useful signal bandwidth is 5 GHz (i.e., Fs/2). Theamplitude signal is confined in a bandwidth of <2 GHz (see Fig. 4.4b). Therefore, abandwidth of 2 GHz in the RF-DAC amplitude path is sufficient to have a negligibleeffect on the signal quality (i.e., EVM). For a DSP operating at 1.76 Gb/s symbolrate, a rising time (trise) corresponding to 25% of the clock period is 142 ps. This isequivalent to a system bandwidth of 2.5 GHz (0.35/trise for rising from 10 to 90% ina first order system).

4.3 A 5-bit 5 GS/s RF-DAC-Based Polar TX with –29.3 dB QPSK EVM 63

Frequency (GHz)

Pout

(dBm

)

(b)

Frequency (GHz)

Pout

(dBm

)

(a)

Fig. 4.9 Simulated replicas with 3 GHz phase path bandwidth at 10 GS/s: a in the amplitude path,and b in the phase path

4.3 A 5-bit 5 GS/s RF-DAC-Based Polar TX with –29.3 dBQPSK EVM

Here we present a 60 GHz digital polar TX with a 5-bit RF-DAC running up to amaximum sampling speed of 5 GS/s [Khalaf14]. This chip does not aim to achieveall the target specifications, but it gives more insight in the operation of the RF-DACand polar architecture at mm-waves.


As shown inFig. 4.2, thePA,RF-DACandupconversionmixer are integrated togetheron the same chip as a proof of the concept. All digital functionality is synthesized off-chip using MatlabTM. A digital circuit is also used in the amplitude path to interfacewith the measurement equipment. The LO signal is provided externally, and a 60GHz distribution circuit is used to generate differential I-Q signal at the mixer LOswitches.

Digital PA

The PA schematic (see Fig. 4.10) consists of two transformer-coupled push-pullstages. Cross-coupled capacitive neutralization is used in the first driver stage toensure better stability and higher gain. Compared to the linear PAs presented inChap. 3, the second stage is now replaced with two RF-DACs in a push-pull config-uration. The same matching strategy of the linear PA is also used here. The outputtransformer and pad capacitance are designed to provide an optimum load for theRF-DAC at maximum code, trading off the output power, gain and efficiency. Theinput and interstage transformers are designed to provide a conjugate match to the I-Q mixer and PA first stage, respectively. The RF-DAC depends on switching the unitPA transistors, which may influence the RF bandwidth. Therefore, controlling thecenter frequency of each resonance in the chain independently should be consideredto cover the 802.11ad frequency band efficiently.


31 cells

PAD OUT

VSW<4:0>

31 cells

Outputbalun

RFDAC

Interstagetransformer

Inputtransformer 10fF

To mixerswitches

1st PA stage(pre-PA)

2nd PA stage

M1

M

V

Vbias1

Rb1

Vbias2

DD

VDD

PAµ )m2(

Cneut

40µm40nm

min. length

Vsw<4>

Cb

MnMp

Rb

(2.64μm) (2μm)

(5fF)

(2.8k )

MPACb

MnMp

Rb

Fig. 4.10 Transformer-coupled two-stage PA with 5-bit RF-DAC

5-bit RF-DAC

The 5-bit RF-DAC is comprised of 31 (i.e., 2N − 1) parallel identical unit cells, asshown in Fig. 4.11, distributed in a common-centroid layout to ensure monotonicityand improved output linearity. Separate RF-DACs are used for each side of the60 GHz differential signal to reduce their coupling as well as the RF-DAC layoutcomplexity. The amplitude word (VSW<4:0>) (see Fig. 4.10) is binary coded toreduce the number of high-speed lines on-chip, and the number of pads used to routethe amplitude signal off-chip for testing. The LSB is connected to one unit cell andthe MSB is connected to 16 cells (i.e., one-half of the total number). One dummyunit cell is also added for symmetry. The input and output connections to the unitcells are 32µm long and wired in the highest metals M9 and M10. The minimumline width (0.5µm) is used to reduce parasitic capacitance, while the parasitic seriesresistance improves stability and does not limit the RF performance. A single RF-DAC occupies an area of 32 × 56µm2. The output power can be controlled viaVbias1 and Vbias2 or by operating on the amplitude of the phase signal at the mixerinput (see Fig. 4.2) in a similar way to an analog TX implementation.

Gate-Switched Unit Cell

The RF-DAC unit cell is gate controlled, as shown in Fig. 4.12a. This way, the PAunit transistor (MPA) has more voltage headroom. All unitMPA outputs are connectedtogether, and the inputs are AC coupled by backend-metal capacitors (Cb). The polyresistor (Rb) is used to bias the gate of MPA. Inverter Mn − Mp buffers the control


Input TaperOutput Taper

(a)

122

33

4 33 4

4 444 4

40

555 55 5

5 5

555 55 5

5 5

(b)

Fig. 4.11 The 5-bit RF-DAC top a layout and b cell distribution

Vsw<N>

Cb M

Mn

Vbias2 Gnd

x32 cells

In

Out

Mp

Rb

PA(2μm)

(2.64μm) (2μm)

(5fF)

(2.8k )

min. gatelength

(a)

(b)

CBRB

MswNMswP

Fig. 4.12 a Schematic and b layout of the gate-switched RF-DAC unit cell

signal VSW <N> (N ranging from ‘0’ to ‘4’) with an output level set by Vbias2. Theminimal length 31 unit PA transistors form a 62µmtotal output transistor, designed togenerate an average output power (at 5 dBback-off from themaximumcode saturatedoutput power) comparable to that of the linear PA of Sect. 3.2 (i.e., 5.8 dBm at 5 dBP1dB back-off). The unit cell layout is shown in Fig. 4.12b and occupies 8 × 7µm2.The active components are laid out in 6 × 5µm2, and the remaining space is usedto route the input, output and biasing signals to the different cells.

Rb and Cb are part of a high-pass filter for the input 60 GHz signal, and they forma low-pass filter for the switching signal. Thus, their values are a trade-off betweenloading the RF signal path and the switching speed. Figure 4.13 shows the effectof Rb on the RF gain. The testbench includes only one extracted RF-DAC cell with5fF Cb and loaded with 50 � at the input and output. The gain (Gmax) drops for Rb

values below 3.6 k�. A value of 2.8k� is used for Rb such that Kf is just above 1to ensure stability and still low enough to allow 5Gbps switching speed.


Fig. 4.13 Simulated effectof Rb on the RF-DAC cellperformance at 60 GHz

Gai

n (d

B)

0

2

4

6

8

10

12 Stability Factor (Kf)

0.5

1

1.5

2

2.5

3

3.5

Rb (kΩ)0 1 2 3 4 5

GmsgGmaxKf

One drawback of this topology is that the inverter draws few milliamps at therising and falling edges of the switching signal, because both Mn and Mp are on atthe same time. This requires increasing the biasing current supplying the RF-DAC,which contributes to the total PA power consumption by around 10 mA.

Voltage Feedback Upconversion Mixer

Compared to the super source-follower transconductor used in Chap. 3, here wetry to improve the feedback loop around the source-follower by inserting an ampli-fier in order to improve the design orthogonality, and thus gain/Idc, together withincreasing linearity. As shown in Fig. 4.14, the differential RF input voltage is copiedat resistor (R) terminals, generating the transconductor differential output current.Thus, the effective transconductance is 1/R. The value of R is a trade-off betweenthe target mixer gain and the source-followers open loop gain, which sets the targetgain specification of the amplifier.

As shown in Fig. 4.15, the input amplifier is a conventional two-stage differentialto single-ended amplifier with PMOS input transistors and a common-source outputstage.

Digital Interface

As will be shown in the measurement setup of Fig. 4.21, an arbitrary wave generator(AWG) is used to send the amplitude codeword to the chip. The digital interfacecircuit of Fig. 4.16 is used to synchronize the amplitude data after passing via cables,PCB tracks and bond wires. The AWG can maximally provide 4 programmabledigital output channels with 10 Gb/s rate. Therefore, at least one channel needs tohold two multiplexed amplitude data lines in order to feed a 5-bit RF-DAC. Thismeans that the RF-DAC will be sampled at 5 GS/s instead of 10 GS/s after thedata is demultiplexed in the digital interface. This is acceptable in this testchip asit is meant to explore the operation rather than achieving the target specifications.Here we choose to multiplex 2 channels (A<4:3> and A<2:1> in Fig. 4.16) to freeone for the clock (CLK), which makes it easier to synchronize the clock with theamplitude data. Positive edge-triggered DFFs and inverters are used to demultiplexthe serialized data lines. Inverter buffers are binary sized according to the weightof the line to achieve similar rise/fall times at the RF-DAC input. Buffers in a line


To PA InputTransformers

LO+ LO+

LO-

BB+ BB-Vbias,bb

Rb

R

AMP AMP

Vbias,amp

M

M

BB

MbiasVbias,mix

SW

(10 )

(96µm)(80nm)

20k

(40µm)(40nm)

(128µm)(80nm)

+

-

+

-

Fig. 4.14 Voltage feedback upconversion mixer

Fig. 4.15 Voltage feedbackmixer input amplifier (AMPblock in Fig. 4.14)

VDD VDD

IN+ IN- OUT(63.8µm)

(32µm)

(80µm)(87 )

(64µm)

(L=160µm)

are also binary sized to optimize the power consumption, where only 1mA time-averaged current is used for the operation of the whole digital interface. Custom I/Opads and ESD protection to reduce the capacitive loading of the input lines are usedwith 50� transmission lines (TLs) in order to ensure the 10 Gb/s data transmissionto the first on-chip inverters.


Fig. 4.16 Digital interfacecircuit for the 5-bit RF-DAChigh-speed inputs

clock

8xVSW<3>

16x

VSW<4>

A21(10GBPS)

2xVSW<1>

4xVSW<2>

A0(5GBPS) 1x

VSW<0>

A43(10GBPS)

50

TLESD

VDD

LO Distribution

The required four phases of the LO signal are derived from an external 60 GHzsource generator. As shown in Fig. 4.17, an on-chip balun is used to have a dif-ferential signal, which then enters a differential lumped equivalent of a 90◦ Langehybrid coupler [Shi13]. Before going to the mixer switches, the LO signal is bufferedwith transformer-coupled push-pull differential amplifier with stabilizing feedbackresistors and Cgd neutralization capacitors. A 400µm long 50� transmission lineis inserted between the input bond pad and the balun so that the total circuit layoutfits the IO ring (see Fig. 4.18) and the probes do not touch any bond wire whilemeasuring.


A photomicrograph of the 2.38mm2 bondpad-limited TX prototype is shown inFig. 4.18, and a zoomed-in version is shown in Fig. 4.19. The chip is implemented in40 nm bulk CMOSwith 0.9 V supply. The whole RF-DAC occupies 32 × 120µm2.ThePAand the digital interface are connected to 2 separate supply domains apart fromthe rest of the circuit. The high-speed amplitude and clock pads are placed on one sideseparatedwith ground pads for less interference. The I-Qdifferential phase input padsare placed on the other side together with the staggered serial peripheral interface(SPI) pads. Staggering pads saves more space but is more difficult to bond. Custom150µm pitch GSG LO input and TX output pads are used with a surrounding pad-free zone to avoid probes touching bond wires of the adjacent pads. One additionalDC pad is used as an external backup for the RF-DAC biasing. The core circuitoccupies only 0.18 mm2 including the LO distribution. Figure 4.20 shows the PCBused to measure the chip with the digital SPI control, and all the probe and cableconnections.


Buffer

LO In

50

Outputtransformer


Cc

MBUFVbI

Cs RsInput balun

VbQ

To mixerswitches

I

Q

0°

180°

0°

180°

90°

270°

I-Q hybrid

VDD

VbMIX

VDD

Fig. 4.17 LO distribution chain

PA DigitalInterface

LOGenera�on

I-Q Mixer

1.525mm

1.565mm

SPI c

trl +

IO su

ppy

Mix

er B

B

PA supply

Mixer supply

Digital interfacesupply

5GHz clock

A_43 (10GS/s)

A_0 (5GS/s)

A_21 (10GS/s)

VB2_Force

Fig. 4.18 Chip micrograph of the 5-bit 5 GS/s testchip

The measurement setup is shown in Fig. 4.21. The baseband phase signal and theamplitude digital word are provided from an AWG controlled via MatlabTM. Only 4programmable digital channels are available with a maximum rate of 10 Gb/s each,which sets the RF-DAC maximum sampling speed to 5 GS/s after demultiplexing.Two channels multiplex 4 amplitude digital lines and run at 10 Gb/s, while the third


32µm

120µmRF-DAC

Mixer pre-PA

Hybrid LO Buffer

Fig. 4.19 Chip micrograph of the 5-bit 5 GS/s testchip

Fig. 4.20 The 5-bit 5 GS/s PCB with its input-output connections

(LSB) channel runs at 5 Gb/s and goes directly to the RF-DAC after being synchro-nizedwith the other 4 lines by a 10Gb/s (5GHz fundamental) clock signal. TheAWGanalog channels have less than 3.5 GHz bandwidth. This constrains the phase pathinput bandwidth but does not limit the full-rate TX EVM at an RF-DAC resolutionof 5 bits, as shown in Fig. 4.7a. In this chip test, an un-calibrated equipment band-width of 2.5 GHz (together with the limited TX input bandwidth) contributed to the


Digital

5-bits5GS/s

MATLAB

Diff

. hyb

rid

I-Q Mixer

0°

180°

90°

270°

Balun

SPI Interface + DC Supplies

60GHz

Ch2Analog[cos(φ)]

Ch1Analog[sin(φ)]

Spectrum AnalyzerOR

Reference RX + Scope

DigitalInterface

60GHzGenerator PA

AWG

1 2 3 4

CLK

10GBPS5GBPS

DC x415.625GHz

2.5GHzto Scope

Reference RX

1.85mmto WR15

BPFVariable att.

Fig. 4.21 Simplified measurement setup of the 5-bit 5 GS/s testchip

bandwidth reduction of the phase path. The delay difference between the amplitudeand phase paths is compensated in the AWG, where coarse compensation is realizedby delaying the transmitted amplitude samples in MatlabTM by 1.5 ns, and the finedelay steps are programmed into the instruments digital channels. They can providea delay of up to 300 ps with 1 ps resolution. Synchronization between the amplitudeand phase paths is detected by monitoring the signal EVM after downconversionvia a mm-wave receiver (RX) chain (Reference RX in Fig. 4.21). The phase signalscoming from the AWG analog channels are connected to the mixer baseband inputafter being matched with off-chip 50� resistors. In a chip re-measurement, externalbias tees were used to allow for independent setting of the mixer input transistor biasand override the on-chip biasing circuit to compensate for the TX DC offset thatdominates EVM at reduced TX input powers.

Linear-Mode Behavior

The TX is first characterized in its linear mode, i.e. when all the RF-DAC cellsare switched on. Figure 4.22a shows the measured TX performance with a single200MHz tone applied at the mixer baseband inputs. An under-estimation of the RF-DAC and output pad parasitics caused the measured saturated output power to be−3.9 dBm, which is around 14 dB less than the estimated value from simulation.Figure 4.22b compares the measured reflection coefficient (S22) with simulation,and shows around 20 GHz frequency shift due to the initial simulation error. Themeasured P1dB and gain values are −5.5 dBm and 22.5 dB, whereas the expectedvalues from simulation are 5.5 dBm and 34 dB, respectively. The simulated high


0

2

4

6

8

10

12

14

-25-20-15-10

-505

1015

-45 -25 -5

sim1sim2measeff

Vin,TX,rms/50 (dBm)

Pout

(dB)

%

2

(a)

-30

-25

-20

-15

-10

-5

0

10 20 30 40 50 60 70

sim1sim2meas

Frequency (GHz)

S22

(dB)

(b)

Fig. 4.22 a Measured (meas), reproduced (sim1) and expected (sim2) output powers and expectedefficiency (eff) versus Pin. b Measured, reproduced and expected values of S22

gain is due to the low differential resistance R in the voltage feedback applied atthe mixer baseband input stage (see Fig. 4.14). The first simulated output powercurve in Fig. 4.22a (i.e., ‘sim1’) tries to reproduce the measured data. The secondone (i.e., ‘sim2’) is after correcting the circuit in simulation. The efficiency curve isan estimation of the behavior if the chip was functioning correctly. The measuredvalues are corrected by the difference between the measured and simulated outputpower. The expected saturated output power and peak efficiency are 10 dBm and13%, respectively. Although the measured output power is less than expected, thechip still allows exploring the polar TX architecture at mm-waves, and still we cangain more insight about the polar TX signal quality and behavior as a function ofdatarate, power levels and delay mismatch between the amplitude and phase paths.

Figure 4.23 shows the TX output and input bandwidth. The measured large-signal(Pin= −15 dBm) and small-signal (Pin= −35 dBm) chip RF bandwidths are 9GHzand 7 GHz, respectively (see Fig. 4.23a). Figure 4.23b shows the baseband inputbandwidth at 58 GHz. The phase path has a bandwidth of around 850MHz, limitedby the AWG (un-calibrated 2.5 GHz) and the TX input BW (1.2 GHz de-embeddedtill the PCB). This caused the signal EVM to depend on the datarate, as will be shownin Sect. 4.4.2.

Static Characterization

In this test, a single 200MHz tone is applied at the mixer baseband inputs and theRF-DAC code is swept from ‘0’ to ‘31’. Figure 4.24a shows the monotonic RF-DAC behavior versus switching codes. Here we show the efficiency behavior afteradding 14 dB to the to the measured output power (measured max. efficiency isaround 1%). At an input power level of −21 dBm (i.e., onset of saturation), themaximum code efficiency drops from 13% (at saturation) to 11%, and the relativevalue can be controlled by the RF-DAC gate bias. Pin is selected as a compromisebetween efficiency (see Fig. 4.22a) and EVM (see Fig. 4.26). The PA drain efficiencyreduction at lower codes is due to the fixed pre-PA DC current and the mismatchcaused by the output impedance variations at different codes . The average RF-DAC


0

5

10

15

20

25

54 56 58 60 62 64 66

Pin = -35dBmPin = -15dBm

Frequency (GHz)

Gain

(dB)

(a)

0

5

10

15

20

25

0 1000 2000

SetupDe-embedded3dB line

Frequency (MHz)

Gain

(dB)

(b)

Fig. 4.23 TX bandwidth behavior at a RF and b baseband

0

5

10

15

20

25

0

0.05

0.1

0.15

0.2

0.25

0 8 16 24 32

VoutGaineff

RFDAC Code

Out

put V

olta

ge (V

)

dB, %

(a)

-35

-30

-25

-20

-15

-10

-5

0

0 8 16 24 32

Pin=-30dBm

Pin=-25dBm

RFDAC Code

EVM

(dB)

(b)

Fig. 4.24 Static RF-DAC characterization versus switching code using a single 200MHz tone andb a QPSK signal

efficiency depends on the signal modulation and is 4.6% (compared to 1.5% forclass-A back-off efficiency of the same prototype as shown in Fig. 4.22a) for code16 for a signal of 6 dB PAPR.

Figure 4.24b shows a static EVMmeasurement, where a QPSK signal is transmit-ted to the DC offset compensated TX working in linear-mode at different RF-DACcodes. At an input power of −25 dBm (i.e. close to compression), EVM starts todegrade at RF-DAC codes lower than ‘4’, dominated by the reduced SNR becauseof transmitting very small signal amplitudes. If the input power is reduced by 5 dB,EVM degradation begins at higher codes (between ‘8’ and ‘12’), which transmits anoutput power that corresponds to the same power level as code ‘4’ of−25 dBm inputpower. At−30 dBmPin, high-code EVMvalues are about 2 dB better as the RF-DACnow operates far from compression. This degradation in linear-mode EVM values atlow codes can cause EVM degradation for high-order modulations if it occurs closeto the signal average (effective) code.


-27

-25

-23

-21

-19

-17

-15

0 500 1000

16-QAM Linear16-QAM PolarQPSK LinearQPSK Polar

EVM

(dB)

Signal Bandwidth (MHz)

Pin=-26dBm

(a)

-29

-27

-25

-23

-21

-19

-17

-15

0 500 1000

no DCOComp

with DCOComp

EVM

(dB)

Signal Bandwidth (MHz)

QPSK Polar

(b)

Fig. 4.25 a Polar and linear mode EVM versus signal bandwidth, and b Re-measured QPSK EVMin polar mode with DC offset cancellation

Polar Performance

Due to the reduced TX input bandwidth, the signal EVM shows a dependencyon datarate. Figure 4.25 shows the TX performance versus input signal band-width (symbol-rate/2). Both the linear mode (with maximum RF-DAC code settingand variable envelope I-Q baseband chip input) and polar mode (with amplitude-modulated RF-DAC and phase signal at baseband) are compared in Fig. 4.25a withQPSK and 16-QAM signals without compensating DC offset. Full-rate (FR) 16-QAM and QPSK signals have EVM values of−16.2 dB and−19.2 dB, respectively,at 61 GHz TX output frequency required by the reference Rx. EVM improves to−22dB (16-QAM) and −25.5 dB (QPSK) when the signal bandwidth is reduced by afactor of 8. The EVM is improved by 2–4 dB at reduced rates when the DC offset iscompensated at the TX input (see Fig. 4.25b). This improvement is limited to only0.9 dB at full-rate, which is much affected by the reduced TX input bandwidth.

To evaluate the EVM vs. power level and to compare polar and linear modes,QPSK and 16-QAM signals at the full-rate divided-by-8 (FR/8) are used. Figure 4.26shows the linear and polar mode improvements after using DC offset compensation.The linearmode is improved by around 3.5 dB, whereas the polar mode improvementis 2.5 dB. It is also concluded that un-compensated DC offset causes the EVM atlow power levels to be degraded for both linear and polar modes.

Figure 4.27a plots the DC offset compensated QPSK linear and polar modestogether for comparison. The polar-mode EVM degradation at high power levelsoccurs at least 5 dB higher than linear mode, which confirms the possible operationof the polar TX in its nonlinear PA region close to saturation. The same sweep is alsoperformed on a 16-QAM signal without DC offset compensation (see Fig. 4.27b),which also shows a late EVM degradation and the possibility of a polar-mode TXto operate at the onset of saturation. The difference between the polar mode QPSKand 16-QAM EVM values is much affected by the relative position of code non-idealities (AM-AM and AM-PM distortions) to the signal average code and thesignal probability distribution, as will be elaborated further in Sect. 4.4. The polar-


-35

-30

-25

-20

-15

-10

-5

0

-35 -30 -25 -20 -15 -10

noDCOC

with DCOC

Vin,TX,rms/50 (dBm)

EVM

(dB)

QPSKLinear

2

(a)

-30

-25

-20

-15

-10

-5

0

-35 -30 -25 -20 -15 -10

noDCOC

with DCOC

Vin,TX,rms/50 (dBm)

EVM

(dB)

QPSKPolar

2

(b)

Fig. 4.26 Improvement of a linear-mode (i.e., at maximum RF-DAC code) and b polar-modeQPSK signals EVM versus Pin after DC offset compensation at FR/8. Vin,TX,rm is the rms TX inputvoltage at the chip (i.e., mixer) input port

-35

-30

-25

-20

-15

-10

-5

0

-35 -30 -25 -20 -15 -10

Linear

Polar

Vin,TX,rms/50 (dBm)

EVM

(dB)

QPSKwith DCOComp

2

(a)

-28

-23

-18

-13

-8

-35 -30 -25 -20 -15 -10

Linear

Polar

Vin,TX,rms/50 (dBm)

EVM

(dB)

16-QAM

2

(b)

Fig. 4.27 Polar and linear mode EVM versus Pin at FR/8 for a QPSKwith DC offset compensationand b 16-QAM without DC offset compensation

mode EVM degradation in deep saturation is partially due to the hard clipping of thephase signal, which still holds some phase information in its amplitude, and partiallydue to the increased phase distortion in deep saturation. Both effects can be referredto as the analog AM-AM and AM-PM distortions.

Delay mismatch between the amplitude and phase paths is compensated for byshifting the phase samples, giving 100 ps resolution at a 10 GS/s AWG samplingrate. This is sufficient to synchronize the amplitude and phase paths of a full-rate16-QAM signal (see Fig. 4.28a), but can be lower if more system bandwidth is usedand better EVM values are targeted. The EVM flattens out beyond a delay mismatchof 400 ps. The FR/8 signal is 8x slower, and thus less sensitive to the delay mismatch.In this test, fine tuning of the AWG is only required to delay the clock signal withrespect to the amplitude data such that the clock edge always falls in the middle ofthe data bit.


-23-21-19-17-15-13-11

-9-7-5

-4 -3 -2 -1 0 1 2 3 4

FR/8FR/1

Time (ns)

EVM

(dB)

(a)

-23-21-19-17-15-13-11

-9-7-5

0 1 2 3 4 5

FR/8FR/1

Resolu�on (bits)

EVM

(dB)

(b)

Fig. 4.28 16-QAM signal EVM at FR and FR/8 rates without DC offset compensation due to: adelay mismatch between the amplitude and phase paths, and b RF-DAC resolution. The EVM valueat fully synchronized amplitude and phase signals and at 5-bit resolution corresponds to the bestvalue in Fig. 4.27b

52 54 56 58 60 62 64−70

−60

−50

−40

−30

−20

fRF (GHz)

Pout

(dBm

)

802.11ad

Fig. 4.29 Full-rate QPSK output PSD

Figure 4.28b shows the effect of lower RF-DAC resolution on EVM. A resolutionof “0” corresponds to a ‘phase-only’ signal. At the full-rate, no EVM improvementis seen beyond 2-bit resolution. This is masked by the bandwidth limitation of thephase path. At FR/8, EVM is affected by other non-idealities including the DC offset,AM-AM and AM-PM distortions.

The output PSD of a full-rate QPSK signal at maximumRF-DAC code setting andcompression level is shown in Fig. 4.29. No aliases are seen in the output spectrum,which experiences more attenuation due to the low cut-off frequency in the TX phasepath.

In order to compare the linear and polar mode PSDs at high output power levels,a FR/8 QPSK at signal is used to eliminate bandwidth-limiting effects as shownin Fig. 4.30. Input power values of 6 and 8.5 dB higher than P1dB are used forcomparison. At P1dB+6 dB, there is no visible distortion in the polar-mode output,whereas saturation of the envelope causes signal distortion in the linear mode. At a2.5 dB higher Pin (see Fig. 4.30b), the RF-DAC shows more distortion in the linear


60.5 61 61.5−50

−40

−30

−20

−10

fRF (GHz)

Pout

(dBm

)

LinearPolar

P1dB+6dB

(a)

60.5 61 61.5−50

−40

−30

−20

−10

fRF (GHz)

Pout

(dBm

)

LinearPolar

P1dB+8.5dB

(b)

Fig. 4.30 PSD of the linear and polar modes at a onset of saturation and b higher power at FR/8rate

−1 0 1

−1

−0.5

0

0.5

1

QPSK Full−rate Polar(a)

−1 0 1

−1

0

1

16−QAM Full−rate Polar(b)

Fig. 4.31 Full-rate (i.e., 1.67 Gsymbols/s) constellations in polar mode of: a QPSK (with −19.2dB EVM) and b 16-QAM (with −16.2 dB EVM)

mode, and the polar mode begins to distort as well. This behavior also confirms thepossibility of a polar-mode TX to operate at higher power levels close to saturation.

Figure 4.31 shows the received full-rate QPSK and 16-QAM constellations inpolar mode at Pin = −26 dBm. The corresponding EVM values are −19.2 dB and−16.2 dB, respectively.

The reduced-rate DC offset compensated QPSK and 16-QAM constellations areshown in Fig. 4.32. The QPSK EVM is −27.5 dB and corresponds to the −25 dBminput power of Fig. 4.26b. The 16-QAM EVM is −24.2 dB, which is 2 dB betterthan the value of Fig. 4.27b because of DC offset compensation.

Figure 4.33 shows reduced rate signal constellations when DC offset is compen-sated and an amplitude predistortion is applied. The QPSK signal EVM is improvedto −29.3 dB. The 16-QAM EVM remains at −23 dB due to an extra clockwiserotation in the inner constellation points caused by larger AM-PM error after predis-tortion. A detailed description of amplitude predistortion, AM-PM behavior and therelationship with constellation points will be given in Sect. 4.4.


−1 0 1−1

−0.5

0

0.5

1

QPSK FR/8 Polar(a)

−1 0 1

−1

0

1

16−QAM FR/8 Polar(b)

Fig. 4.32 FR/8 (i.e., 208.33Msymbols/s) constellations in polarmodewithDCoffset compensationof: a QPSK (with −27.5 dB EVM) and b 16-QAM (with −24.2 dB EVM)

−1 0 1

−1

−0.5

0

0.5

1

QPSK FR/8 Polar w/PD(a)

−1 0 1

−1

0

1

16−QAM FR/8 Polar w/PD(b)

Fig. 4.33 FR/8 (i.e., 208.33Msymbols/s) constellations in polarmodewithDCoffset compensationand amplitude predistortion of: a QPSK (with−29.3 dBEVM) and b 16-QAM (with−23 dBEVM)

4.3.3 Conclusions

A digitally-modulated TX architecture is prototyped in 40 nm CMOS to evaluatethe polar transmission at 60 GHz. The measurements confirm the monotonic char-acteristic of the RF-DAC, and verify the expected polar TX behavior at mm-wavefrequencies. Synchronizing the amplitude and phase paths is possible by observingEVM after downconversion with a reference receiver. The RF-DAC is driven closeto saturation without EVM or spectral mask degradation. Reduced TX input band-width limits full-rate EVM values of QPSK and 16-QAM signals to −19.2 dB and−16.2 dB, respectively. The QPSK EVM is improved by 0.9 dB when LO leakage iscompensated in the TX.When the datarate is divided by 8 (i.e., 208.33Msymbols/s),QPSK and 16-QAM signals show EVM values of −27.5 dB and −24.2 dB, respec-tively. The QPSK EVM can be improved to −29.3 dB when amplitude predistortionis applied. This shows the implementation potential and possibility to achieve EVMvalues close to the linear mode.

This testchip is meant to explore the polar TX architecture operation at mm-waves without targeting optimal performance. The RF-DAC output power reductioncaused the efficiency to be less than 1%. The RF-DAC sampling speed in this test is


limited to 5 GS/s due to the measurement setup. Even if the speed limitation of themeasurement setup is solved, the biasing R-C in the RF-DAC unit cell can influencethemaximum speed. Sampling the RF-DAC at 5GS/s limits the useful TX phase pathbandwidth to 2.5 GHz and does not provide sufficient attenuation for the first aliasin the TX output spectrum. No aliases were observed in this test due to the limitedTX input bandwidth caused by the mixer input stage. This caused the datarate to bemuch reduced for optimal TX EVM values. These limitations are addressed in thenext polar TX implementation as will be discussed in Sect. 4.4.

4.4 A 4-bit 10 GS/s RF-DAC-Based Polar TX with 15.3%Average PA Efficiency

The 5-bit RF-DAC-based polar TX implemented in Sect. 4.3 shows that it is possi-ble to digitally modulate a polar TX architecture at 60 GHz, while operating at theonset of saturation, with the potential to gain much improvement in TX efficiency.It was possible to synchronize the amplitude and phase path and obtain good EVMvalues, but the chip did not meet TX input bandwidth or RF-DAC sampling speedrequirements and was not able to show the efficiency advantage of a polar TX imple-mentation over the recent linear-PA-based implementations. Thus, the main targetof this chip [Khalaf15a] is to overcome the limitations of the 5-bit version, as willbe discussed in the following sub-sections.


Few circuit modifications in this chip were done including the RF-DAC resolutionand unit cell design, the mixer input stage and the digital interface circuit.

Digital PA

As shown in Fig. 4.34, the 4-bit digital PA is similar to the 5-bit one of Fig. 4.10 with15 parallel RF-DAC cells instead of 31 and a different unit cell.

The PA layout including theRF-DAC is shown in Fig. 4.35. TheRF-DACoccupies32 × 64µm2, and the output transformer is optimized for maximum PA efficiencywhen all the RF-DAC switches are on.

4-bit RF-DAC

Constraining the PA size to 15 unit cells prevents layout parasitics from limiting theRF-DAC performance. With optimal impedance matching and transformer design,the maximum simulated PA drain efficiency can reach 30% with 15 cells (4 bits) in40 nm CMOS, while for a 31-cell (5-bit) RF-DAC it is limited to 20%. Furthermore,having 4 bits in the RF-DAC allows testing the chip with a signal generator of 4


15 cells

Out

VSW<3:0>

15 cells

VSW<3>

Outputbalun

RFDAC


Inputtransformer 10fF

To mixerswitches

1st PA stage(pre-PA)

2nd PA stage

M1

M

V

Vbias1

Rb1

Vbias2

Rb2

DD

VDD

PAµ )m4(

MSWµ )m81(

Cneut

40µm40nm

min. length

Fig. 4.34 Transformer-coupled two-stage PA with 4-bit RF-DAC

RF-DACpre-PA

Mixer

32μm

64μm

Fig. 4.35 Layout of the PA with 32 × 64µm2 RF-DAC

programmable digital channels at its maximum 10 GS/s sampling speed instead ofdata multiplexing at one-half of this speed (i.e., 5 GS/s) to reach 5-bit resolution asin Sect. 4.3.

In principle, 4 bit resolution in the RF-DAC are sufficient to achieve the SNRq

of 31.76 dB as required to transmit high-order modulated RF carriers. A resolutionof 4 bits still has an acceptable out-of-band emissions, where simulated 802.11adspectral mask violations started to appear at less than 3 bits. The potential for higherresolutions using further downscaled CMOSwould yield the extra margin (e.g., afterRF-DAC calibration) necessary for applications using 64-QAM signals.

AdifferentialRF-DACfloorplanwith input and output tapers is shown inFig. 4.36.Only 4 of the 8 rowsof Fig. 4.11 are used in this design, utilizing the common-centroiddistribution.

4.4 A 4-bit 10 GS/s RF-DAC-Based Polar TX with 15.3% Average PA Efficiency 81

Fig. 4.36 The differentialRF-DAC floorplan

To outputbalun

Frompre-PA

VSW<3:0>

1

0

2

2

44

44

4

4

4

4

33

3 3

VSW bit order(0 is dummy)

2

2

0

1

44

44

4

4

4

4

33

3 3

One of the PA layout challenges is to avoid electromigration in the presence ofhigh currents passing through itsmetal layers. Figure 4.36 shows one advantage of theunit-cell-based RF-DAC approach in the last stage of the PA, where the current goingto the lower metal layers is a small fraction of the total current. The 0.5µm widthM10 RF-DAC output lines allow 64.8 mA DC current in the whole (differential)RF-DAC.

Source-Switched Unit Cell

The RF-DAC unit cell includes a minimum gate-length (i.e., 40 nm) 4µm widetransistor for power amplification (MPA in Fig. 4.37a), forming a total width of 60µmas 15 unit cells are used. Transistor MPA is sized to have a total width comparable tothe 5-bit version (i.e., 2µm × 31 = 62µm). This generates an average output powercomparable to the TX of Chap. 3 (i.e., 5.8 dBm). A minimum-length 18µm wideMOSFET switch (MSW in Fig. 4.37a) is used at the source of the PA unit transistorin each RF-DAC cell to provide the amplitude signal. The selection of the switchwidth is a trade-off between its on-resistance and the area occupied by the RF-DAC.Both constraints affect the RF performance of the DAC either by degeneration of thePA, or through layout parasitic capacitances.

Compared to the gate-switched RF-DAC unit cell of Fig. 4.10 from Sect. 4.3, thesource-switched cell of this implementation provides at least 2x higher (i.e., >10GS/s) switching speed. The speed in the 5-bit version is limited by the pole formedby the biasing resistor (Rb) and the total capacitance at the main PA transistor gatein Fig. 4.10.

As shown in Fig. 4.37b, the 18µm switching transistor still allows using the sameunit cell area of 6 × 5µ m2 in the 5-bit version.


Vsw<N>

M

Gnd

In

OutPA(4μm)

min. gatelength

x15 cells

MSW(18μm)

(a)

IN

Switch

(b)

Fig. 4.37 Source switched RF-DAC unit cell a schematic and b layout

Gilbert Upconversion Mixer

TX input bandwidth of the 5-bit version is less than 1 GHz due to the upconversionmixer baseband amplifier (see Fig. 4.14) and the uncalibrated AWG reduced band-width of 2.5 GHz. This caused a rate-dependent EVM reaching its minimum (i.e.,best) value at 208.33 Msymbols/s. In this design, however, only common-sourcetransistors are used at the I-Q mixer input (see Fig. 4.38), relaxing the TX inputbandwidth and providing 8× higher full 802.11ad datarate without EVM degrada-tion.

Digital Interface

The 4 input digital amplitude lines (A<3:0> in Fig. 4.39) enter the chip at 10GSam-ples/s each, and no multiplexing is required. The digital lines are synchronized usinga 10 GHz clock (CLK) signal. This allows the RF-DAC to be sampled at 10 GS/s,which is 2× higher than the 5-bit version, and allows the first alias to be attenuatedmore than 30 dB to meet the 802.11ad spectral mask.

LO Distribution

The LO distribution is reused from the 5-bit version (see Fig. 4.17) without anymodification.

Full Circuit

Figure 4.40 shows a full schematic of the circuits implemented in this chip. Theleast amplitude significant bit is connected to a single RF-DAC unit cell and itscomplementary, while the MSB with 8× larger buffer size is connected to a total of16 unit cells. The I and Q phase paths are added at the mixers outputs, and the LOhybrid coupler is represented by its lumped component model.


To PA InputTransformers

LO+ LO+

LO-

BB+ BB-M

M (40µm)(40nm)SW

BB

Rb 20k

Vbias,bb(160µm)(80nm)

Fig. 4.38 Gilbert upconversion mixer

Fig. 4.39 Digital interfacecircuit for the 4-bit RF-DAChigh-speed inputs

A<1>

A<2>

A<3>

A<0>

clock

50

ESDDFF

TL

1x

2x

4x

8x

VSW<0>

VSW<1>

VSW<2>

VSW<3>

VDD


A<2> A<1> A<0>A<3> CLK

50ESD

DFF

TL

8x 4x 2x 1x

Ph(I) Ph(Q)

Tx Out

LO In

PARFDAC

HybridCoupler

LOGenera�on

DigitalInterface

I-Q Mixer4 μm

18 μm

40 μm

160μm

50

40k

40μm

18.2

μm

8x 2x

PPA

A = I +QPh(I)Ph(Q)

2 2

= sin(φ) = I/A = cos(φ) = Q/A

10fF

5fF

TL

80nm

Fig. 4.40 Full circuit diagram of the 4-bit 10 GS/s polar TX testchip


As shown in Fig. 4.41, the 4-bit chip uses the same I/O ring, power routing and LOdistribution as the 5-bit one (see Fig. 4.18). Both chips are fabricated in the same 40nm bulk CMOS technology with 0.9 V supply, and the difference lies in the designof the RF-DAC, upconversion mixer and the digital interface circuit. The PA, mixerand their biasing circuits occupy 0.085 mm2. The LO generation, including the inputbalun, differential hybrid and LO buffers are 0.055 mm2 in area. The digital interfacewith its output lines connecting to the PA occupies 0.026 mm2. Thus, the completecore circuit, including a few internal decoupling capacitors totals 0.18 mm2, whilethe entire chip area is 2.38 mm2.

The 4 programmable digital channels available in the AWG are used to generatethe amplitude data, while the clock signal is generated from a separate sinewavegenerator with phase control to allow synchronization with the amplitude data (seeFig. 4.42). The clock signal is converted to a square wave by on-chip inverters in thedigital interface. Each AWG channel has a maximum sampling speed of 10 GS/s,which sets the sampling rate of the RF-DAC in the transmitter used for testing.The AWG analog channels have less than 3.5 GHz bandwidth. This constrains the


PADigitalinterface

LOgenera�on

I-Q mixer

1.525mm

1.565mm

SPI c

trl +

IO su

pply

Mix

er B

B

PA supply

Mixer supply

Digital interfacesupply

10GHz clock

A<3:0>(10GS/s)

LO In

PA Out

Fig. 4.41 Chip micrograph of the 4-bit 10 GS/s testchip with 0.18 mm2 core and 2.38 mm2 totalarea

Digital1-4

10GS/s

4-bits10GS/s

10GHzGenerator

CLK

MATLAB

Diff

. hyb

rid

I-Q Mixer

0°

180°

90°

270°

Balun

DC

Biastees

SPI Interface + DC Supplies

60GHz

Ch2Analog[cos(φ)]

Ch1Analog[sin(φ)]

Spectrum AnalyzerOR

Reference RX + Scope

DigitalInterface

60GHzGenerator PA

AWG

x415.625GHz

2.5GHzto Scope

Reference RX

1.85mmto WR15

BPFVariable att.

Fig. 4.42 Simplified measurement setup of the 4-bit 10 GS/s testchip

phase path input bandwidth but does not limit the full-rate TX EVM at an RF-DACresolution of 4 bits, as shown in Fig. 4.7a. External bias tees are used at the mixerinput to compensate LO leakage.


Linear-Mode Behavior

Similar to the 5-bit version, measurements are first performed at the maximum RF-DAC code (i.e., when all RF-DAC cells are switched on) to evaluate the TX RFperformance. For a single 200MHz tone applied to the mixer input, Fig. 4.43 showsthe maximum output power of 10.8 dBm (in saturation) and small-signal conversiongain and maximum PA drain efficiency (ηD) of 24.3 dB and 29.8%, respectively.The Pout curve saturates above 10 dBm, which is the maximum useful power whentransmitting a modulated signal in polar mode, as shown in Sect. 4.3. At the onsetof saturation, the gain drops to 20.3 dB, and ηD becomes 27.2%. The output 1-dBcompression point (P1dB) is 7.4 dBm. The PA drain efficiency operating at 5 dBback-off from OP1dB is 5.6% if the RF-DAC at its maximum code is used as a 2ndPA stage operating in class-A.

As shown in Fig. 4.44a, drain efficiency remains above 20% between 51.5 and64 GHz, and the average Psat is 10.1 dBm with a variation of +/–0.7 dB from 53.5to 66 GHz. The center frequency can be readjusted by reducing transformer sizes.The baseband input bandwidth is 3.1 GHz (see Fig. 4.44b), and is dominated by theAWG analog channel bandwidth (3.5 GHz in its direct output mode).

0

5

10

15

20

25

30

-15

-10

-5

0

5

10

15

-40 -25 -10 5Pin (dBm)

P out

(dBm

) Gain (dB)

(a)

0

5

10

15

20

25

30

35

-40 -25 -10 5Pin (dBm)

PA E

ffici

ency

(%)

29.8% at Psat

5.6%in class-A

(b)

Fig. 4.43 TX performance versus Pin at maximum RF-DAC code: a Pout and conversion gain, andb PA drain efficiency

05

101520253035

50 55 60 65 70

PA Efficiency

Psat

LO Frequency (GHz)

dBm

, %

(a)

-35-30-25-20-15-10

-505

0 1 2 3 4 5

3dB line

Frequency (GHz)

P out

(dBm

)

(b)

Fig. 4.44 TX performance versus a LO and b baseband input frequencies at maximum RF-DACcode


Table 4.2 TX performance summary at maximum RF-DAC code

Technology 40 nm CMOS Supply (V) 0.9

Psat (dBm) 10.8 Pdc,PA@Psat (mW) 40.25

P1dB (dBm) 7.4 Pdc,mixer (mW) 18

TX small-signal gain (dB) 24.3 Pdc,total@Psat (mW) 58.25

TX large-signal gain (dB) 20.3 Psat/Pdc,PA@Psat (%) 29.8

1 dB large-signal RFBW (GHz) 9 (54.5–63.5) Psat/Pdc,total@Psat (%) 20.59

3 dB large-signal RFBW (GHz) >17 @ 59 Pout/Pdc,PA@P1dB−5 (%) 5.6

3 dB IFBW (GHz) >3.1 GHz Core area (mm2) <0.18

0

5

10

15

20

25

30

0

0.5

1

1.5

0 5 10 15

Static

Input Code

V out

(V)

PA Efficiency (%)

(a)

051015202530

-25

-20

-15

-10

-5

0

0 5 10 15Input Code

S22

(dB)

PA η (%)

Static

D

(b)

Fig. 4.45 RF-DAC static behavior: a AM-AM and AM-PM, and b S22 and PA drain efficiency

The measured linear-mode performance is summarized in Table 4.2. The I-Qmixer dissipates 18 mW that can be reduced to 9 mW for 0.5 dB reduction in theoutput power. The PA consumes 40.25 mW when operating in saturation, leadingto a total maximum power consumption of 58.25 mW (excluding 12 mW in the LObuffers). A large RF bandwidth (RFBW) of 17 GHz is achieved by applying an offsetin the center frequency of each RF stage.

Static Characterization

Figure 4.45a shows the static RF-DAC Vout (i.e., AM-AM) and AM-PM behavior atthe onset of saturation (i.e., Pin of−10 dBm). The TX output power is measured for a200MHz input tone at different RF-DAC switching codes, and then referred to 50�

to determine the peak output voltage. For the phasemeasurement, a network analyzeris used, where port ‘1’ is connected to the LO input via an external amplifier, andport ‘2’ is connected to the PA output. The DC offset at the mixer input is controlledto allow the LO signal to saturate the PA. The AM-PM curve is obtained from ameasurement of the phase of S21 versus the RF-DAC switching codes, referred tocode ‘0’. As seen from the Vout curve, the RF-DAC input signal leaks at code ‘0’(i.e., when all the RF-DAC switches are off) due to the finite off-resistance of theunit cell switches (MSW in Fig. 4.37a) and through the gate-drain capacitance ofmain transistor MPA. This effect limits the transmitted signal quality, as it causes theconstellation points with small amplitude values to get pushed away from the center(i.e., the point of zero-crossing) towards larger amplitudes. Signal leakage can be


improved in a future implementation with a cascode configuration and switching thepre-PA. If necessary, an input switch per cell can also be used at the expense of somedegradation in gain and efficiency. The large phase error versus codes only occurs atthe first two codes having low probability distribution (see Fig. 4.6b). The simulatedeffect of the measured AM-PM curve only without amplitude or phase predistortionon the signal EVM is −32 dB for QPSK and −29 dB for 16-QAM. This can beimproved in a future implementation if needed by adding a variable capacitor at theRF-DAC input or by simply ignoring the first two codes. Figure 4.45b shows the PAoutput impedance variations (i.e., S22) and drain efficiency versus RF-DAC codes.The PA output matching is optimized at its maximum RF-DAC code, achieving amaximum drain efficiency of 27.2%. Ideally, the efficiency at lower codes shouldfollow a linear curve going towards 0%. Signal leakage and the fixed pre-PA DCcurrent consumption cause the PA drain efficiency to have a non-zero value at code‘0’, while the integral nonlinearity is due to the RF-DAC impedance variation atdifferent codes.

Polar Performance

AQPSK signal is used to synchronize the digital polar TX and test its performance atdifferent power levels and RF-DAC effective resolutions. A time delay of 1.5 ns with50 ps resolution between the amplitude and phase paths (see Fig. 4.46a) is required forsynchronization, yielding a minimum EVM value of −20.7 dB. Figure 4.46b showsthe signal EVM and average drain efficiency versus the average output power whenthemixer input voltage (phase signal amplitude) is increased. The PA drain efficiencyreaches 22.3%before the EVM is degraded by hard clipping of the upconverted phasesignal and the phase distortion that predominates in deep saturation. The EVM floorat signal back-off is a reflection of all the system non-idealities, mainly dominatedby signal leakage, AM-AM and AM-PM in the RF-DAC.

Test with Lower RF-DAC resolution

In Fig. 4.47, a test is performed where we investigate the effect of shifting the inputamplitude codes to higher levels (i.e., intentionally reducing the RF-DAC resolutionand clipping the signal to degrade EVM). This shows the efficiency-linearity trade-off in the TX, gives more insight about the effect of different AM-AM (i.e., output

-25

-20

-15

-10

-5

0

0 0.2 0.4 0.6Relative Delay (ns)

EVM

(dB)

QPSK

50ps

(a)

0

5

10

15

20

25

-25

-20

-15

-10

-5

0

2 4 6 8 10Avg. Pout (dBm)

EVM

(dB)

Avg. PA η (%)

Increasing Vin(Tx phaseinput)

QPSK

D

(b)

Fig. 4.46 Polar TX dynamic behavior: a amplitude-phase synchronization, and b performanceversus Pin


0

5

10

15

0

0.5

1

1.5

0 5 10 15

Shifted Code

Input Code

Vout

(V)

12 effectiveRF-DAC levels

Static

ReferenceAM-AM

(a)

20

22

24

26

28

8

8.75

9.5

10.25

11

-21 -20 -19 -18 -17EVM (dB)

Avg.

Pou

t (dB

m) Avg. PA η (%

)

Reducing RFDACeffectiveresol’n.

16 levels

8 levels

QPSK

D

(b)

Fig. 4.47 RF-DAC a code shift behavior and b its performance at the remaining number of quan-tization levels

Table 4.3 Modulated polar TX performance summary with and without predistortion

Without predistortion With predistortion PD1

Modulation BPSK QPSK 16-QAM BPSK QPSK 16-QAM

Pav (dBm) 9.3 8.1 7.2 7.9 5.3 3.6

Pdc,total@Pav (mW) 51.5 46.9 44.5 46.46 40.15 37.75

Pav/Pdc,PA@Pav (%) 25.3 22.3 19.8 21.7 15.3 11.6

Pav/Pdc,total@Pav (%) 16.5 13.8 11.8 13.3 8.4 6.1

Raw datarate (Gb/s) 1.67 3.33 6.67 1.67 3.33 6.67

EVM (dB) –24.3 –20.7 –16.5 –24.1 –23.6 –18.1

voltage versus input code) curves on EVM, and provides extra measurement data tovalidate our MatlabTM model. Figure 4.47a shows the static curve when shifted up4 levels as an example, leading to 12 RF-DAC effective levels instead of 16. Whenthe RF-DAC effective number of levels are moved from 16 (i.e., 4 ENOB) to 8 (i.e.,3 ENOB), Fig. 4.47b shows that the EVM increases to −17.5 dB, while the averagepower and PA drain efficiency reach 9.8 dBm and 27%, respectively.

Table 4.3 lists a summary of the polar TX performance under BPSK, QPSKand 16-QAM modulations at 10 GS/s sampling speed for 6× oversampling, withand without predistortion (PD). When no predistortion is applied, the average RFoutput power and PA drain efficiency for QPSKmodulation are 8.1 dBm and 22.3%,respectively, at an EVM of −20.7 dB. The corresponding 16QAM values are 7.2dBm power output with 19.8% efficiency at −16.5 dB EVM, and BPSK delivers9.3 dBm to the load with 25.3% efficiency at −24.3 dB EVM. The transmitted datarates for BPSK, QPSK and 16-QAMmodulations are: 1.67 GS/s, 3.33 GS/s and 6.67GS/s, respectively.

Applying Predistortion

Better EVM values are achieved with predistortion (PD1 in Fig. 4.48a), where theinput amplitude codes are mapped to others that give the best straight-line fit (withminimum absolute error) passing through 0V and the maximum voltage. All codesfrom ‘0’ to ‘4’, representing the smaller amplitude values, are mapped to code ‘0’


0

5

10

15

0

0.5

1

1.5

0 5 10 15Input Code

Vout

(V) PD1 Code

Static

w/PD1

ReferenceAM-AM

(a)15

10

0

5PD1

Code

Time (μs)1.41.00.60.2

(b)

Fig. 4.48 RF-DAC: a PD1 predistortion behavior and b QPSK predistorted input codes with PD1

when predistorted. In the time domain, this is equivalent to clipping the amplitudesignal from the bottom, as shown in Fig. 4.48b. This effect is caused by the signalleakage at code ‘0’. Phase predistortion is limited by signal leakage. Table 4.3 alsoshows a summary of the QPSK and 16-QAM measured performance with PD1.The higher average output power and efficiency of uncalibrated RF-DAC come atthe expense of degraded signal quality. The QPSK signal output power is 5.3 dBmwith 15.3% drain efficiency at −23.6 dB EVM, while 16-QAM yields 3.6 dBm ofpower with 11.6% efficiency at −18.1 dB EVM. At the same average output power,the calibrated RF-DAC provides 3.6 dB EVM improvement for QPSK. Althoughthe effective resolution after predistortion is reduced to 3.6ENOB, the EVM stillimproves as the output voltage becomes more linear around the average codes. The16-QAM EVM does not yet meet the standard requirement of the SC mode (evenwithout taking the phase noise contribution of an on-chip PLL into account) that isused in measurements for its low PAPR [Bourdoux08a]. This shows the importanceof improving the RF-DAC linearity (e.g., by reducing the signal leakage), especiallyfor high-datarate scenarios.

Output PSD and Constellation

The QPSK modulated signal output spectrum from 45 to 70 GHz, with and withoutpredistortion is shown in Fig. 4.49. The predistorted signal has an improved out-put spectrum, while still slightly exceeding the 802.11ad spectral mask out-of-band(around 57 and 62 GHz) due to leakage. The figure also shows the spectrum mea-sured by the analyzer when no cable is connected to its input port. This shows thatspurious tones at 50 and 67 GHz (the analyzers maximum frequency) are generatedinternally. With an LO frequency of 59 GHz, the first lower-side and upper-sidespectral images are expected to be at 49 GHz and 69 GHz, respectively. The RF-DACs spectral images are better than 30 dB lower than the modulated signal, whichis required by the 802.11ad spectral mask. This is achieved thanks to oversamplingas well as the finite TX input and output bandwidths.

Figure 4.50 shows the QPSK and 16-QAM constellations for the polar TX, withand without RF-DAC predistortion. The deformations seen in the 16-QAM constel-lation without predistortion are due to the non-ideal static behavior of the RF-DAC


Fig. 4.49 Output PSD withand without PD1predistortion

-70

-60

-50

-40

-30

-20

-10

45 50 55 60 65 70

No PDw/PDNo output

Frequency (GHz)Po

ut (d

Bm)

802.11ad mask

Analyzer max. freq.1st alias belowanalyzer jump

1

RBW 3MHz

(see Fig. 4.45a), where the inner constellation points are pushed away from the cen-ter, as expected, due to leakage. The outer points are affected by the compressionand relative phase error of large amplitudes compared to the middle codes. Whenpredistortion is applied, the outer constellation points are corrected, as the higheramplitude codes of the predistorted static curve in Fig. 4.48a lie on a linear curve,while the inner constellation points are deformed due to clipping at lower codes.

When code ‘0’ is reused for all the codes from ‘0’ to ‘4’, a large phase stepoccurs between the lower and higher input codes (see Fig. 4.45a), causing a constantphase error (i.e., rotation) for the inner constellation points. In the third column,a trial is made to compensate the TX leakage in the receiver to explore its effecton EVM. The received signal is first split into amplitude and phase, then a fixedvalue that corresponds to the signal leakage is subtracted from the amplitude signal.After the modified amplitude and the phase signals are recombined, the signal is thenprocessed normally in the RX chain. The QPSK signal shows an EVM of −21.2 dB,while the 16-QAM EVM is improved to −18.6 dB. In this case, the 16-QAM outerconstellation points are similar to the first column, where no predistortion is applied.The inner constellation points are improved, as the effect of signal leakage is muchreduced. Compensating the leakage signal after PD1 predistortion by subtracting afixed value from its received amplitude does not improve the EVM, because anotheroffset will be created in the transfer function (i.e., output voltage versus the inputamplitude code) that causes deviation from the (ideal) linear behavior of the RF-DAC(seen in Fig. 4.48a).

4.4.3 Analysis and Discussion

In order to get more insight into the effect of RF-DAC non-idealities, especially AM-AM on EVM, the measured static curve is used to implement aMatlabTM model, anddifferent linearization techniques are compared. The measured QPSK EVM valuesof Fig. 4.47 are shown again in Fig. 4.51a to verify that themodel can fit themeasureddata (also 16-QAM at 16 RF-DAC levels gives −16.4 dB in simulation comparedto −16.5 dB in measurement). Figure 4.51b shows a MatlabTM simulation, wherethe amplitude of the leakage signal in Fig. 4.45a is swept from 0 to 1 V, and phaseerrors are ideally compensated. An EVM value of −21.4 dB is simulated for 0.3 V


No PD With PD1 Compensated

Leakage

EVM=-20.7dB EVM=-23.6dB

EVM=-16.5dB EVM=-18.1dB

EVM=-21.2dB

EVM=-18.6dB

Fig. 4.50 Measured QPSK and 16-QAM constellations

-22

-21

-20

-19

-18

-17

-16

8 10 12 14 16

Sim.Meas.

RF-DAC Levels

EVM

(dB)

QPSK

(a)

-30

-26

-22

-18

-14

0 0.5 1Offset Voltage (V)

EVM

(dB)

(b)

Fig. 4.51 a Simulated and measured EVM versus the number of used top RF-DAC levels, and bsimulated effect of signal leakage on EVM

leakage amplitude, which corresponds to the measured leakage. The simulated EVMimproves to −26.1 dB at no leakage, and is dominated by the AM-AM nonlinearity.

In the following analysis, the RF-DAC signal leakage is fully compensated in theRX digital domain, and the AM-PM errors are predistorted with infinite resolution.This focuses the analysis on the AM-AM behavior of the RF-DAC. Furthermore,when reducing the effective RF-DAC resolution by using only its higher levels, thesignal is allowed to scale and fit the remainingRF-DAC levels instead of being shiftedand clipped from the top. This leaves us with only the quantization error beside theAM-AM nonlinearity to be investigated.

Figure 4.52 shows the effect of linearizing theRF-DACoutput voltage by a straightline passing through the first and last code voltages. As shown in Fig. 4.52b, QPSK inthis predistortion method (PD2) achieves −29.3 dB EVM, while 16-QAM reaches


0

5

10

15

0

0.5

1

1.5

0 5 10 15

PD2 Code

Input Code

Vout

(V)

Static

w/PD2

ReferenceAM-AM

(a)

-30

-26

-22

-18

-14

8 10 12 14 16

RF-DAC Levels

EVM

(dB)

16QAM

Simulatedw/PD2

QPSK(b)

Fig. 4.52 RF-DAC a PD2 behavior, and b its simulated performance on top of measured andsimulated data without predistortion

Code xCode x+1

Input Code

Vout

(V)

0.3

1

(a)

-29

-28

-27

-26

-25

-24

0 5 10 15Code x

EVM

(dB)

Simulated

QPSK

16QAM

(b)

Fig. 4.53 a Applying a voltage step on the ideal line of PD2, and b its influence on EVM

−23.6 dB at the maximum RF-DAC resolution. However, the 16-QAM EVM isimprovedwhen using theRF-DACs top 14 or 15 levels compared to its full resolution.This can be understood by looking at the signal histogram of Fig. 4.6b. The averageand most influential code in the 16-QAM signal is ‘7’, which is very close to a notchin PD2 that deviates from the ideal straight line (see Fig. 4.52a). When using thehigher 14 or 15 RF-DAC levels, the average code is increased, going far from thenotch and towards a more linear part of the PD2 curve. When using fewer RF-DAClevels the effect of ENOB begins to affect EVM.

The effect of a non-ideality of the AM-AM curve at a certain code on EVM isanalyzed by introducing a step in the ideal PD2 line (as shown in Fig. 4.53a), thatis swept form code ‘0’ to the maximum RF-DAC code. Figure 4.53b shows that theworst EVM indeed occurs with a step at code ‘7’, and that the EVM behavior followsthe signal histogram of Fig. 4.6b. This explains the 16-QAM EVM degradation atmaximum RF-DAC levels, where two non-idealities occur at codes ‘3’ and ‘6’. Theaverage code for a QPSK signal is ‘9’ with a narrower distribution over input codesand reduced effect of a step on the signal EVM, explaining its ideal EVM behaviorversus the number of used RF-DAC levels.

In order to improve the 16-QAM EVM, a third predistortion technique (PD3) isemployedwhich has amore linear RF-DAC static curve till code ‘11’ (see Fig. 4.54a).


0

5

10

15

0

0.5

1

1.5

0 5 10 15

PD3 Code

Input Code

Vout

(V)

Static

w/PD3

ReferenceAM-AM

(a)

-30

-26

-22

-18

-14

8 10 12 14 16RF-DAC levels

EVM

(dB)

16QAM

Simulatedw/PD3

QPSK

(b)

Fig. 4.54 RF-DAC a PD3 behavior, and b its simulated performance on top of measured andsimulated data without predistortion

Table 4.4 Simulated EVM of PD2 and PD3 AM-AM predistortion techniques assuming idealAM-PM calibration and signal leakage compensation

PD2 PD3

ENOB (bits) 3.8 3.6

EVM (dB) QPSK –29.3 –28.2

16-QAM –23.6 –27

The simulated EVM performance with PD3 is shown in Fig. 4.54b, where the 16-QAM signal achieves an EVM of−27 dB with a monotonic degradation when usingfewer RF-DAC levels. This improvement is because the non-ideality in the RF-DACstatic curve with PD3 is above code ‘11’, where the effect on EVM is minimal (seeFig. 4.53b). The useful RF-DAC levels after PD3 are 12 levels (ENOB of 3.6 bits)compared to 14 levels in PD2 (ENOBof 3.8 bits), leading to aQPSKEVMof−28.16dB compared to−29.3 dB in PD2 because of the lower RF-DAC effective resolution.

In this part, the effect of different AM-AM calibration algorithms on EVM isshown, where the reasoning behind their difference and possible degradation due tothe use of one of the algorithms is also explained. Table 4.4 summarizes the EVMvalues of PD2 and PD3 predistortion techniques. This comparison is also beneficialfor an RF-DAC without signal leakage. In this case, the average output power willbe close to that of PD1 predistortion.

4.4.4 Comparison with State-of-the-Art

Table 4.5 compares this work with other TX architectures based on either linearor nonlinear PA implementations. Nonlinear PA operation realizes higher averageefficiencies compared to a linear PA.At the same output power back-off, the proposedpolar TX places itself well among the non-linear PA implementations with 15.3%


Tabl

e4.

5Com

parisonwith

state-of-the-art

Vidojkovicetal.

[Vidojkovic13]

Kulkarniand

Reynaert

[Kulkarni14]

Zahoetal.

[Zhao12b

]Kaymaksutetal.

[Kaymaksut14]

Chenetal.

[Chen13]

5-bitC

hip

4-bitC

hip

TXtype

Class-A

/AB

Push-Pull

(PA)

Outphasing

Doherty

(PA)

SpatialD

igital

Cartesian

DigitalP

olar

Class-A

DigitalP

olar

Frequency(G

Hz)

6060

6077

6060

60

Technology

40nm

-LP

40nm

40nm

40nm

65nm

40nm

40nm

Supply

(V)

1.1

1.8

10.9

10.9

0.9

P sat(dBm)

14/10.3

16.4

15.6

16.2

9.6

–3.9

10.8

P1dB

(dBm)

10.8/8

13.9

1315.2

NA

–5.5

7.4

Gain(dB)

31/22.5

22.4

25.5

9.1

NA

22.5

24.3

P sat

÷Pdc

,PA(%

)32/22

2425

23.5

28.5

0.5

29.8

OutputA

M-PM

(o)

NA

0.2/2.3

15NA

NA

NA

NA

32/7

RF-DAC

Resolution(bits)

NA

NA

NA

NA

55

NA

4

Sampl.rate(G

S/s)

NA

NA

NA

NA

7.8

5NA

10

5dB

P out

back-off

P av(dBm)

5.8/3

8.9

10.6

10.2

4.6

–8.9

2.4

5.3

P av÷

P dc,PA

(%)

4.9/7.4

89.1a

12.5a

17a

0.2

5.6

15.3

P av

÷P d

c,PA

+Mixer

(%)

2.1b

NA

5.2

NA

7b0.2

3.5

8.4

QPS

KEVM

(dB)

NA

NA

–34

NA

–15

–29.3(420

Mb/s)

–30

–23.6

Rate(G

b/s)

QPS

K3.5

NA

3.5

NA

3.5

0.42

3.5

3.3

16-Q

AM

7NA

0.5

NA

60.83

76.7

Corearea

(mm2)

<0.18

0.08

0.33

0.1

0.75

a<0.18

<0.18

a Estim

ated

basedon

theavailablepu

blishedfig

ures

bIncludes

contributio

nof

baseband

andLO


average PA efficiency using a QPSK modulated signal, while the EVM should stillbe improved for higher modulations. Compared to the same PA operating in class-A,the average drain efficiency increased by 2.7× due to the polar operation. The 0.18mm2 core area of the polar TX is at least one-half the area occupied by other TXimplementations based on nonlinear PAs, because it uses only a single PA in thesignal path.

4.4.5 Conclusions

A60GHzRF-DAC-based polar TX is implemented in thiswork,where the amplitudesignal modulates a 4-bit RF-DAC that is sampled at 10GS/s with 6× oversampling toachieve−30 dB attenuation of the spectral image. The main polar TX challenges areaddressed, where the TX phase path input provides more than 3.1 GHz bandwidthand the amplitude-phase paths were synchronized with a 50 ps delay resolution.The PA delivers a maximum output power of 10.8 dBm with 29.8% drain efficiencythat remains above 20% over 12.5 GHz. The average output power and PA drainefficiency are 8.1 dBm and 22.3% without predistortion for QPSK, respectively. Thecorresponding 16-QAM values are 7.2 dBm power and 19.8% efficiency. When theamplitude signal leakage is compensated in the receiver, QPSK and 16-QAM EVMvalues of−21.2 and−18.6 dB are achieved. AM-AMpredistortion is used to achievea signal EVM of −23.6 and −18.1 dB for QPSK and 16-QAM, respectively. In thiscase, the average output power and PA drain efficiency are 5.3 dBm and 15.3% forQPSK, and 3.5 dBmand 11.6% for 16-QAM.The signal EVM is currently dominatedby parasitic signal leakage through the RF-DAC in its off state. Simulations showthat QPSK and 16-QAM EVM values down to −29.3 dB and −27 dB, respectively,could be achieved without signal leakage. The CMOS chip, fabricated in 40 nm,delivers QPSK and 16-QAM datarates of 3.33 and 6.67 Gb/s, while occupying 0.18mm2 core of the 2.38 mm2 total area.

Chapter 5Summary and Conclusions

Driven by the demand for higher (>1Gb/s) datarate communication, low-powerTX front-end implementations targeting 60GHz frequency band are investigatedin this work. Five chips are demonstrated enhancing the PA operating efficiencyfrom 2 to 15.3%. The first three chips build on the conventional linear PA approachadding neutralization, class-AB operation and using design optimization techniquesto achieve a better performance,while the other two chipsmove to a polar architecturewith an RF-DAC output stage targeting 3x efficiency improvement.

5.1 Conclusions

Starting from a 40nm-LP 3-stage class-A push-pull PA configuration with a maxi-mum and 5dB back-off drain efficiencies of 13% and 2%, respectively, considerableimprovements in the peak and average PA efficiencies were achieved. A neutral-ized class-AB is introduced to have 5.7% back-off efficiency. With optimal passivedesign, a 2-stage class-A/AB PA is implemented achieving a maximum drain effi-ciency of 32.8% and a 5dB back-off efficiency of at least 7.4%. In 28nm technology,the topology is reused to achieve 11.4% drain efficiency at 5dB back-off.

More disruptive approach is considered to push the back-off efficiency even fur-ther. In a conventional TX architecture using a linear PA (see Fig. 5.1a), the powerconsumption is dominated by the PA. In a digital polar architecture (see Fig. 5.1b),the PA is allowed to operate in saturation utilizing its maximum efficiency. Phasemodulation is implementedwith upconversionmixers, and the amplitude signalmod-


97


https://doi.org/10.1007/978-3-030-16653-3_5

98 5 Summary and Conclusions

A(t)sin(φ(t))

A(t)cos(φ(t))cos(ω t)0

sin(ω t)0

A(t)sin(ω t+φ(t))0 (a)

sin(φ(t))

cos(φ(t))

A(t)sin(ω t+φ(t))0

cos(ω t)0

sin(ω t)0

τA(t)(b)

Fig. 5.1 Implemented TX architectures: a conventional analog Cartesian and b digital polar withmixer upconversion

ulates an RF-DAC. Two chips in 40nm-GP bulk CMOS are used to explore the polarTX operation at 60GHz, showing efficient operation in saturation, full datarate andmitigated out-of-band distortion.

The first chip uses a 5-bit RF-DACwith gate-switched unit cell, and an upconver-sion mixer based on voltage feedback transconductor. The chip achieves an EVM of−29.3dB when using a QPSK modulation and −24.2dB with 16-QAM at low (i.e.,208.33Msymbols/s) datarate and reduced output power. In the second chip, a 4-bitRF-DAC sampled at 10GS/s is used with source-switched unit cell and a Gilbert-cellupconversion mixer. The chip achieves a QPSK average output power of 5.3dBmwith 15.3% average PA drain efficiency. The modulated signals achieve EVM valuesof−23.6dB and−18.6dB at 3.33Gb/s and 6.67Gb/s datarates while still complyingwith 802.11ad spectral mask for QPSK and 16-QAM, respectively. Each chip has atotal area of 2.38mm2, while the core circuit occupies only 0.18mm2 including thePA, mixer LO distribution and digital interface circuitry. Both chips show the poten-tial of digital PA implementations and polar architectures to be used at mm-waves,representing a chance to further reduce the power consumption of mm-wave highdatarate transmitter solutions.

5.2 Possible Future Work 99

5.2 Possible Future Work

In a future work, reducing signal leakage in the RF-DAC off state is necessaryto improve the EVM of 16-QAM modulation, relaxing the requirement on PLLcontribution, and to have larger margin for the spectral mask. A value of −30dBEVM should be targeted in the front-end (i.e., PA andmixer combination) to transmit64-QAM constellations without dominating the total TX EVM. The pre-pA can beswitched in order not to consume a fixed DC current and the output matching can beoptimized for the middle code to improve the average PA efficiency (i.e., at lowercodes). Further increasing the average PA efficiency requires supply modulation,which is challenging for 802.11ad due to the large bandwidth requirement.

For a full TX system, the DSP needs to be integrated on-chip. The challenge thereis to keep all the additional functionalities over that of a conventional linear PA-basedTX architecture within a small (e.g., 50mW) power budget. This includes the extraupsampling factor, I-Q to polar conversion, AM-AM and AM-PM predistortions andamplitude-phase path synchronization. Applying more filtering at the phase pathinput adds extra attenuation to the aliases, and thus relaxes the RF-DAC switchingspeed requirement that directly affects the DSP complexity and power consumption(e.g., an oversampling ratio of 4 can be used at lower phase path input bandwidthat the expense of limited EVM degradation). Practically, a feedback form eitherthe transmitted or received output is necessary to form a closed loop for automaticcalibration (predistortion and synchronization).

Two more elements need to be implemented for a full system prototype: Two10GS/s DACs in the phase path, and a delay element with 10ps that can be either inthe amplitude or phase path.DAC implementationswith >8 bits andmulti-GS/s speedare reported [Olieman15, Nazemi15]. Delay elements with less than 1ps resolutionand more than 8 bits are implemented in CMOS [Markulic14, Ru15].

Other digital TX implementations can also be considered. The digital Cartesianarchitecture (seeFig. 5.2a) does not suffer frombandwidth expansion and the required


cos(ω t)0

sin(ω t)0

I(t)=A(t)sin( (t))φ

Q(t)=A(t)cos( (t))φ

(a)


τA(t)

φ(t)

sin(ω t+φ(t))0

(b)

Fig. 5.2 Potential TX architectures: a digital Cartesian and b digital polar with VCO injection

100 5 Summary and Conclusions

synchronization. A similar architecture is reported in [Chen13], where one antenna isused in each I or Q PA, and their output is combined in the air. Two-fold interpolationis used in the PA to boost the effective resolution (one extra bit) and sampling rate(x2). The systemEVMof−16.2dB, however, could bemuch improvedwith the samearchitecture. On-chip power combining is more reliable and occupies less footprintthan spatial combining, while less than 1dB losses could be achieved at 60GHz([Zhao13]).

Taking the mm-wave digital polar architecture another step forward, injecting thephase signal into a VCO/DCO (see Fig. 5.2b) instead of being upconverted with theI-Q mixers could be investigated. In this case, at least the mixers can be omittedfrom the TX power consumption budget. If the DCO is used, the baseband filtersand DACs will also be omitted. As the phase signal bandwidth is >1GHz and thePLL loop bandwidth is in the order of 1MHz, the low frequency part of the phasesignal can be neglected and a single-point injection in the VCO/DCO should besufficient without an effective influence on the signal quality. The main challenge inthis topology would be the VCO/DCO gain linearity requirement (the DCO couldbe preferred in this case), which may require additional predistortion in the digitaldomain. Additionally, the input signal is only the phase instead of sin(ϕ) or cos(ϕ),which has more bandwidth due to the phase jumps while the signal trajectory crosses‘0’. This requires implementing zero-crossing algorithms in the DSP to relax thetuning range requirement on the VCO/DCO.

Acomparisonbetween the4 architectures inFigs. 5.1 and5.2 is shown inTable 5.1.The digital polar with VCO injection has the least analog hardware with only an in-phase VCO or DCO and a digital PA, while DSP is required to provide the maximumnumber of functionalities including the VCO/DCO gain (Kvco) nonlinearity calibra-tion and a zero-crossing avoidance algorithm.

Table 5.1 Comparison between different TX architectures for minimum TX power consumptionTX architecture Analog cartesian

(Class-A)Digital cartesian Digital polar with

mixer upconversionDigital polar with VCOinjection

PA relativeefficiency

1× >3× >3× >3×

Relative Pout @same PA size

1× <2× (powercombiner)

1× 1×

Number of analogblocks

PA, QVCO, 2mixers, 2 filters, 2DACs

2 PAs, QVCO PA, QVCO, 2mixers, 2 filters, 2DACs

PA, (DAC+filter+VCO)or (DCO)

Oversampling factor 2 (3.52GS/s) 6 (10.56GS/s) 4 (7.04GS/s) or 6 >4

Input BWrequirement (GHz)

0.88 0.88 2 >2

Extra DSPfunctionality

Simplest AM-AM + AM-PMpredistortion (at 3×higher samplingspeed)

I-Q to polarconversion,AM-AM + AM-PMpredistortion,synchronization (at2× higher samplingspeed)

I-Q to polar conversion,AM-AM +AM-PM +Kvco predistortion,synchronization (at >2×higher sampling speed),zero-crossingselimination

AppendixLoaded Transformer Input Impedance

Figure A.1a shows a possible representation of the transformer model, where a seriesresistance is added to the model in [Long00]. Figure A.1b shows the transformermodel when loaded with a complex impedance.

The input impedance can be written as following:

Zin = (ZL1 − XM) + XM//(ZL2 − XM + ZL)

= ZL1 − XM + XM(ZL2 − XM + ZL)

ZL2 + ZL

= ZL1 − X2M

ZL2 + ZL

(A.1)

XM in A.1 is jωM, where M is the mutual inductance, and can be written as:

M = k × √L1L2 (A.2)

Equation A.1 can then be written as:

Zin = r1 + jωL1 + k2ω2L1L2

r2 + jωL2 + RL

1 + jωCL RL

(A.3)

© Springer Nature Switzerland AG 2019K. Khalaf et al., Low-Power Millimeter Wave Transmitters for HighData Rate Applications, Signals and Communication Technology,https://doi.org/10.1007/978-3-030-16653-3

101

https://doi.org/10.1007/978-3-030-16653-3

102 Appendix: Loaded Transformer Input Impedance

Fig. A.1 a Equivalenttransformer model and bwhen loaded with a compleximpedance

L1

kr1

L2

r2L2-Mr2L1-M r1

M

CL RL

L2-Mr2L1-M r1

MZin

(a)

(b)

A.1 Real Part of the Input Impedance

The real part of Eq. A.3 can be written as following:

Real(Zin) = r1 + k2ω2L1L2[r2 + RL(1 − ω2L2CL) + ω2RLCL(L2 + r2RLCL)][r2 + RL(1 − ω2L2CL)]2 + ω2(L2 + r2RLCL)2

(A.4)It can be shown that the real part of the input impedance can be written as:

Real(Zin) = r1 + k2ω2L1L2{RL + r2[1 + (ωRLCL)2]}

r2{2RL + r2[1 + (ωRLCL)2]2} + R2L(1 − ω2L2CL)2 + (ωL2)2

(A.5)

A.2 Imaginary Part of the Input Impedance

The imaginary part of Eq. A.3 can be written as following:

Imag(Zin) = ωL1

+ k2ω2L1L2{ jωRLCL(r2 + RL − ω2RLCL L2) − jω(L2 + r2RLCL)}r2{2RL + r2[1 + (ωRLCL)2]2} + R2

L(1 − ω2L2CL)2 + (ωL2)2(A.6)

Appendix: Loaded Transformer Input Impedance 103

It can be shown that the imaginary part of the input impedance can be written as:

Imag(Zin) = ωL1(1+k2ω2L2[R2

LCL(1 − ω2L2CL) − L2]r2{2RL + r2[1 + (ωRLCL)2]} + R2

L(1 − ω2L2CL)2 + (ωL2)2) (A.7)

A.3 Simplified Input Impedance Equations

If we assume an infinite quality factor, Eqs.A.5 andA.7 can be rewritten as following:

Real(Zin) = k2ω2L1L2RL

R2L(1 − ω2L2CL)2 + (ωL2)2

(A.8)

Imag(Zin) = ωL1(1 + k2ω2L2[R2LCL(1 − ω2L2CL) − L2]

R2L(1 − ω2L2CL)2 + (ωL2)2

) (A.9)

If the load is only capacitive (i.e., RL is approaching infinity), the equationsbecome:

Real(Zin) = k2ω2L1L2

RL(1 − ω2L2CL)2= 0 (A.10)

Imag(Zin) = ωL1(1 + k2ω2L2CL

1 − ω2L2CL) (A.11)

If the load is only resistive, Eqs. A.8 and A.9 become:

Real(Zin) = k2ω2L1L2RL

R2L + (ωL2)2

(A.12)

Imag(Zin) = ωL1(1 − k2(ωL2)2

R2L + (ωL2)2

) (A.13)

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