K.K. Gan US ATLAS Pixel Meeting 1

Opto-IC/Board

K.K. Gan

The Ohio State University

WBS 1.1.1.3 & 4

July 9, 2003

K.K. Gan US ATLAS Pixel Meeting 2

Outline

Introduction

VDC/DORIC

Opto-board

Cost and schedule summary

Conclusions

K.K. Gan US ATLAS Pixel Meeting 3

ATLAS Pixel Opto-link

K.K. Gan US ATLAS Pixel Meeting 4

OSU Responsibilities

VDC and DORIC:

design testing of 50% of final production

Opto-board:

design and fabrication testing of 50% of final production?

K.K. Gan US ATLAS Pixel Meeting 5

OSU ATLAS Personnel

FacultyK.K. Gan, Harris Kagan, Richard Kass

Research AssociatesAmir Rahimi, Mike Zoeller

Graduate StudentsKregg Arms, Rouben Ter-Antonian

EngineersMark Johnson, Chuck Rush

TechniciansJim Burns, Jason Moore, Shane Smith, Bob Wells

new

new

K.K. Gan US ATLAS Pixel Meeting 6

VDC: convert LVDS signal into single-end signal to drive VCSEL

DORIC: extract clock and command signal from bi-phase mark encoded signal received at PIN

five IBM prototype runs with various improvements andchanges in response to opto-pack evolutionfour MPW runs plus one with FE/MCC-I1

VDC/DORIC-I5e were submitted with MCC-I2 as engineering runconvert from 3-metal MPW layout to 5-metal layoutminor improvements in DORIC-I5e

this will be production run if performance is satisfactory

Status of VDC/DORIC

K.K. Gan US ATLAS Pixel Meeting 7

bright current is similar to I5 dim current is similar to I5 and close to target 1 mA rise/fall times, duty cycle, current consumption within specs

VDC-I5e: Bright and Dim Currents vs. Iset

VDC-I5e

VDC-I5

high power oxide VCSEL

0

4

8

12

16

0.0 0.4 0.8 1.2 1.6 2.0

Iset (mA)

IVCSEL

(mA)

K.K. Gan US ATLAS Pixel Meeting 8

started with 1-channel VCSEL

adapted 8-channel p+ VCSEL to use with MT connector

converted to oxide VCSELbecause p+ has been discontinued by Truelight

converted to high-power oxide VCSELbecause normal oxide has been discontinued by Truelight

VCSEL Opto-pack Evolution

K.K. Gan US ATLAS Pixel Meeting 9

p+/oxide VCSELs have similar optical power in operating range (10-20 mA)

oxide VCSELs have larger effective serial resistance

smaller VCSEL current when driven by VDC

I-V Curves/Optical Power ofP+, Normal & High Power Oxide VCSELs

high power oxide (3 arrays)normal oxidehigh power oxide (2 arrays)p+

0.0

1.0

2.0

3.0

0 5 10 15 20

Current (mA)

Voltage (V)

0

1000

2000

3000

Optical Power (

μ )W

K.K. Gan US ATLAS Pixel Meeting 10

some VCSEL arrays contain a channel with much larger effective serial resistance

maximum VCSEL current of 10 mA when driven by VDCsignificantly below target of 20 mA annealing current

I-V Curve of High Power Oxide VCSELs

normal oxide

high power oxide

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0 2 4 6 8 10 12 14 16 18 20

Current (mA)

Voltage (V)

0

1000

2000

3000

Optical Power (

μ )W

p+ with 10

high power oxide

0

5

10

15

20

0.0 0.4 0.8 1.2 1.6 2.0

Iset (mA)

IVCSEL

(mA)VDC6 Channel 1, NormalVDC6 Channel 2, NormalVDC6 Channel 3, NormalVDC6 Channel 4, NormalVDC6 Channel 1, High PowerVDC6 Channel 2, High PowerVDC6 Channel 3, High PowerVDC6 Channel 4, High PowerVDC1 Channel 1, P+, with 10 ohmVDC1 Channel 2, P+, with 10 ohmVDC1 Channel 3, P+, with 10 ohmVDC1 Channel 4, P+, with 10 ohm

K.K. Gan US ATLAS Pixel Meeting 11

some links have twice as worse PIN current thresholds for no bit errors

measured with all clocks running asynchronically

High Power Oxide VCSEL with Negative Common Cathode

0

20

40

60

1 2 3 4 5 6 7

Link

IPIN

(μ)A

20 mAVc @ -0.2 V

10 mAVc @ gnd

other links @ 80 μA

other links off

K.K. Gan US ATLAS Pixel Meeting 12

0

10

20

30

40

50

60

1 2 3 4

DORIC-I5e #1DORIC-I5e #2DORIC-I5 #6DORIC-I5 #3

Threshold (uA)

Link

PIN current thresholds for no bit errors measured with 44-pin packages

thresholds are low and similar to DORIC-I5

expect lower thresholds on opto-board as DORIC-I5

upper thresholds > 1200 μA successfully converted reset from active high to low

DORIC-I5e: PIN Current Thresholds for No Bit Errors

K.K. Gan US ATLAS Pixel Meeting 13

control circuit boards: designed/built/tested

LabView programs: written/tested

VDC/DORIC QA plan: currently use packaged chips to exercise QA system have received probe cards perform QA with probe station

opto-board QA plan: perform QA in temperature controlled chamber

QA system almost ready for production

VDC/DORIC/Opto-board Quality Assurance

K.K. Gan US ATLAS Pixel Meeting 14

converts: optical signal electrical signal

contains 6-7 optical links:

layers 1 and 2 optical link:

2 DORICs, 2 VDCs, PIN/VCSEL (opto-pack)

B layer optical link:

2 DORICs, 4 VDCs, PIN/2 VCSEL (opto-pack)

use BeO for heat management but prototype initiallyin FR-4 for fast turnaround and cost saving have four FR-4 prototype runs to accommodate

various design changes in chips/opto-packs

Opto-Board

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First batch: 30 boards delivered in April several open vias on each board due to insufficient gold filling

repair with wire-wrap wires

Status of BeO Opto-board

VDC-I5 opto-pack

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PIN Current Thresholds for No Bit Errors

low PIN current thresholds for no bit errorsindependent of activity in adjacent channels no design errors

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Second batch: 31 boards delivered in June vias overfilled and excess metal ground away

no open vias 17 boards have shorts between power and ground lines attempt to populate a second BeO board:

opto-pack housing fits wellone DORIC mounted backwardno visible damage to adjacent chip after replacementboard failed to workreplaced both DORICsopto-board now works!

Status of BeO Opto-board

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BeO Opto-board from 2nd Batch

VDC housingDORIC opto-pack latch broken

34.7 oC 36.4 oC

Ambient:22.5 oC

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both opto-boards have low PIN current thresholds for no bit errorsindependent of activity in adjacent channels will produce opto-boards with second vendor

PIN Current Thresholds for No Bit Errors

0

10

20

30

40

0 1 2 3 4 5 6 7 8

Link

IPIN (

μ)A

, #1Other Links with no input BeO batch

40 , #1All Other PINs Have uA BeO batch

, #2Other Links with no input BeO batch

80 , #2All Other PINs Have uA BeO batch

2nd batch

1st batch

OSU

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Opto-Link Proton Irradiations four 24-GeV proton irradiations at CERN in last three years

OSU designed and fabricated all test systems: cold box: electrical test of DORIC/VDC shuttle: test of opto-link on opto-boards

BER testerfibersopto-board

K.K. Gan US ATLAS Pixel Meeting 21

duty cycle increases by ~ 2% after 58 Mrad

VDC-I4: Clock Duty Cycle vs. Dosage

44

46

48

50

52

54

56

0 10 20 30 40 50 60

Dosage (Mrad)

Duty Cycle (%)

link1

link2

link3

link4

link5

link6

link7

link8

K.K. Gan US ATLAS Pixel Meeting 22

VCSELs annealed with 20 mA during indicated periodsPIN current thresholds for no bit errors remain constant up to 21 Mrad

Opto-Board Bit Error Threshold vs. Dosage

0

5

10

15

20

25

30

IPIN

(μ)A

Start

3.1Mrad9hours12hours6.2Mrad15hours8.3Mrad12hours12.2Mrad

14hours13.8Mrad

9hours13hours16.9Mrad

12hours21.0Mrad

3Link

4Link

5Link

6Link

Dosage/VCSEL Annealing Time

K.K. Gan US ATLAS Pixel Meeting 23

opto-link with DORIC/VDC-I3 and p+ VCSEL opto-pack meets radiation specs

August 2003 irradiation: double irradiation statistics:

cold box: four 4-channel DORIC/VDC shuttle: four opto-boards

Proton Irradiation Summary and Plan

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cost adjustments:

BeO opto-board prototype run with new vendor: $15K

increase cost for production BeO boards: $30K

increase cost for SMD mounting of production BeO boards: $3K

technician for opto-board production: $57K

no funds allocated in FY04 irradiation:need irradiation of random sample of production opto-boards?

WBS 1.1.1.4 FY04ETC03: $78K?ETC04: $78K+$105K

Changes in ETC04

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Opto-Board Milestones

WBS Task_Name Baseline Date ETC02 Date ETC03 Date1.1.1.4.1 Optical FDR 31-Jan-02 10-Oct-02 28-Feb-03 Optical PRR 5-Mar-03 12-Jun-03 12-Jun-03 Release initial MC for optical components 19-Mar-03 26-Jun-031.1.1.4.3 First optical boards 20-Aug-03 20-Nov-03 Optical production complete 24-Dec-03 24-May-04

???

??? ???

K.K. Gan US ATLAS Pixel Meeting 26

preliminary results indicate that DORIC/VDC-I5ecan be used for production opto-boards

BeO prototype opto-board can operate with low PIN current thresholdsno technical problem is foreseen but first vendor is unsatisfactory

Summary