konstantin stefanov, cclrc rutherford appleton laboratory pprp open session: lcfi, iop, 8 th...

Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory PPRP open session: LCFI, IoP, 8th September 2004 1

Linear Collider Flavour Identification (LCFI)

--- Part 2 ---

Goals for the detector R&D

Overview of the work during the last 3 years

Current status and future directions

Plans for the next year and beyond

Konstantin Stefanov (RAL) on behalf of the LCFI collaboration

PPRP Open Session, IoP, 8th September 2004


Goals for detector R&D

Initially detector R&D addressed the requirements of both “warm” and “cold” accelerators

Driven mainly by the cold machine - much more challenging in terms of signal readout

The cold machine has been selected (20 August 2004)

Main detector parameters:

Inner layer effectively read out at 50 μs intervals during the 1 ms pulse train (20 readouts) – information may leave the sensor or be stored in pixel

Outer layers read out at 100 μs intervals

Immune to EMI from RF leakage

Pixel size 20 μm 20 μm

Radiation hard

Low power dissipation

Thin mechanical support structure – Sonja’s talk


Two approaches to detector R&D

Fast column parallel CCD with 50 MHz readout:

Currently main detector R&D at LCFI

Established technology

Possible vulnerability to RF pickup: ~1000 electrons from 109 pixels are read out 20 times during the bunch train

Challenge to drive at high speeds

In-situ Storage Image Sensor (ISIS), “new idea” from LCFI (since December 2003):

High immunity to EMI

20 charge samples stored in pixel and read out during the “quiet” period

Could require significant R&D

CPR-1/CPR-2 readout chip applicable to ISIS as well


Summary of the detector R&D over the last 3 years

Main goal – develop Column-Parallel CCD (CPCCD) with CMOS readout

First CPCCD (CPC-1) manufactured by e2V with significant input from LCFI

CPC-1 successfully tested stand-alone

CMOS readout chip (CPR-1) designed at RAL, manufactured by IBM and performing well

Hybrid assembly CPC-1/CPR-1 bump bonded by VTT

Everything worked extremely well

Next generation devices CPC-2 and CPR-2 near completion

Very successful programme overall


Our first CPCCD (CPC-1)

Two phase, pixel size 20 μm 20 μm;

400 (V) 750 (H) pixels;

Two charge transport regions;

Wire/bump bond connections to readout chip and external electronics.

Direct connections and 2-stage source followers

1-stage source followers and direct connections on 20 μm pitch

Manufactured by e2V (UK)

RAL

e2V


Main parameters of CPC-1

Metal-strapped gates for efficient clock propagation

CCD sensitivity 3.1 μV/electron

Optimised for low voltage operation – works with 1.9 Vpp clock amplitudes

Currently implanted inter-gate barrier

“Stepped nitride” barrier failed in a test wafer – to be resolved for the next device

In future 1 Vpp clock operation could be achieved

Clocked to 25 MHz, far beyond the original goal of 1 MHz

15 wafers made available to LCFI, 10-11 good chips/wafer;

CPC-1 multi-project wafer with 12 chips

RAL

e2V


Bump-bonded CPC-1 to readout chip

Bump-bonding done at VTT (solder bumps)

Very high quality connections

First time e2V CCDs have been bump-bonded

Bump-bonded CPC-1/CPR-1 in a test PCB Bump bonds on CPC-1 under microscope

Oxford U

RAL

e2V

VTT


Off-sensor electronics: CPR-1 RAL

IBMWire/bump bond pads

Wire/bump bond pads

250(W)132(L)5-bit FIFO

250 5-bit flash ADCs

Charge Amplifiers Voltage AmplifiersASIC for CPC-1 readout

Designed by the Microelectronics Group at RAL

Size : 6 mm 6.5 mm

Voltage amplifiers for the 1-stage SF outputs

Charge amplifiers for the direct outputs;

250 5-bit flash ADCs

Everything on 20 μm pitch, 0.25 μm CMOS process

Fully bump-bondable and partially wire-bondable

Scalable and designed to work at 50 MHzManufactured by IBM


CPR-1 response with X-ray signals from CPC-1

Charge channels :

86 mV expected, 70 mV observed – very good agreement;

Gain does not change across the array

1-in-3 channels with higher noise due to the wire-bondable pad

Voltage channels:

Gain in the centre of the array is ½ the gain at the edge

Most likely a timing problem

Noise ~ 60 electrons


CPR-1 and CPC-1 bump bonded RAL

VTT

IBM 7 assemblies delivered by VTT, 3 tested so far:

All CPC-1 worked perfectly

3 CPR-1 failed, dicing problems assumed – have taken measure to avoid that in the future

3 CPR-1 worked fine, tested with X-rays from 55Fe source

All working CPR-1: All ADC channels work fine; All charge amplifiers work 20% of voltage channels with no signal – currently under study

CPR-1 is very high speed, extremely sensitive to clock timing Power supply is 2.0 V instead of 2.5 V to improve ADC performance

Design of next generation CPR-2 with cluster finding and sparsified

readout near completion


Next generation CPCCD : CPC-2 Oxford U

RAL

e2V

Sufficient experience gained with CPC-1 to move to CPC-2

CPC-2 in design phase

Large area stitched device (up to 10 cm long) and several smaller chips

Even lower clocks amplitudes – stepped nitride barrier definition or low value implants

Compatible with CPR-1 and CPR-2

Two charge transport sections

Choice of epitaxial layers for different depletion depth

Baseline design allows few MHz operation for the largest size CPC-2

Clock bus

Main clock wire bonds

Extra pads for clock connection

Main clock wire bonds

CPR-1 CPR-2

Temperature diode on CCD

Charge injection

Four 1-stage and 2-stage SF in adjacent

columns

Four 2-stage SF in adjacent columns

Standard Field-enhanced Standard

Extra pads for clock monitoring and drive

every 5 mm

No connections

this side

Image area

Baseline design


Next generation CPCCD : CPC-2 Oxford U

RAL

e2V CPC-1 has asymmetric clock distribution and non-optimal drive conditions due to single level metal

Novel idea from LCFI for high-speed clock propagation: “busline-free” CCD:

The whole image area serves as a distributed busline

Highest speed potential: 50 MHz achievable with suitable driver

Φ1 Φ2

Φ1 Φ2

Level 1 metal

Polyimide

Level 2 metal

Φ2 Φ1

Φ2 Φ1

To multiple

wire bonds

To multiple

wire bonds

1 mm


RF pickup immunity is an issue for all detectors that convert charge into voltage during the bunch train;

Concerns about the RF immunity of the CPCCD triggered this idea:

Charge collected under a photogate;

Charge is transferred to 20-pixel storage CCD in situ, 20 times during the 1 ms-long train;

Charge is converted to voltage and read out in the 200 ms-long quiet period after the train, RF pickup is avoided;

1 MHz column-parallel readout is sufficient;

ISIS Concept

ISIS for particle detection


Additional ISIS advantages:

~100 times more radiation hard than normal CCDs – less charge transfers

Easier to drive because of the low clock frequency

Pure CCD-based ISIS for high-speed imaging already exists (storing 100 frames at 106 frames/s)

ISIS for particle detection combines CCDs, active electronics in pixel and some logic in one device

Specialised manufacturing process:

Typical CCD technology lacks multi-level metallisation

“Standard CMOS” technology cannot implement CCDs

Development and design of ISIS is more ambitious goal than CPCCD

International collaboration is the preferred way forward

ISIS Development RAL

e2V

(DALSA?)

(Sarnoff?)

Edge logic for row selection and clock gating not shown


Detector Perspective

Several groups interested in ISIS:

Nijmegen U, NIKHEF (Netherlands) – possible work with DALSA

Yale U, Oregon U (USA) – possible work with Sarnoff

LCFI talks and keeps in touch with the world’s experts in the field:

David Burt (e2V) – leading CCD expert

Albert Theuwissen (DALSA) – leading CCD expert, ISIS developer

Jim Janesick (Sarnoff) – expert in both CCD and CMOS imaging

e2V agreed to make small ISIS prototype as a part of the CPC-2 wafer batch, at no additional cost:

1616 array of photogates and buried channel CCD storage cells;

Single level metal, cell pitch 40 μm 160 μm;

No on-chip logic;

Will be evaluated in parallel with CPC-2;


Driver electronics and radiation damage effects

Oxford U

Lancaster U

Liverpool U

RAL

Driver electronics:

Fast CPCCD represents low impedance load, challenge to drive

Driver R&D has started

Will be expanded in the next 3-year proposal

Radiation damage effects:

LCFI has great expertise in radiation damage effects in CCDs:

Past studies on CCD58 (50 MHz 3-phase CCD)

Currently studies on CPC-1

Help decide between CPCCD and ISIS, provided that EMI is not a problem

Choose operating temperature for CPCCD – impact on thin ladder development


Plans and Summary

Plans for the next year and beyond:

Finish design and evaluate CPC-2, CPR-2 and ISIS-1 till ~Autumn 2005

Participate in a global effort to understand EMI issues, help with tests at SLAC and DESY

Achieve clearer view on the preferred detector technology

Will lead to the next 3-year proposal by LCFI

Our PPARC-funded 3-year programme has been extremely successful

LCFI is a strong collaboration between academic research and industry, with 25 years of experience working with UK industry

The International Linear Collider (ILC) is a major growth area both in UK and abroad

LCFI already in a leading position to contribute to the vertex detector at ILC and participate in its rich physics programme

konstantin stefanov, cclrc rutherford appleton laboratory pprp open session: lcfi, iop, 8 th...

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