kronse kt luf2012 final

© IMEC 2012

LITHOGRAPHY CHALLENGES FOR (SUB-)20NM

SEMICONDUCTOR TECHNOLOGY NODES

KURT G. RONSE

12 FEBRUARY 2012

KLA-T LITHOGRAPHY USERS FORUM 2012

© IMEC 2012

MOORE’S LAW CONTINUING NEW DRIVERS

K. RONSE - KLA-T LUF 2012 2

Materials Enabled Scaling

Litho Enabled Scaling

~ 16-14 nm ~ 90 nm

3D Enabled Scaling

Patterning Enabled Scaling

“PATTERNING”, Films (deposition) Lithography Dry etch

© IMEC 2012

MOORE’S LAW CONTINUING NEW DRIVERS


Materials Enabled Scaling

Litho Enabled Scaling

~ 16-14 nm ~ 90 nm

3D Enabled Scaling

Patterning Enabled Scaling

“PATTERNING”, Films (deposition) Lithography Dry etch

© IMEC 2012

GEOMETRICAL SCALING BASED ON 3 CORNER STONES

Layout

Advanced Patterning

4

Scanner enhancements

K. RONSE - KLA-T LUF 2012

© IMEC 2012


Layout

Advanced Patterning

DR compliancy Design decomposition Computational litho (SMO, ...)

5



© IMEC 2012


Layout

Advanced Patterning Scanner enhancements New Scanner ‘Knobs’

Flexray, Flexwave, ... CDU/OVL control

Multiple patterning LPLE, LELE, SADP, DSA Complementary (insertion of EUV)

6 K. RONSE - KLA-T LUF 2012

© IMEC 2012


Layout

Advanced Patterning Multiple patterning LPLE, LELE, SADP, DSA Complementary (insertion of EUV)

7



© IMEC 2012

OUTLINE

Introduction

Advanced patterning

Layout trends in advanced logic (incl. SRAM)

EUV lithography status and insertion

Scaling limited by overlay ?

Summary and conclusions


© IMEC 2012

SPACER DEFINED PATTERNING SELF ALIGNED DOUBLE PATTERNING - SADP

Potential Process flow

▸ Advantages ; - Frequency doubling - Precise CD control (linked to film thickness) - Improved LER - Self-alignment - Potential to repeat : SAQP (quadruple spacer)

▸ Challenges : - Complex patterning stack requiring

multiple deposition and etch steps (CoO) - Precise dose control (pitch-walking) - Requires at least 1 and often 2 additional

litho steps : cut mask / pad mask

▸ Application : - 1. Flash memory - 2. Advanced logic (FIN, gate, ...) - 3. DRAM ???


Source : www.itrs.net

Paper 8326-12 Alexander Miloslavsky et al, Tue 14.00

© IMEC 2012 K. RONSE - KLA-T LUF 2012 10

15 nm

Self aligned double pattering with EUV litho

© IMEC 2012

DIRECTED SELF-ASSEMBLY THE SUCCESSOR OF SADP ?


▸ Principle Self-Assembly - Block co-polymers can give microscopic

phase separation

▸ Directed self-assembly (DSA) : guiding patterns

- Topographical guiding : grapho-epitaxy

- Chemical guiding : chemo-epitaxy

Paper 8325-16 Mark H. Somervell et al, Tue 9.40am

© IMEC 2012

-OH brush grafting BCP annealing PMMA removal

X-PS cross-linking O2 etching Pattern the PR PR strip with solvent

A DSA PROCESS FLOW EXAMPLE UW FLOW (CHEMO-EPITAXY)

12 K. RONSE - KLA-T LUF 2012 Paper 8323-12 Paulina A. Rincon Delgadillo et al, Tue 11.40am

© IMEC 2012

DIRECTED SELF-ASSEMBLY

▸ Potential power : - Frequency multiplication (x N : extention of SADP) - Pattern “healing” (e.g. contact hole local CD variation)

▸ Key questions to be answered :

- Material purity for IC processing (“from lab to fab”) - Process flow and material stability and control (process windows) - Resolution, defect density – pattern fidelity


60nm 29nm

Source : Joy Cheng et al, IBM, Miami 2011

© IMEC 2012

OUTLINE

Introduction

Advanced patterning

Layout trends in adv. logic (incl. SRAM)





© IMEC 2012

LOCAL INTERCONNECT EXTRA LAYERS IN-BETWEEN TRADITIONAL FRONT- AND BACK-END

15

Active STI

Metal1 Contact Poly

Without LI

Active STI

Metal1 Via0 LI2 LI1 Poly

With LI

Simple example: one Active and one gate contact

Why LI?: • Offers advantages in electrical

performance & reliability, cell-routability and litho printability ⇒ generally adopted from 20 nm node onwards

An approach using 2 LI layers seems to be adopted in the industry

• But: no industry standard on how exactly to implement

• The introduction of LI completely changes the layout of Logic & SRAM cells

• LI eases the printability of back-end layers (esp. Metal; contacts become trenches)

• Contact is replaced by 4* (critical) layers

*LI1, LI2A, LI2B and Via0 K. RONSE - KLA-T LUF 2012

© IMEC 2012

SRAM LAYOUT: IMPACT OF USING LI PLANAR TYPE OF DEVICE (I.E. NOT FINFET)

16

wit

hout

LI

Dua

l-lay

er L

I

Active – Gate - LI1 LI2A - LI2B Via1 – Metal2 Via0 – Metal1

Metal1: cannot be printed any more beyond 28 nm node

All layer-layouts (except Front-End) are very different

Via2 – Metal3


© IMEC 2012

LOGIC-CELL LAYOUT: IMPACT OF USING LI EXAMPLE: XOR, METAL1 LAYER

17

High Metal1 density Severe Splitting conflicts ⇒

• Multiple (>2) patterning (), or • Re-layout (with area increase)

without LI Dual-layer LI

Reduced Metal1 density Pattern splitting = easier


© IMEC 2012

OUTLINE

Introduction

Advanced patterning






© IMEC 2012 19

EUV FOCUS AREAS 2007-2011: 22 NM HALF-PITCH INSERTION TARGET

2007 / 22hp 2008 / 22hp 2009 / 22hp 2010 / 22hp 2011 / 22hp 1. Reliable high power

source & collector module

1. Long-term source operation with 100 W at IF and 5MJ/day

1. Mask yield & defect inspection/review infrastructure


1. Long-term reliable source operation with 200 W at IF*

2. Resist resolution, sensitivity & LER met simultaneously

2. Defect free masks through lifecycle & inspection/review infrastructure

2. Long-term reliable source operation with 200 W at IF

1. Long-term reliable source operation with 200 W at IF


3. Availability of defect free mask





4. Reticle protection

during storage, handling and use

• Reticle protection during storage, handling and use

• EUVL manufacturing integration



5. Projection and illuminator optics quality & lifetime

• Projection / illuminator optics and mask lifetime

HVM introduction in late 2013 if productivity challenge can be met 2011 EUVL Symposium

© IMEC 2012

ASML NXE:3100 AT IMEC 0.25NA FULL FIELD EUV SCANNER

ASML NXE:3100 interfaced to TEL Lithius Pro EUV and equipped with Ushio DPP source


© IMEC 2012

NXE:3100 CHAMPION RESOLUTION 16NM HALF PITCH RESOLVED

30°Dipole σ 0.8/0.7

33mJ/cm2

18nm hp 17.5nm hp 17nm hp 16nm hp

21 K. RONSE - KLA-T LUF 2012 8322-54,Tom Wallow et al, Thu 9.30am

© IMEC 2012

EUV RESIST STATUS RLS TRIANGLE FOR 25NM L/S ON NXE:3100

Sensitivity (mJ/cm2)

LER (nm)

NXE Target for 25nm LS

dipole 5

10

15

20

25

2 2.5 3 3.5 4 4.5 5

40nm FT 50nm FT


LER is the biggest issue to meet the specs

© IMEC 2012

LWR REDUCTION BY POST-PROCESSING (SMOOTHING MODULE ON TEL LITHIUS PRO )

3sigma LWR 17% (high/mid range spatial frequency)

23

LWR= 5.7nm LWR=4.7nm

Post-Litho Post-Smoothing

K. RONSE - KLA-T LUF 2012 8322-77 Hideo Shite et al, Thu 18.00-20.00

© IMEC 2012

LWR REDUCTION BY DRY ETCH PRE-PLASMA TREATMENT

Post-Litho

Post-Etch

3sigma LWR and LER improved by 30%

2.5

3

3.5

4

4.5

5

5.5

EUVL Exp

H2 PPT Encap ULE HMO Si-Et Si Et (Opt)

LWR

and

LER

(nm

)

LWR

LER

24 K. RONSE - KLA-T LUF 2012 8328-19 Efrain Altamirano-Sánchez et al,Tue.15.30

© IMEC 2012

NXE:3100 OFF-AXIS ILLUMINATION 27NM DENSE CONTACT HOLES

Conventional

Quasar

19% EL 320nm DOF

14% EL 240nm DOF

Biggest issue is local CD variation 25 K. RONSE - KLA-T LUF 2012 8322-21 Roel Gronheid et al, Tue 14.50

© IMEC 2012

OTHER RESIST/PROCESS ISSUES

▸ Outgassing

▸ Pattern collapse ▸ Process defectivity

▸ ...

Important engineering work but no fundamental show stoppers


8322-50 James H. Underwood et al, Wed 17.40

8325-27 Gustaf Winroth et al, Tue 17.20

© IMEC 2012

EUV MASKS DEFECTIVITY KEY CONCERN

▸ Multilayer defects (ML) - Substrate / blank

▸ No pellicle : - reticle handling in fab to avoid particle adders (EUV PODS)

▸ Defect repair - Successful repair on EUV absorber defects demonstrated by

Zeiss (also compensation repair on some ML defects)

▸ Defect inspection : - Actinic blank inspection under development (EIDEC) - EUV AIMS under development (Zeiss – EMI) - Performance of today’s state-of-the-art inspection tools

K. RONSE - KLA-T LUF 2012 27 8322-11 Markus Waiblinger et al,Tue.9.00

© IMEC 2012 28 © IMEC 2012

COMPARISON PATTERNED EUV MASK VS WAFER DEFECT INSPECTION PROGRAMMED DEFECTS

Defect design

Image on mask

KT Teron PMI capture rate

Image after nitride etch

KT 2835 WI capture rate (nitr. etch)

detected

capture rate <90%

not detected

• Wafer(1X): programmed defects confirm ~20nm protrusion is about detection limit

• Mask (4X): detection limit can go beyond printing defects (for absorber defects)

40nm 36nm 32nm 30nm 28nm 26nm 24nm 22nm 20nm 18nm 16nm 14nm

K. RONSE - KLA-T LUF 2012 8324-20 Dieter Van den Heuvel et al,Tue.13.30

© IMEC 2012

EUV INSERTION OPPORTUNITIES


▸ EUV insertion mainly in BEOL (contacts, trenches) rather than FEOL - Very high resolution long FINs and gates can be nicely

patterned using 193i with SADP - The benefit of EUV has to come from its intrinsically

higher resolution for printing holes, trenches, high resolution cuts...

© IMEC 2012

EXAMPLE : PV BAND SIMULATIONS 14NM HIGH DENSITY SRAM LI1


LI1: SP LI1-Fill: SP LI1-Fill: DP

EU

V

193i

LI1 target

Pitch: about 60 nm Smallest gap: 25 nm

Fin Gate IM1

X

MEF

© IMEC 2012

EUV INSERTION OPPORTUNITIES


▸ EUV insertion mainly in BEOL (contacts, trenches) rather than FEOL - Very high resolution long FINs and gates can be nicely

patterned using 193i with SADP - The benefit of EUV has to come from its intrinsically

higher resolution for printing holes, trenches, high resolution cuts...

▸ These benefits become visible at the 14nm logic node - The gain is in number of masks... - On the condition that the overlay to193i is good enough

© IMEC 2012

Wafer clamping (e-chuck)

Reticle (clamp) flatness (e-chuck)


MAIN EUV-SPECIFIC SCANNER CONTRIBUTIONS TO OVERLAY – AS LEARNT FROM ADT

CONTRIBUTION

Reticle (clamp) flatness (e-chuck + non-telecentricity)

Vacuum purge chamber and thermal stability

EFFECT ON OVERLAY

Wafer grid stability

Intrafield distortion

Wafer grid and intrafield stability

e-chuck = electrostatic chuck

© IMEC 2012

KLA-TENCOR SCANNERTEMP SOLUTION - SCANNER TEMPERATURE MONITORING

▸ To investigate thermal behavior, the wireless ScannerTemp wafer from KLA-Tencor is used

▸ Wafer temperature stability and uniformity is measured during exposure sequence

Non-contact BaseStation

ScannerTemp wafer (Sensarray wafer)


© IMEC 2012

THERMAL BEHAVIOR OF FIRST WAFER


Wafer temperature stable before and during “exposure” of a first wafer on NXE:3100: no large wafer expansion difference expected

1. Wafer exposure preparation 2. Wafer exposure

= wafer alignment

1 2

8322-1 Jan V. Hermans et al, Mon 13.30

© IMEC 2012

IMPACT OF THERMAL BEHAVIOR ON FIRST WAFER


-0.200

-0.150

-0.100

-0.050

0.000

0.050

0.100

0.150

0.200

0 1 2 3 4 5 6

Scal

ing

(ppm

)

Wafer #

Scaling X (ppm) Scaling Y (ppm)

No clear first wafer effect on wafer scaling on NXE:3100 due to improved thermal stability

ADT

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

0 1 2 3 4 5 6

Scal

ing

(ppm

)Wafer #

Scaling X (ppm) Scaling Y (ppm)

NXE:3100, Single chuck mode, Chuck 2

© IMEC 2012

XT:1900GI TO NXE:3100 – EXPECTED VS MEASURED PERFORMANCE USING ALL THE TOOLS AND ENHANCEMENTS AVAILABLE TODAY (HIGH ORDER GRID AND INTRAFIELD CORRECTIONS)

37

3σ: X = 6.0nm, Y = 5.6nm.

freq

uenc

y

Measured

3σ: X = 5.6nm, Y = 5.5nm.

freq

uenc

y

Expected

8326-22 David Laidler et al, Wed.8.20 K. RONSE - KLA-T LUF 2012

© IMEC 2012

XT:1900GI TO NXE:3100 – EXPECTED VS MEASURED PERFORMANCE USING ALL THE TOOLS AND ENHANCEMENTS AVAILABLE TODAY

38

3σ: X = 6.0nm, Y = 5.6nm.

freq

uenc

y

Measured

8326-22 David Laidler et al, Wed.8.20 K. RONSE - KLA-T LUF 2012

© IMEC 2012

OVERLAY REQUIREMENTS LOCAL INTERCONNECT LI1 TO GATE

▸ Challenge : LI1 should not contact the gate : - Narrow trench width ! - Alignment budget becomes very thight !

node 20nm 14nmP_Gate 82 58Poly_L 24 20Smin 5 5LI1_L 26 18

OV < 11 539 K. RONSE - KLA-T LUF 2012

© IMEC 2012

SELF-ALIGNED PROCESSES PRINCIPLE


Non-self-aligned

• Litho target trench-widths can be ‘larger’ (~P_Gate/2) • Self-aligned ⇒ no impact of LI1-Gate overlay errors

• Process : difficult (find the materials with the right etch selectivities

Self-aligned: • LI1-mask: trench >> intended LI1 width • Spacer requirement: high etch selectivity

© IMEC 2012

SUMMARY AND CONCLUSIONS

▸ IC scaling continues to follow Moore’s law

▸ Advanced patterning techniques have become the main driver for geometrical scaling in 193 immersion

▸ Layout optimization and design for manufacturability are key requirements

▸ EUV momentum continues but source power and reliability remain the most critical focus item

▸ Overlay budgets are getting extremely tight and require clever process solutions

▸ 193nm immersion and EUVL are the key technologies for volume production of the next technology nodes


© IMEC 2012

SUMMARY AND CONCLUSIONS/2

▸ Alternative lithographies like e-beam direct write are behind in terms of momentum but may find their own niche markets (e.g. fast prototyping, advanced mask writing, ...) - Interesting progress has been reported with KLA-T REBL


© IMEC 2012

ACKNOWLEDGMENTS ▸ KLA-T ▸ Lithography and Patterning teams at imec ▸ Special thanks for input to this presentation :

- Peter De Bisschop - Mieke Goethals - Roel Gronheid - Vincent Wiaux - Jan Hermans - Dieter Van Den Heuvel - David Laidler - Eric Hendrickx - Shaunee Cheng - Geert Vandenberghe - Steven Demuynck - ....


© IMEC 2012

ADVANCED LITHOGRAPHY PROGRAM PARTNERS Eq

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kronse kt luf2012 final

Documents

ronse kla

d enabled scaling patterning

scaling litho

geometrical scaling

insertion scaling

euv litho imec

klat lithography users

complex patterning stack