ks note power sequence
DESCRIPTION
KS NOTE Power Sequence. NDK100 : Jimmy Chen. KS Note Block Diagram. H8. Power Block Diagram. 2. VCCXM_ON. 8. 1. VCCXA_ON. POWER. M_ON. TSURUMA. PWR_SW. A_ON. VCCXB_ON. 7. PMH7. B_ON. 5. 3. MPWRGD. BPWRGD. 9. 6. 4. PCI DEVICE. SLP_S3 . SLP_S4. PWR_SW_H8. 13. - PowerPoint PPT PresentationTRANSCRIPT
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KS NOTE Power Sequence
NDK100 : Jimmy Chen
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KS Note Block Diagram
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Power Block Diagram
H8
PMH7
SB
ADP
3207
NB
PCI DEVICE
POWERTSURUMAPWR_SW
M_ON
A_ON
B_ON
VCCXM_ON
VCCXA_ON
VCCXB_ON
MPWRGDBPWRGD
BPWRGD
PWR_SW_H8
PLTRST
PCIRST
CPU_PWRGD (BPWRGDX VR_PWRGD)
VCCCPUCORE
VR_PWRGDCPURST
SLP_S3 . SLP_S4
CPU
1
2
8
4
11
10
9
7
6
5
12
13
14
3
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Power sequence Table-1
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Power sequence Table-2
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DOCK-PWR19-F U12 pin 1,2,3 U12 pin 1,2,3
VREGIN19 DOCK-PWR19-F=> D41 pin3 D41 pin3
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VREGIN19 DOCK-PWR19-F=> D41 pin3 D41 pin3
VCC3SW Output from U74 pin 59 C440 pin1
CV19 DOCK-PWR19-F => U12 Pin5,6,7,8 U12 Pin5,6,7,8
VINT19 CV19 => U13 pin 5,6,7,8 U13 pin 5,6,7,8
EXTPWR_PMH to detect AC R411 pin 2
VREGIN19U74
VCC3SW
因此只要 power VREGIN19 supply to U74 , 無須控制信號U74 產生 VCC3SW
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EXTPWR_PMHU72
M1_ON
M2_ON
AUXON
Control Signal EXTPWR_PMH be sent to U72 , 然后產生 Control Signal M1_ON/M2_ON/AUX_ON
PWH7
EXTPWR_PMH to detect AC R411 pin 2
M1_ON Output from PWH7 pin76 to enable M power R469 pin1
M2_ON Output from PWH7 pin43 R435 pin1
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這里順便了解一下 PWH Control Signal Sequence
(1) System detect EXTPWR OK then generate M_ON & AUX_ON (2) System detect PWRSTWITCH OK then generate A_ON &B_ON ,也就是說﹕ System generate M_ON & AUX_ON before pressing power button System generate A_ON & B_ON after pressing power button
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M1_ON Output from PWH7 pin76 to enable M power R469 pin1
VCC3M_ON M1_ON => VCC3M_ON R480 pin2
VCC5M_ON M1_ON => VCC5M_ON R469 pin2
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VCC3M_ON M1_ON => VCC3M_ON R480 pin2
VCC3M output from U58 pin 15 TC4 pin1
VCC2R5M VCC3M=>VCC2R5M C366 pin1
VCC5M_ON M1_ON => VCC5M_ON R469 pin2
VCC5M output from U58 pin 27 TC13 pin1
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VCC3M output from U58 pin 15 TC4 pin1
VCC5M output from U58 pin 27 TC13 pin1
MPWRG Output from U74 pin 51 to detect M power OK R479 pin2
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M2_ON Output from PWH7 pin43 R435 pin1
VCC1R5M_ON M2_ON => VCC1R5M_ON R435 pin2
VCC1R5M Output from U57 pin15 TC17 pin1
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VCC3M output from U58 pin 15 TC4 pin1
VCC5M output from U58 pin 27 TC13 pin1
MPWRG Output from U74 pin 51 to detect M power OK R479 pin2
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AUX_ON Output from PWH7 pin88 to enable AUX power R367 pin1
VCC1R2AUX_ON AUX_ON => VCC1R2AUX_ON R367 pin2
VCC3AUX_ON AUX_ON => VCC3AUX_ON R365 pin2
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AUX_ON Output from PWH7 pin88 to enable AUX power R367 pin1
VCC1R2AUX_ON AUX_ON => VCC1R2AUX_ON R367 pin2
VCC1R2AUX VCC1R5M=>VCC1R2AUX C464 pin1
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VCC3AUX_ON AUX_ON => VCC3AUX_ON R365 pin2
VCC3AUX VCC3M => VCC3AUX Q49 pin2
VCC2R5AUX VCC3M=>VCC2R5M=>VCC2R5AUX C472pin1
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MPWRG Output from U74 pin 51 to detect M power OK R479 pin2
ICH_SLP_S3# Output from ICH7 U72 pin20
ICH_SLP_S4# Output from ICH7 U72 pin74
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PWRSWITCH# press power button , output from CN3 pin19 D10 pin 1
PM_SLP_S3# Output from PWH7 Q59 pin3
PM_SLP_S4# Output from PWH7 U72 pin 72
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PWRSWITCH# press power button , output from CN3 pin19 D10 pin 1
A1_ON Output from PWH7 R436 pin1
B1_ON Output from PWH7 R475 pin1
B2_ON Output from PWH7 D2 pin2
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A1_ON Output from PWH7 R436 pin1
VCC1R8A_ON A1_ON=>VCC1R8A_ON R426 pin2
VCC1R8A VCC5M=>VCC1R8A C195 pin1
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B1_ON Output from PWH7 R475 pin1
B_ON B1_ON=> B_ON R490 pin2
VCC0R9B_ON B1_ON=>VCC0R9B_ON R491 pin2
VCC1R05B_ON B1_ON=>VCC1R05B_ON R475 pin2
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B_ON B1_ON=> B_ON R490 pin2
VCC3B VCC3M=>VCC3B Q67 pin4
VCC5B VCC5M=>VCC5B Q52 pin4
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B_ON B1_ON=> B_ON R490 pin2
VCC0R9B_ON B1_ON=>VCC0R9B_ON R491 pin2
VCC0R9B VCC5M=>VCC0R9B C197 pin1
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B_ON B1_ON=> B_ON R490 pin2
VCC1R05B_ON B1_ON=>VCC1R05B_ON R475 pin2
VCC1R05B VCC5M=>VCC1R05B C239 pin2
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B_ON B1_ON=> B_ON R490 pin2
VCC1R5B VCC1R5M=>VCC1R5B U60 pin1,2,3
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B2_ON Output from PWH7 D2 pin2
VCCCPUCORE Output from U44 C105 pin 1
VR_PWRGD Detect VCCCPUCORE R175 pin1
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VR_PWRGD Detect VCCCPUCORE R175 pin1
BPWRG(PWROK) Detect B power U74 pin50
CPUPWRGD VR_PWRGD & BPWRG R82 pin2
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CPUPWRGD VR_PWRGD & BPWRG R82 pin2
PCIRST# output from ICH7 to reset the device that reset on PCI bus R696 pin 2
CPURST# output from NB to enable CPU R70 pin2