ks57c0002

7/28/2019 KS57C0002

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GS MSUNKS57C0002/00044-BIT CMOS Microcontroller

Product Specification

2–1

OVERVIEW

The KS57C0002/0004 single-chip CMOS microcontroller is designed for high-performance using Samsung'snewest 4-bit CPU core. With a four-channel comparator, eight LED direct drive pins, serial I/O interface, and aversatile8-bit timer/countkxcellent design solution for a variety of general-purpose applications.

Up to 24 pins of the 30-pin SDIP package can be dedicated to I/O. Five vectored interrupts provide fast responseto internal and external events. In addition, the KS57C0002/0004's advanced CMOS technology ensures lowpower consumption and a wide operating voltage range.

FEATURES

Memory

• 256 × 4-bit data memory(KS57C0002)512 × 4-bit data memory(KS57C0004)

• 2048 × 8-bit program memory(KS57C0002)4096 × 8-bit program memory(KS57C0004)

24 I/O Pins

• I/O: 18 pins, including 8 high-current pins

• Input only: 6 pins

Comparator

• 4-channel mode with internalreference (4-bit resolution)and 16-step variablereference voltage

• 3-channel mode with externalreference

• 150 mV resolution (minimum)

8-Bit Basic Timer

• Programmable interval timer

8-Bit Timer/Counter

• Programmable interval timer

• External event counterfunction

• Timer/counter clock output toTCLO0 pin

Watch Timer

• Interval generation: 0.5 s,3.9ms at 32768 Hz

• Four frequency outputs to theBUZ pin

8-Bit Serial I/O Interface

• 8-bit transmit/receive mode

• 8-bit receive-only mode

• LSB-first or MSB-firsttransmission selectable

• Internal or external clocksource

Bit Sequential Carrier

• Support for 16-bit serial datatransfer in arbitrary format

Interrupts

• Two external interrupt vectors

• Three internal interruptvectors

• Two quasi-interrupts

Memory-Mapped I/O Structure

• Data memory bank 15

Power-Down Modes

• Idle mode (only CPU clockstops)

• Stop mode (system clockstops)

Oscillation Sources

• Crystal, ceramic, or RC forsystem clock (RC is only forthe KS57C0002)

• Crystal, ceramic: 4.19 MHz(typical)

• RC: 1 MHz

• CPU clock divider circuit(by 4, 8, or 64)

Instruction Execution Times

• 0.95, 1.91, 15.3 µs at 4.19MHz

Operating Temperature

• – 40 °C to 85 °C

Operating Voltage Range

• 2.7 V to 6.0 V

Package Type

• 30 SDIP, 32 SOP

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KS57C0002 /0004 MICROCONTROLLER PRODUCT SPECIFICATION

September 1996 2–2

GELECTRONICS

S MSUN GS MSUN

P3.0 / TCL0

P3.1 / TCLO0

P3.2 / CLO

BASIC

TIMER

ARITHMETIC

LOGIC UNIT

INTERRUPT

CONTROL

BLOCK

STACK

POINTER

PROGRAM

COUNTER

PROGRAM

STATUS

WORD

I/O PORT 0P0.0 / S S C C K K

P0.1 / SO

P0.2 / SI

256 / 512

x 4-BIT

DATA

MEMORY

SERIAL

I/O

PORT

WATCH

TIMER

2 K/ 4 K

BYTE

PROGRAM

MEMORY

8-BIT

TIMER/

COUNTER

FLAGS

INSTRUCTION

DECODER

CLOCK

R

R E

E S

S E

E T

T Xin Xout

INTERNAL

INTERRUPTS

I/O PORT 4

I/O PORT 5

P4.0–P4.3

P5.0–P5.3

I/O PORT 6

P6.0 / KS0

P6.1 / KS1

P6.2 / KS2

P6.3 / BUZ COMPARATOR

INPUT

PORT 1

INPUTPORT 2

I/O PORT 3

P1.0 / INT0

P1.1 / INT1

P2.0 / CIN0

P2.1 / CIN1P2.2 / CIN2

P2.3 / CIN3

a

Figure 1. KS57C0002/0004 Block Diagram

VDD

P6.3 / BUZ

P6.2 / KS2

P6.1 / KS1

P6.0 / KS0

P5.3

P5.2

P5.1

P5.0

P4.3

P4.2

P4.1

P4.0

Xout

Xin

30

29

28

27

26

25

24

23

22

2120

19

18

17

16

1

2

3

4

5

6

7

8

9

1011

12

13

14

15

KS57C0002/04(Top View)

P0.0 / S S

C C

K K

P0.1 / SO

P0.2 / SI

P1.0 / INT0

P1.1 / INT1

P2.0 / CIN0

P2.1 / CIN1

P2.2 / CIN2

P2.3 / CIN3

P3.0 / TCL0P3.1 / TCLO0

P3.2 / CLO

R R E E S S E E T T

TEST

VSS

A

30 SDIP

P0.0/ S S C C K K

P0.1/SO

P0.2/SI

P1.0/INT0

NC

P1.1/INT1

P2.0/CIN0

P2.1/CIN1

P2.2/CIN2

P2.3/CIN3P3.0/TCL0

P3.1/TCLO0

P3.2/CLO

R R E E S S E E T T

TEST

VSS

1

2

3

4

5

6

7

8

9

1011

12

13

14

15

16

KS57C0002/04(Top View)

VDD

P6.3/BUZ

P6.2/KS2

P6.1/KS1

P6.0/KS0

P5.3

P5.2

P5.1

P5.0

P4.3P4.2

NC

P4.1

P4.0

Xout

Xin

32

31

30

29

28

27

26

25

24

2322

21

20

19

18

17

32 SOP

Figure 2. KS57C0002/0004 Pin Assignments (32 SOP, 30 SDIP)

7/28/2019 KS57C0002


PRODUCT SPECIFICATION KS57C0002 /0004 MICROCONTROLLER

GELECTRONICS

S MSUN GS MSUN2–3 September 1996

Table 1. KS57C0002/0004 Pin Descriptions

Pin Name Pin Type Description Number Share Pin

P0.0P0.1P0.2

I/O 3-bit I/O port. 1-bit or 3-bit read/write and test ispossible. Pull-up resistors are assignable to input pinsby software and are automatically disabled for outputpins. Pins are individually configurable as input oroutput.

123

S

S C

C K

KSOSI

P1.0P1.1

I 2-bit input port. 1-bit or 2-bit read and test is possible.Pull-up resistors are assignable by software.

45

INT0INT1

P2.0–P2.3 I 4-bit input port. 1-bit or 4-bit read and test is possible. 6–9 CIN0–CIN3

P3.0P3.1P3.2

I/O Same as port 0 101112

TCL0TCLO0CLO

P4.0–P4.3

P5.0–P5.3

I/O 4-bit I/O ports.

1-, 4-, or 8-bit read/write and test is possible.Pins are individually configurable as input or output.Ports can be configurable as n-channel open-drain bymask option (maximum 9V).

18–21

22–25

—

P6.0P6.1P6.2P6.3

I/O 4-bit I/O port.1-bit or 4-bit read/write and test is possible.Pull-up resistors are assignable to input pins bysoftware and are automatically disabled for outputpins. Pins individually configurable as input or output.

26272829

KS0KS1KS2BUZ

INT0 I External interrupts with rising/falling edge detection 4 P1.0

INT1 I External interrupts with rising/falling edge detection 5 P1.1

CIN0–CIN3 I 4-channel comparator input.CIN0–CIN2: comparator input only.CIN3: comparator input or external reference input

6–9 P2.0–P2.3

S S C C K K I/O Serial interface clock signal 1 P0.0

SO I/O Serial data output 2 P0.1

SI I/O Serial data input 3 P0.2

TCL0 I/O External clock input for timer/counter 10 P3.0

TCLO0 I/O Timer/counter clock output 11 P3.1

CLO I/O CPU clock output 12 P3.2

BUZ I/O 2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at

4.19 MHz for buzzer sound

29 P6.3

KS0–KS2 I/O Quasi-interrupt input with falling edge detection 26–28 P6.0–P6.2

VDD — Main power supply 30 —

VSS — Ground 15 —

R R

E E

S S

E E

T T I Reset signal 13 —

TEST I Test signal input (must be connected to VSS) 14 —

Xin, Xout — Crystal, ceramic, or RC oscillator signal for systemclock

16, 17 —

7/28/2019 KS57C0002


KS57C0002 /0004 MICROCONTROLLER PRODUCT SPECIFICATION

September 1996 2–4

GELECTRONICS

S MSUN GS MSUN

Table 2. Supplemental KS57C0002/0004 Pin Data

Pin Numbers Pin Names Share Pins I/O Type Reset Value Circuit Type

1, 2, 3 P0.0–P0.2 S

S C

C K

K, SO, SI I/O Input 54, 5 P1.0, P1.1 INT0, INT1 I Input 3

6–9 P2.0–P2.3 CIN0–CIN3 I Input 6, 8 *

10–12 P3.0–P3.2 TCL0, TCLO0, CLO I/O Input 5

13 R R

E E

S S

E E

T T — I — 9

14 TEST — — I — —

15 VSS — — — —

16, 17 Xin, Xout — — — —

18–21 P4.0–P4.3 — I/O Input 7

22–25 P5.0–P5.3 — I/O Input 7

26–29 P6.0–P6.3 KS0, KS1, KS2,BUZ

I/O Input 5

30 VDD — — — —

* I/O circuit type 8 is for P2.3 only.

ks57c0002

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