L0 RICH TriggerFirmware Status

Cristiano Santoni

Università degli studi di PerugiaINFN - Sezione di Perugia

Collaboration meeting 18/12/2013

Tasks performed during the dry run

• RICH trigger firmware integration in the TEL62 framework (thanks to Pisa for the support)

• Simulation in Modelsim of the firmware (SL plus one PP) using standard testbench available on SVN (used for the simulation of the “generic” version of the firmware)

• Test of the firmware loaded in a TEL62 pulsed by a patti

RICH Trigger Firmware

HITSFROMTDCB

FINE TIME TO GLOBAL

TIME

HITS SORTING

CLUSTERS FINDER

PRIMITIVES MERGER

PP SL

PP

PP

PP

PP

TEL62 ID

TO L0TP

TO THE NEXT TEL62

TO GPU

FROMPREVIOUS

TEL62

TRIGGERGENERATOR

RICH Trigger Firmware: what we have

FINE TIME TO GLOBAL

TIME

HITS SORTING

CLUSTERS FINDER

PRIMITIVES MERGER

PP SL

PP

PP

PP

PP

TEL62 ID

TO L0TP

TO THE NEXT TEL62

TO GPU

FROMPREVIOUS

TEL62

TRIGGERGENERATOR

HITSFROMTDCB

RICH Trigger Firmware: what we miss

FINE TIME TO GLOBAL

TIME

HITS SORTING

CLUSTERS FINDER

PRIMITIVES MERGER

PP SL

PP

PP

PP

PP

TEL62 ID

TO L0TP

TO THE NEXT TEL62

TO GPU

FROMPREVIOUS

TEL62

HITSFROMTDCB

TRIGGERGENERATOR

Hit Sorting

Problems with timing violations in firmware: sorting algorithm need to be improved.During tests a limit to the maximum number of hits in a 6.4 us frame was imposed (max 64 hits) to avoid timing problems, just to be sure that any error would not come from the sorting logic.

Timing problems solutions:

- To sort data coming from different TDCs independently in order to exploit parallelism

- To simplify sorting logic

- To add latency to the sorting logic

Firmware Integration

DONE:

INPUT

OUTPUT

CONTROL

PP SL

TDCB outputPP-SL

communicationReset, clock, enable, …

MTP asssembler

PP-SL communication

TO DO:

• Error notification• Logging

SOFTWARE:

• TDSPY RICH version

Resource utilization: PP

Combinational ALUTs…………… 8%

Memory ALUTs.………………… <1%

Dedicated logic registers…………10%

Total block memory bits …………<1%

Resource utilization: SL

Combinational ALUTs…………… 3%

Memory ALUTs.………………… <1%

Dedicated logic registers………… 3%

Total block memory bits ………… 0%

Firmware Simulation

In the testbench, one SL plus one PP were instantiated while the others PP were simulated as not producing data (empty output fifo from the PP)

A complete TEL62 with SL and 4 PPs will be simulated soon

Firmware latency:

Biggest latency contribution comes from sorting logic: 2N clock cycle(N number of hits in a 6.4 us frame)

Additional latency is introduced also to find all the M hits in a cluster soanother contribution of M clock cycle is introduced during this step

Total latency: O(100 ns)

Primitives Generation

PRIMITIVE NUMBERFINETIM

ETIMESTAMP @ 25 ns

RESERVEDMULTIPLICITY

PRIMITIVE NUMBERFINETIM

ETIMESTAMP @ 25 ns

RESERVEDPRIMITIVE ID

Current format (debug only):

Official format:

31 16 8 0

31 16 8 0

Conclusions

The core of the L0 RICH trigger firmware was developed and tested:we were able to see primitives coming out from the TEL62 withcorrect cluster average time and multiplicity

A better integration need to be done to use all the features of theTEL62 framework

The test phase will continue in Perugia side by side with the development of new features of the algorithm

Some modules need to be improved and missing feature willbe implemented soon

Spares

Firmware test: primitives generation

Tests were done using a patti to pulse the TEL62 with the RICH version of the firmware loaded

The patti board was connected to some channels on which it periodically sends pulses

From 1 to 64 channels were pulsed during tests

The tests done with 1 to 32 channels gave correct results

For 64 channels some problems raised due to a limitation on the maximum number of words that was set exactly to 64 (so having some words from noise, the multiplicity of the primitives generated by the signal was not 64 but 63 or 62).

byROBERTOPIANDANIvalid

primiteve

valid primiteve

noise*

0x800 * 25 ns =2048 * 25 ns =

51.2 us

Firmware test: primitives generation

timestamp

timestamp* due to

unconnected channels

SORTER2

a

b

s

g

Sorting Logic (1)

• Fully synchronous• Low resources consuption• Configurable in both data width and comparison range

= MIN(a, b)

= MAX(a, b)

S2

S2

S2

S2

S2

R

S2 R

LOADINPUT

OUTPUT

Sorting Logic (2)

N to load

+N to sort

2 N