l2-armprogramming4

7/25/2019 L2-ARMProgramming4

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UCSD ECE 30 Clark Guest 2013

Programming ARMECE 30 Lect ure 2


Topics

ARM Data path

ARM Registers

ARM Modes

Arithmetic Operations

ARM Condition Codes

Comparison Operations

Move and Logic Operations

Branch Operations

Shift Options

Multiplication Operations2


ARM Datapath

AddressRegister

WriteData

Register

ReadData

Register

AddressIncrementer

MUX

RegisterBank

ALU

32 x 8Multiplier

BarrelShifter

MUX

A-bus

B-bus

PC-bus

ALU-bus

RAMMemory

Instruction Decode& Control

PC

CPU


ARM Registers and ModesUser Supervisor Abort IRQ Undefined FIQ

r0

r1

r2

r3

r4

r

r6

r

r8 r8_fiq

r9 r9_fiq

r10 r10_fiq

r11 r11_fiq

r12 r12_fiq

r13 (sp) r13_svc r13_abt r13_irq r13_undef r13_fiq

r14 (lr) r14_svc r13_abt r14_irq r14_undef r14_fiq

r15 (pc)

cpsr

NA spsr_svc spsr_abt spsr_irq spsr_undef spsr_fiq


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ARM Modes

User: Where most tasks run

FIQ: Entered on a high priority (fast) interrupt

IRQ: Entered on a low priorit y interrupt

Superv isor: Entered on reset or soft ware interrupt

Abort: Entered on memory access violation

Undef: Entered when an undefined instruction isencountered

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Example Mode Switch

User

r0

r1

r2r3

r4

r5r6

r7

r8

r9r10

r11

r12

r13r14

r15 (p c)

cpsr

FIQ

r0

r1

r2

r3

r4

r5

r6

r7

r8_fiq

r9_fiq

r10_fiq

r11_fiq

r12_fiq

r13_fiq

r14_fiq

r15 (p c)

cpsr

spsr_fiq

Interrupt

Addressof FIQ

routine


Contents of CPSRs and SPSRs

N = Negati ve result f rom ALU

Z = Zero result from ALUC = Carry ou t of ALU or shif t out of ALU

V = Overflo w from ALU

I = 1 disables IRQ

F = 1 disables FIQ

T = 0 Processor in ARM state

T = 1 Processor in Thumb state

Mode = Processor mode

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31 30 29 28 7 6 5 4 3 2 1 0

N Z C V N t sed I F T

ode


Assembly Language Basics

Assembly language has one processor operation perline

C-language: a = b + c;

Assembly language: ADD r0, r1, r2

Each assembly language line gets translate d into aone word ( 32 bits ) machine code instr uction (by

the assemble r program)

Each processor has its own assembly language, tomatch its own particular capabilities

ARM is general ly a three-operand machine

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Arithmetic Operations

General form: {}{S} Rd, Rn, Operand2

Where {} indicate an optional part, and:

is:

ADD - Rd = Rn + Operand2

ADC - Rd = Rn + Operand2 + carryBit

SUB - Rd = Rn - Operand2SBC - Rd = Rn - Operand2 + carry - 1

RSB - Rd = Operand2 - Rn

RSC - Rd = Operand2 - Rn + carry - 1

is: EQ, NE, HS, CS, LO, CC, MI, PL, VS, VC, HI,

LS, GE, LT, GT, LE, AL

Examples:

ADD r0,r1,r2 ; r0 = r1 + r2

SUBGT r3, r3, #1 ; if CPSC=GT then r3 = r3 - 1

RSBLES r4, r5, #5 ; if CPSC=LE then r4 = 5 - r5

; and set CPSC with result

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The Compilers Job: C to Assembly

C-code ARM Assembly

a = b + c; add r0, r1, r2

a = b - c; sub r0, r1, r2

a = -b + c; rsub r0, r1, r2

c = e - a; sub r2, r4, r0

b = b + e; add r1, r1, r4

a = b - 5; sub r0, r1, #5

a = 2 - b; rsub r0, r1, #2

Assume a = r0, b = r1, c = r2, etc.


The Compi ler s Job: C to Assembly (2)

C-code ARM Assembly

a = b + 2 - (c + 5)

add r1, r1, #2add r2, r2, #5sub r0, r1, r2

(note: the valuesof a, b, and c are

all changed by thiscode)

Assume a = r0, b = r1, c = r2, e tc.


Register Assignment

One important task for the compile r is to decidewhat variable name in C-code wi ll correspond wi th

what reg ister in ARM.

If there are more variables than registers (like ly),va lue s can be swappe d back and forth frommemory.

A good compiler make s assignments that require asfew memory swaps as possible.

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ARM Condi tion Codes

Very powerful and unique(?) feat ure of ARM assembly

All ARM instructions have codes

An instruction is executed only if its matches

the CPSRAlternative to branching over instruc tions ( e.g. if-then-else )

Non-executed instructions take much less time

Also, improves pipelining (explained later)

Inst ruct ions dont affec t CPSR unles s {S} is appended

Except for comparison instructions, which always affect CPSR

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Meaning of Condition Codes

Code Meaning Binary

EQ ALU result = 0 0000

NE ALU result !0 0001

HS/CS C-bit set (Carry) 0010

LO/CC C-bit clear (No carry) 0011

MI N-bit set (Negative) 0100PL N-bit clear (Non-negative) 0101

VS V-bit set (Overflow) 0110

VC V-bit clear (No overflow) 0111

HI C-bit set and Z-bit clear 1000

LS C-bit clear or Z-bit set 1001

GE N-bit = V-bit ( >= ) 1010

LT N-bit !V-bit ( < ) 1011

GT Z-bit clear and V-bit set ( > ) 1100

LE Z-bit set or N-bit !V-bit (


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Branch Instruct ions

Branch: B{} label ; Jump to label if is true

Branch with Link: BL{} label ; Used to call subroutines

Puts the current value of R15(PC) into R14(LR)

To return from subroutine: MOV pc, lr

Both instructions are limited to label addresses 32MB

which is the same as 8 million instructions

Examples:

SUBS r0, r1, r2

BEQ isZero

ADD r0, r0, #1

isZero: AND r3, r0, #255

...

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BL sub1

AND r3, r0, #255

...

sub1: SUB r0, r0, 1

MOV pc, lr


Example Program: GCD

Start

r0=r1? Stop

r0>r1?

r1=r1-r0r0=r0-r1

Y

Y N

N


Example Code

Normal Assembler

gcd: cmp r0,r1 ; reached the end?

beq stop

blt less ; if r0>r1

sub r0, r0, r1 ; subtract r1 from r0

bal gcd

less:sub r1, r1, r0 ; subtract r0 from r1

bal gcd

stop:...

ARM Conditional Assembler

gcd: cmp r0, r1 ; if r0>r1

subgt r0, r0, r1 ; subtract r1 from r0

sublt r1, r1, r0 ; subtract r0 from r1

bne gcd ; reached the end?

....

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if - else Statement

C-code ARM Assemblyif(a==b) { c = d;}c = c + 2;

CMP r0, r1 BNE lbl1 MOV r2, r3lb l1: ADD r2, r2, #2

if (a==b) { c = d;} else { c = e;}c = c + 2;

CMP r0, r1 BNE lbl2 MOV r2, r3 B lbl1lbl2: MOV r2, r4lb l1: ADD r2, r2, #2

if(a==b) { c = d; e = f;}c = c + 2;

CMP r0, r1 ; Using condi tion execu tion MOVEQ r2, r3 MOVEQ r4, r5 ADD r2, r2, #2

if (a==b) { c = d;} else { c = e;

}c = c + 2;

CMP r0, r1 ; Using condi tion execu tion MOVEQ r2, r3 MOVNE r2, r4

ADD r2, r2, #2


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Nested if - else Statement

C-code ARM Assemblyif(a != b) { if(c > d) { a = a - b;

} else { a = b - a; }} else { if( a < 0 ) { a = -a; }}c = c + 2;

CMP r0, r1

BEQ lbl1 ; Outer if cant use cond. exec. CMP r2, r3 SUBLT r0, r0, r1 ; Inner if uses cond. exec. SUBGT r0, r1, r0 ; B lbl2 ; End of outer true clauselbl1: CMP r0, #0 ; Oute r els e, inn er if RSBLT r0, r0, #0 ; Inner if uses cond. exec.lbl2: ADD r2, r2, #2


switch - case Statement

C-code ARM Assembly

switch (a) {

case 1: b = a; break;case 2: c = a; break;case 5: f = a; break;defaul t: m = a;}a = a +2;

lb l1: CMP r0, #1 BNE lbl2 MOV r1, r0

B lbl5lbl2: CMP r0, #2 BNE lbl3 MOV r2, r0 B lbl5lbl3: CMP r0, #5 BNE lbl4 MOV r5, r0 B lbl5lbl4: MOV r12, r0lbl5: ADD r0, r0, #2


while Loops

C-code ARM Assembly

whi le ( a < b ) {

a = a + a;}a = a - b;

wlp1: CMP r0, r1

BGE wlp2 ADD r0, r0, r0 B wlp1

wlp2: SUB r0, r0, r1

whi le ( a < b ) { a = a + a;}a = a - b;

; Using c ondi tio nal e xecu tio nwlp1: CMP r0, r1 ADDLT r0, r0, r0 BLT wlp1 SUB r0, r0, r1


for Loops

C-code ARM Assembly

for(a = 0; a < b; a++) { c[a] = d[a] + e[a];}b = b - 1;

MOV r0, #0fl p1: CMP r0, r1 BGE flp2 LDR r5, [r3, r0 LSL #2] LDR r6, [r4, r0 LSL #2] ADD r5, r5, r6 STR r5, [r2, r0 LSL #2] ADD r0, r0, #1 B flp1fl p2: SUB r1, r1, #1


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Shift InstructionsShift commands can be appended to other instructions

They apply to Operand2

Can shift by a fixed number of bits,

or by an amount specified in a register

Shift left = multiply by a power of two

Shift right = divide by a power of two (discard remainder)

{}{S} Rd, Rn, Operand2 { #number}

Where is:

LSL - Logical Shift Left

LSR - Logical Shift Right

ARS - Arithmetic Shift Right

ROR - Rotate Right

RRX - Rotate Right Extended

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Binary ValueCF 0

Binary Value CF0

Binary Value CF

Binary Value CF

Binary Value CF


Shift Examples

ADD r0,r1,r1,LSL#2 ; r0 = r1*5 = r1 + r1*4

; Want r2 = r3 * 105 = r3 * (16-1) * (8-1)

RSB r2,r3,r3,LSL#4 ;r2=r3*15

RSB r2,r2,r2,LSL#3 ;r2=r2*7

RSB Rd, Rn, Rn LSL#K gives Rd = Rn * (2 K- 1)

MOV Rd, Rn LSL#K gives Rd = Rn * 2K

ADD Rd, Rn, Rn LSL#K gives Rd = Rn * (2 K+ 1)

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Shifts with ConstantsArithmetic instructions have 12 bits reserved for Operand2

These bits could have been used for 0 to 4095

Instead, 8 bits are used for 0 to 255

the remaining 4 bits are used to specify ROR by 0,2,4...30

This provides constants

0,1,2,...255 ; ROR #0

0,4,8...256, 260, 264...1020 ; ROR #30 => * 22

0,16,32...1024, 1040, 1056...4080 ; ROR #28 => * 24

0,64,128...4096, 4160, 4224...16320 ; ROR #26 => * 26

Implemented as third operand to MOV

MOV r0, #57, 26 ; r0 = 57 * 232-26= 57 * 64 = 3648

Assembler will calculate for you

MOV r0, #4096 => MOV r0, #64, 26

Error reported if the value cant be generated

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Loading Full 32-bit ConstantsRecommended instruction for ANY load with constant:

LDR Rd, =constant

LDR r1, =7384

Assembler will automatically:

see if constant can be generated using MOVsee if constant can be generated using MVN

or initialize memory with constant and load from there

Be aware that 3rd option takes more run time

LDR Rd, =constant is an example of a pseudoinstruction

not an instruction that the hardware actually recognizes

but the assembler translates it into recognizable

instruction(s)

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Multiplication

MUL{}{S} Rd, Rm, Rs ; Rd = Rm * Rs

MLA{}{S} Rd, Rm, Rs, Rn ; Rd = Rm * Rs + Rn

Rd and Rm cannot be the same register

PC cannot be used for any register

Takes less time if smaller number is in Rs

M-type ARMS also provide:

UMULL{}{S} RdLo,RdHi,Rm,Rs ;Unsigned

UMLAL{}{S} RdLo,RdHi,Rm,Rs ;Unsigned,Accumulate

SMULL{}{S} RdLo, RdHi, Rm, Rs ;Signed

SMLAL{}{S} RdLo, RdHi, Rm, Rs ;Signed,Accumulate

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Review

ARM Data path

ARM Registers

ARM Modes: USR , SVC, FIQ , IRQ , ABT, UNDEF

Arithmetic OperationsARM Condition Codes, Conditional Execution

Comparison Operations

Move and Logic Operations

Branch, Branch and Link

Shift Options

Multiplication Operations

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