la-4961p tag uma rev: 1 - ldasystem.com 1.0 block diagram custom thursday, august 27, ... 2mb...
TRANSCRIPT
![Page 1: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/1.jpg)
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Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
Cover Sheet
Custom
1 54Thursday, August 27, 2009
2009/03/23 2010/03/23Compal Electronics, Inc.
Schematics Document
REV:1.0
2009-08-27
Mobile AMD S1G3 CPU with ATI
RS880M(NB) & SB710(SB) core logic
Compal confidential
![Page 2: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/2.jpg)
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Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
Block Diagram
Custom
2 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
Compal Confidential
Thermal Sensor
ADM1032
Fan conn
AMD S1G3 CPU
638-PIN uFCPGA 638
16X16
ATI RS880M
Power On/Off CKT.
DC/DC Interface CKT.
Page 4, 5, 6, 7
Page 10, 11, 12, 13, 14
Page 8, 9
Page 19, 20, 21 ,22, 23
RTC CKT.
ATI SB710
Power OK CKT.
PCI-E BUS
BANK 0, 1, 2, 3
LED CKT.
DDR2-SO-DIMM X2
A-Link Express II
4X PCI-E
TAG UMA
Page 17
Page 33
CRT
LVDS Panel
Interface
Page 16
Page 4
Page 4
Display PortPage 18
page 28
page 36
Hyper Transport Link
DDR2 800MHz 1.8V
Dual Channel
Accelerometer
ST LIS302DLTRPage 30
Page 27
Mini Card UWB
PCIE X 1Express Card 54
PCIE X1 + USB X1
WLAN CardUSB + PCIE X1
10/100/1000 LAN
RJ45 CONN
Page 26
Page 25
Page 35
Page 28Page 28
LPC BUS
TPM1.2
Page 29 page 34
Touch Pad CONN.
Int.KBD
SMSC KBC 1098
TrackPoint CONN.
SLB9635TT
SMSC Super I/O
ITE IT8305
Controller
Rico R5U230
1394 port Smart Card
Page 30
Page 28
Page 17USB x1(Camara)
SATA ODD Connector
Page 24
Page 28
2.5" SATA HDD Connector
SATA0
SATA1
MDC V1.5
Page 33
Page 24
92HD75Audio CKT
USB x2(Docking)
AMP & Audio Jack
TPA6041A
USB conn x 2(For I/O)
USB2.0
FingerPrinter VFM451
USBx1
BT Conn USB x 1
Azalia
RJ11
daughter board
WWAN USB X 1
Caspian
Page 33 Page 33
COM1 LPT( Docking ) ( Docking )
Page 29
SPI ROM2 MB
Docking CONN.
(1) PCI Express x1 channels
(2) PS/2 Interf aces
(2) USB 2.channels
(2) SATA Channels
(2) Display Port Channels
(1) Serial P ort
(1) Parallel Port
(1) Line In
(1) Line Out
(1) RJ45 (10/100/1000)
(1) V GA
(1) 2 LAN indicator LED's
(1) Power Button
(1) I2C interface
P38
Clock Generator
ICS9LPRS476EPage 15
72QFN
88E8072
daughter board
daughter board
USB ConnX2
sub BD
daughter board
Page 13
Side-Port DDR2 SDRAM
512Mbits(32Mbx16)-64MB
DDR2 400MHz
Page 27
Page 27
daughter board
Page 31
Page 31
Page 31
Page 31
Page 31 Page 31 Page 31
Page 31
Page 30
![Page 3: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/3.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
Notes List
Custom
3 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
Voltage Rails O MEANS ON X MEANS OFF
O
O
X
+0.9V
S3
+3VS
X
X
+3VALW
+5VS
S1
O
+2.5VS
+CPU_CORE_0
OO
OO
X
X X
powerplane
O
O
O
O
O
X
S5 S4/ Battery only
X X X
+B
State
+1.5VS
+1.8V
S5 S4/AC & Batterydon't exist
S5 S4/AC
+5VALW
S0
O
O
Symbol Note :
: means Digital Ground
: means Analog Ground
SERIAL
SENSORSOURCE INVERTER BATT EEPROMTHERMAL
SODIMM CLK CHIP
SMBUS Control Table
MINI CARD LCD
ADM1032
+1.8VSLayout Notes
Slot 2I / IICPU &
VSMB_CK_CLK0
SMB_CK_DAT0SB710
HDMI
SB710
G-Sensor
: Question Area Mark.(Wait check)
"*" as default BOM setting @ : means just reserve , no build 45@ : Install when 45 level Assy.CONN@:means ME part
+NB_VDDC
+VDDA11PCIEVL
+3VL
VVX X X X X X
SMB_CK_CLK1
SMB_CK_DAT1
X X X X X X X X X X
X
![Page 4: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/4.jpg)
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B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
H_CADIN1
H_CADIN0
H_CADIP3H_CADIN2H_CADIP2
H_CADIP1
H_CADIN3H_CADIP4
H_CADIN5
H_CADIN4H_CADIP5
H_CADIN6
H_CADIN8
H_CADIN7
H_CADIN9
H_CADIP8
H_CADIP6
H_CADIP7
H_CADIN10H_CADIP10
H_CADIN11H_CADIP11
H_CADIP9
H_CADIN13
H_CADIN12
H_CADIP14
H_CADIP12
H_CADIN14
H_CADIP0
H_CADIN15H_CADIP15
H_CADIP13
H_CADON15
H_CADOP13
H_CADON2
H_CADON3
H_CADON9
H_CADON6
H_CADON0
H_CADOP11
H_CADOP8
H_CADOP6
H_CADON13
H_CADOP1
H_CADOP2
H_CADOP4
H_CADOP5
H_CADON12
H_CADON7
H_CADON5
H_CADON10
H_CADON8
H_CADON4
H_CADON1
H_CADOP12
H_CADOP15
H_CADOP9
H_CADOP10
H_CADOP14
H_CADOP7
H_CADOP3
H_CADOP0
H_CADON14
H_CADON11
H_CADIN[0..15]
H_CADOP[0..15]
H_CADON[0..15]
H_CADIP[0..15]
NB_THERMAL_DANB_THERMAL_DC
FAN_PWM_R
NB_THERMAL_DC
NB_THERMAL_DA
CPU_THERMTRIP#_R
FAN_PWM_R
H_CADON[0..15] <10>H_CADIN[0..15]<10>
H_CADOP[0..15] <10>
H_CLKIN0<10>
H_CLKIN1<10>H_CLKIP1<10>
H_CTLIN1<10>
H_CLKIP0<10>
H_CTLIP1<10> H_CTLOP1 <10>
H_CLKOP1 <10>
H_CADIP[0..15]<10>
H_CLKOP0 <10>H_CLKON0 <10>
H_CLKON1 <10>
H_CTLON1 <10>
H_CTLOP0 <10>H_CTLON0 <10>H_CTLIN0<10>
H_CTLIP0<10>
SMB_CK_CLK0 <6,8,9,15,21,30>
SMB_CK_DAT0 <6,8,9,15,21,30>
NB_THERMAL_DC<11>NB_THERMAL_DA<11>
CPU_THERMTRIP#_R<6>
FAN_PWM<33>
H_PROCHOT#<6,46>
+1.2V_HT
+1.2V_HT
+3VS
+3VS
+1.2V_HT
+5VS+5VS+1.8V
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
AMD CPU S1G2 HT I/F
Custom
4 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
250 mil
VLDT=500mA
Athlon 64 S1
Processor Socket
Near CPU Socket
VLDT CAP.
9/20 SP07000DM00/SP07000EQ00
PWM Fan Controlcircuit
Thermal Sensor EMC1402
change from ADM1032 to EMC1402 12/1
change 4.7U to 10U for AMD S1G3 request. HP 12/8
for RF, HP 12/10
address: 4C
for Fan shake issue when in 70 degree. Compal 3/23
HP 3/30
C6180P_0402_50V8J
1
2
C210U_0805_10V4Z
1
2
R1 3K_0402_5%12
C
B
E
Q108
PMBT3904_SOT23
1
2
3
C8
0.1
U_
04
02
_1
6V
4Z
1
2
R534 2.2K_0402_5%
12
R556
30K_0402_5%
12
C9
2200P_0402_50V7K1 2
R557
10K_0402_5%
12
C40.22U_0603_16V4Z
1
2
U2
TC7SH00FU_SSOP5
INB1
INA2
O4
G3
P5
C10
0.1U_0402_10V6K@1 2
R471
0_0603_5%
12
C5180P_0402_50V8J
1
2
C110U_0805_10V4Z
1
2
C7 10U_0805_10V4Z
1 2
U1
EMC1402-1-ACZL-TR_MSOP8
DN3
DP2
VDD1
ALERT#6
SMCLK8
THERM#4
GND5
SMDATA7
JP1
ACES_85204-03001
conn@
11
22
33
G14
G25
C30.22U_0603_16V4Z
1
2
HT LINK
JCPU1A
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
VLDT_A3D4
VLDT_A2D3
VLDT_A1D2
VLDT_A0D1
VLDT_B3AE5
VLDT_B2AE4
VLDT_B1AE3
VLDT_B0AE2
L0_CADIN_H15N5
L0_CADIN_L15P5
L0_CADIN_H14M3
L0_CADIN_L14M4
L0_CADIN_H13L5
L0_CADIN_L13M5
L0_CADIN_H12K3
L0_CADIN_L12K4
L0_CADIN_H11H3
L0_CADIN_L11H4
L0_CADIN_H10G5
L0_CADIN_L10H5
L0_CADIN_H9F3
L0_CADIN_L9F4
L0_CADIN_H8E5
L0_CADIN_L8F5
L0_CADIN_H7N3
L0_CADIN_L7N2
L0_CADIN_H6L1
L0_CADIN_L6M1
L0_CADIN_H5L3
L0_CADIN_L5L2
L0_CADIN_H4J1
L0_CADIN_L4K1
L0_CADIN_H3G1
L0_CADIN_L3H1
L0_CADIN_H2G3
L0_CADIN_L2G2
L0_CADIN_H1E1
L0_CADIN_L1F1
L0_CADIN_H0E3
L0_CADIN_L0E2
L0_CADOUT_H15T4
L0_CADOUT_L15T3
L0_CADOUT_H14V5
L0_CADOUT_L14U5
L0_CADOUT_H13V4
L0_CADOUT_L13V3
L0_CADOUT_H12Y5
L0_CADOUT_L12W5
L0_CADOUT_H11AB5
L0_CADOUT_L11AA5
L0_CADOUT_H10AB4
L0_CADOUT_L10AB3
L0_CADOUT_H9AD5
L0_CADOUT_L9AC5
L0_CADOUT_H8AD4
L0_CADOUT_L8AD3
L0_CADOUT_H7T1
L0_CADOUT_L7R1
L0_CADOUT_H6U2
L0_CADOUT_L6U3
L0_CADOUT_H5V1
L0_CADOUT_L5U1
L0_CADOUT_H4W2
L0_CADOUT_L4W3
L0_CADOUT_H3AA2
L0_CADOUT_L3AA3
L0_CADOUT_H2AB1
L0_CADOUT_L2AA1
L0_CADOUT_H1AC2
L0_CADOUT_L1AC3
L0_CADOUT_H0AD1
L0_CADOUT_L0AC1
L0_CLKIN_H1J5
L0_CLKIN_L1K5
L0_CLKIN_H0J3
L0_CLKIN_L0J2
L0_CTLIN_H1P3
L0_CTLIN_L1P4
L0_CTLIN_H0N1
L0_CTLIN_L0P1
L0_CLKOUT_H1Y4
L0_CLKOUT_L1Y3
L0_CLKOUT_H0Y1
L0_CLKOUT_L0W1
L0_CTLOUT_H1T5
L0_CTLOUT_L1R5
L0_CTLOUT_H0R2
L0_CTLOUT_L0R3
![Page 5: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/5.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDR_B_MA10
DDR_B_MA7
DDR_B_MA1
DDR_B_MA12
DDR_B_MA6
DDR_B_MA11
DDR_B_MA0
DDR_B_MA9
DDR_B_MA15
DDR_B_MA3
DDR_B_MA5
DDR_B_MA8
DDR_B_MA13
DDR_B_MA2
DDR_B_MA4
DDR_CKE1_DIMMB
DDR_B_D0
DDR_CKE0_DIMMB
DDR_B_DQS6DDR_B_DQS#6
DDR_B_DQS2DDR_B_DQS#2
DDR_B_DQS5DDR_B_DQS#5
DDR_B_DQS1DDR_B_DQS#1
DDR_B_DQS4DDR_B_DQS#4
DDR_B_DQS0DDR_B_DQS#0
DDR_B_DQS7DDR_B_DQS#7
DDR_B_DQS3DDR_B_DQS#3
DDR_A_DQS0DDR_A_DQS#0
DDR_A_DQS3DDR_A_DQS#3
DDR_A_DQS2DDR_A_DQS#2
DDR_A_DQS1DDR_A_DQS#1
DDR_A_DQS4DDR_A_DQS#4DDR_A_DQS5DDR_A_DQS#5DDR_A_DQS6DDR_A_DQS#6
DDR_A_DQS#7DDR_A_DQS7
+MCH_REF
DDR_B_ODT0DDR_B_ODT1
DDR_A_ODT1DDR_A_ODT0
DDR_B_CLK#0DDR_B_CLK0
DDR_B_CLK1DDR_B_CLK#1DDR_A_CLK#1
DDR_A_CLK#0DDR_A_CLK0
DDR_A_CLK1
DDR_CKE0_DIMMADDR_CKE1_DIMMA
DDR_B_D28
DDR_B_D16
DDR_B_D22
DDR_B_D19
DDR_B_D9
DDR_B_D50
DDR_B_D35
DDR_B_D46
DDR_B_D5
DDR_B_D37
DDR_B_D26
DDR_B_D3
DDR_B_D8
DDR_B_D29
DDR_B_D14
DDR_B_D7
DDR_B_D59
DDR_B_D51
DDR_B_D10
DDR_B_D17
DDR_B_D44
DDR_B_D41
DDR_B_D38
DDR_B_D47
DDR_B_D63
DDR_B_D32
DDR_B_D20
DDR_B_D52
DDR_B_D30
DDR_B_D53
DDR_B_D40
DDR_B_D27
DDR_B_D45
DDR_B_D55DDR_B_D56
DDR_B_D11
DDR_B_D48
DDR_B_D39
DDR_B_D1
DDR_B_D42
DDR_B_D36
DDR_B_D2
DDR_B_D58
DDR_B_D33
DDR_B_D62
DDR_B_D31
DDR_B_D21
DDR_B_D54
DDR_B_D24
DDR_B_D15
DDR_B_D60
DDR_B_D12
DDR_B_D49
DDR_B_D43
DDR_B_D18
DDR_B_D61
DDR_B_D34
DDR_B_D4
DDR_B_DM6
DDR_B_DM4
DDR_B_DM2
DDR_B_DM0
DDR_B_DM5
DDR_B_DM3
DDR_B_DM1
DDR_B_DM7DDR_A_DM6DDR_A_DM5DDR_A_DM4DDR_A_DM3DDR_A_DM2DDR_A_DM1DDR_A_DM0
DDR_A_DM7
DDR_A_D59
DDR_A_D3
DDR_A_D13
DDR_A_D60
DDR_A_D40
DDR_A_D29
DDR_A_D56
DDR_A_D20
DDR_A_D28
DDR_A_D36
DDR_A_D19
DDR_A_D23
DDR_A_D34
DDR_A_D61
DDR_A_D15
DDR_A_D4
DDR_A_D0
DDR_A_D53
DDR_A_D47
DDR_A_D43
DDR_A_D33
DDR_A_D24
DDR_A_D39
DDR_A_D46
DDR_A_D22
DDR_A_D51
DDR_A_D9
DDR_A_D5DDR_A_D6
DDR_A_D54
DDR_A_D8
DDR_A_D31
DDR_A_D7
DDR_A_D50
DDR_A_D57
DDR_A_D12
DDR_A_D21
DDR_A_D26
DDR_A_D63DDR_A_D62
DDR_A_D42
DDR_A_D48
DDR_A_D44
DDR_A_D25
DDR_A_D58
DDR_A_D32
DDR_A_D1
DDR_A_D17
DDR_A_D2
DDR_A_D55
DDR_A_D38
DDR_A_D11DDR_A_D10
DDR_A_D27
DDR_A_D18
DDR_A_D14
DDR_A_D41
DDR_A_D49
DDR_A_D16
DDR_A_D52
DDR_A_D37
DDR_A_D35
DDR_A_D30
DDR_B_D6
DDR_A_D45
DDR_B_RAS#DDR_B_CAS#DDR_B_WE#
DDR_B_BS#0DDR_B_BS#1DDR_B_BS#2
DDR_A_WE#
DDR_B_D25
DDR_A_CAS#DDR_A_RAS#
DDR_B_D23
DDR_B_D57
DDR_B_D13
DDR_A_BS#2DDR_A_BS#1DDR_A_BS#0
DDR_A_MA15
DDR_A_MA12
DDR_A_MA14DDR_A_MA13
DDR_A_MA11DDR_A_MA10
DDR_A_MA6
DDR_A_MA1
DDR_A_MA7
DDR_A_MA2DDR_A_MA3
DDR_A_MA8
DDR_A_MA5DDR_A_MA4
DDR_A_MA9
DDR_A_MA0
DDR_B_MA14
DDR_CS1_DIMMA# DDR_CS0_DIMMB#DDR_CS1_DIMMB#
DDR_CS0_DIMMA#
+MCH_REF
MEMZPMEMZN
DDR_CKE1_DIMMB <9>DDR_CKE0_DIMMB <9>
DDR_CS0_DIMMA#<8>DDR_CS1_DIMMA#<8> DDR_CS0_DIMMB# <9>
DDR_CS1_DIMMB# <9>
DDR_B_D[63..0]<9>
DDR_B_DM[7..0]<9> DDR_A_DM[7..0] <8>
DDR_A_D[63..0] <8>
DDR_B_DQS7<9>DDR_B_DQS#7<9>
DDR_B_DQS6<9>
DDR_B_DQS5<9>
DDR_B_DQS4<9>
DDR_B_DQS3<9>
DDR_B_DQS2<9>
DDR_B_DQS1<9>
DDR_B_DQS0<9>
DDR_B_DQS#6<9>
DDR_B_DQS#5<9>
DDR_B_DQS#4<9>
DDR_B_DQS#3<9>
DDR_B_DQS#2<9>
DDR_B_DQS#1<9>
DDR_B_DQS#0<9>
DDR_A_DQS3 <8>
DDR_A_DQS2 <8>
DDR_A_DQS1 <8>
DDR_A_DQS0 <8>
DDR_A_DQS#3 <8>
DDR_A_DQS#2 <8>
DDR_A_DQS#1 <8>
DDR_A_DQS#0 <8>
DDR_A_DQS4 <8>DDR_A_DQS#4 <8>DDR_A_DQS5 <8>DDR_A_DQS#5 <8>DDR_A_DQS6 <8>DDR_A_DQS#6 <8>DDR_A_DQS7 <8>DDR_A_DQS#7 <8>
DDR_B_RAS# <9>DDR_B_CAS# <9>DDR_B_WE# <9>
DDR_B_BS#0 <9>DDR_B_BS#1 <9>DDR_B_BS#2 <9>
DDR_A_RAS#<8>DDR_A_CAS#<8>DDR_A_WE#<8>
DDR_A_BS#0<8>DDR_A_BS#1<8>DDR_A_BS#2<8>
DDR_A_MA[15..0]<8> DDR_B_MA[15..0] <9>
DDR_B_ODT0 <9>DDR_B_ODT1 <9>
DDR_A_ODT0<8>DDR_A_ODT1<8>
DDR_B_CLK0 <9>DDR_B_CLK#0 <9>DDR_B_CLK1 <9>DDR_B_CLK#1 <9>
DDR_A_CLK0<8>DDR_A_CLK#0<8>
DDR_A_CLK1<8>DDR_A_CLK#1<8>
DDR_CKE0_DIMMA<8>DDR_CKE1_DIMMA<8>
+1.8V
+0.9V+0.9V
+1.8V
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
AMD CPU S1G2 DDRII I/F
Custom
5 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
Athlon 64 S1
Processor
Socket
Athlon 64 S1
Processor Socket
Place them close to CPU within 1"
Processor DDR2 Memory Interface
9/23 HP
C12
0.1U_0402_16V4Z
1
2
R2
1K_0402_1%
12
R3
1K_0402_1%
12
R4 39.2_0402_1%
1 2
MEM:CMD/CTRL/CLK
JCPU1B
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
VTT1D10
VTT2C10
VTT3B10
VTT4AD10
VTT5W10
VTT6AC10
VTT7AB10
VTT8AA10
VTT9A10
MA1_ODT1V19
MA1_ODT0U21
MA0_ODT1V22
MA0_ODT0T19
MB1_ODT0Y26
MB0_ODT1W23
MB0_ODT0W26
RSVD_M2B18
MB1_CS_L0U22
MB0_CS_L1W25
MB0_CS_L0V26
MA0_CS_L1U19
MA1_CS_L1V20
MA1_CS_L0U20
MA0_CS_L0T20
MA_ADD15K19
MA_ADD14K24
MA_ADD13V24
MA_ADD12K20
MA_ADD11L22
MA_ADD10R21
MA_ADD9K22
MA_ADD8L19
MA_ADD7L21
MA_ADD6M24
MA_ADD5L20
MA_ADD4M22
MA_ADD3M19
MA_ADD2N22
MA_ADD1M20
MA_ADD0N21
MA_BANK2J21
MA_BANK1R23
MA_BANK0R20
MA_RAS_LR19
MA_CAS_LT22
MA_WE_LT24
MEMZPAF10
MEMZNAE10
VTT_SENSEY10
MEMVREFW17
MA_CLK_H4P19
MA_CLK_L4P20
MA_CLK_H7Y16
MA_CLK_L7AA16
MA_CLK_H1E16
MA_CLK_L1F16
MA_CLK_H5N19
MA_CLK_L5N20
MB_CLK_H4R26
MB_CLK_L4R25
MB_CLK_H7AF18
MB_CLK_L7AF17
MB_CLK_H1A17
MB_CLK_L1A18
MB_CLK_H5P22
MB_CLK_L5R22
MA_CKE0J22
MA_CKE1J20
MB_CKE0J25
MB_CKE1H26
MB_ADD15J24
MB_ADD14J23
MB_ADD13W24
MB_ADD12L25
MB_ADD11L26
MB_ADD10T26
MB_ADD9K26
MB_ADD8M26
MB_ADD7L24
MB_ADD6N25
MB_ADD5L23
MB_ADD4N26
MB_ADD3N23
MB_ADD2P26
MB_ADD1N24
MB_ADD0P24
MB_BANK2J26
MB_BANK1U26
MB_BANK0R24
MB_RAS_LU25
MB_CAS_LU24
MB_WE_LU23
RSVD_M1H16
R5 39.2_0402_1%
1 2
C13
1000P_0402_25V8J
1
2
MEM:DATAJCPU1C
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
MB_DATA63AD11
MB_DATA62AF11
MB_DATA61AF14
MB_DATA60AE14
MB_DATA59Y11
MB_DATA58AB11
MB_DATA57AC12
MB_DATA56AF13
MB_DATA55AF15
MB_DATA54AF16
MB_DATA53AC18
MB_DATA52AF19
MB_DATA51AD14
MB_DATA50AC14
MB_DATA49AE18
MB_DATA48AD18
MB_DATA47AD20
MB_DATA46AC20
MB_DATA45AF23
MB_DATA44AF24
MB_DATA43AF20
MB_DATA42AE20
MB_DATA41AD22
MB_DATA40AC22
MB_DATA39AE25
MB_DATA38AD26
MB_DATA37AA25
MB_DATA36AA26
MB_DATA35AE24
MB_DATA34AD24
MB_DATA33AA23
MB_DATA32AA24
MB_DATA31G24
MB_DATA30G23
MB_DATA29D26
MB_DATA28C26
MB_DATA27G26
MB_DATA26G25
MB_DATA25E24
MB_DATA24E23
MB_DATA23C24
MB_DATA22B24
MB_DATA21C20
MB_DATA20B20
MB_DATA19C25
MB_DATA18D24
MB_DATA17A21
MB_DATA16D20
MB_DATA15D18
MB_DATA14C18
MB_DATA13D14
MB_DATA12C14
MB_DATA11A20
MB_DATA10A19
MB_DATA9A16
MB_DATA8A15
MB_DATA7A13
MB_DATA6D12
MB_DATA5E11
MB_DATA4G11
MB_DATA3B14
MB_DATA2A14
MB_DATA1A11
MB_DATA0C11
MA_DATA63AA12
MA_DATA62AB12
MA_DATA61AA14
MA_DATA60AB14
MA_DATA59W11
MA_DATA58Y12
MA_DATA57AD13
MA_DATA56AB13
MA_DATA55AD15
MA_DATA54AB15
MA_DATA53AB17
MA_DATA52Y17
MA_DATA51Y14
MA_DATA50W14
MA_DATA49W16
MA_DATA48AD17
MA_DATA47Y18
MA_DATA46AD19
MA_DATA45AD21
MA_DATA44AB21
MA_DATA43AB18
MA_DATA42AA18
MA_DATA41AA20
MA_DATA40Y20
MA_DATA39AA22
MA_DATA38Y22
MA_DATA37W21
MA_DATA36W22
MA_DATA35AA21
MA_DATA34AB22
MA_DATA33AB24
MA_DATA32Y24
MA_DATA31H22
MA_DATA30H20
MA_DATA29E22
MA_DATA28E21
MA_DATA27J19
MA_DATA26H24
MA_DATA25F22
MA_DATA24F20
MA_DATA23C23
MA_DATA22B22
MA_DATA21F18
MA_DATA20E18
MA_DATA19E20
MA_DATA18D22
MA_DATA17C19
MA_DATA16G18
MA_DATA15G17
MA_DATA14C17
MA_DATA13F14
MA_DATA12E14
MA_DATA11H17
MA_DATA10E17
MA_DATA9E15
MA_DATA8H15
MA_DATA7E13
MA_DATA6C13
MA_DATA5H12
MA_DATA4H11
MA_DATA3G14
MA_DATA2H14
MA_DATA1F12
MA_DATA0G12
MB_DM7AD12
MB_DM6AC16
MB_DM5AE22
MB_DM4AB26
MB_DM3E25
MB_DM2A22
MB_DM1B16
MB_DM0A12
MB_DQS_H7AF12
MB_DQS_L7AE12
MB_DQS_H6AE16
MB_DQS_L6AD16
MB_DQS_H5AF21
MB_DQS_L5AF22
MB_DQS_H4AC25
MB_DQS_L4AC26
MB_DQS_H3F26
MB_DQS_L3E26
MB_DQS_H2A24
MB_DQS_L2A23
MB_DQS_H1D16
MB_DQS_L1C16
MB_DQS_H0C12
MB_DQS_L0B12
MA_DM7Y13
MA_DM6AB16
MA_DM5Y19
MA_DM4AC24
MA_DM3F24
MA_DM2E19
MA_DM1C15
MA_DM0E12
MA_DQS_H7W12
MA_DQS_L7W13
MA_DQS_H6Y15
MA_DQS_L6W15
MA_DQS_H5AB19
MA_DQS_L5AB20
MA_DQS_H4AD23
MA_DQS_L4AC23
MA_DQS_H3G22
MA_DQS_L3G21
MA_DQS_H2C22
MA_DQS_L2C21
MA_DQS_H1G16
MA_DQS_L1G15
MA_DQS_H0G13
MA_DQS_L0H13
![Page 6: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/6.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CPU_TDO
CPU_TMS
CPU_TCK
CPU_TDI
CPU_TRST#
CPU_DBREQ#
HDT_RST#LDT_RST#
CPU_VDD0_FB_L
VDD_NB_FB_HVDD_NB_FB_L
CPU_HTREF0
CPU_HTREF1
CPU_DBRDYCPU_TMS
CPU_TEST19_PLLTEST0
CPU_CLKIN_SC_P
CPU_THERMTRIP#_R
LDT_RST#
H_PWRGD_CPU
LDT_STOP#
LDT_STOP#
CPU_SIDCPU_SIC
CPU_CLKIN_SC_N
CPU_VDD0_FB_H
CPU_TDICPU_TRST#CPU_TCK
CPU_DBREQ#
CPU_TDO
CPU_SVCCPU_SVD
CPU_TEST12_SCANSHIFTENB
CPU_TEST20_SCANCLK2CPU_TEST21_SCANEN
CPU_TEST24_SCANCLK1CPU_TEST22_SCANSHIFTEN
CPU_TEST14_BP0CPU_TEST15_BP1
H_PWRGD_CPULDT_RST#
CPU_TEST27_SINGLECHAIN
CPU_TEST18_PLLTEST1CPU_VDD0_FB_HCPU_VDD0_FB_L
CPU_TEST21_SCANEN
CPU_TEST18_PLLTEST1CPU_TEST19_PLLTEST0
CPU_TEST15_BP1
CPU_TEST20_SCANCLK2
CPU_TEST22_SCANSHIFTENCPU_TEST24_SCANCLK1
CPU_SVDCPU_SVC
H_PROCHOT#
H_PROCHOT#
CPU_LDT_REQ#
CPU_THERMTRIP#_R
ALERT
ALERT
CPU_DBRDY
CPU_SMCLK
CPU_SMDATA
CPU_SIC
CPU_SID
CPU_TEST28_L_PLLCHRZ_NCPU_TEST28_H_PLLCHRZ_P
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST29_L_FBCLKOUT_NCPU_TEST29_H_FBCLKOUT_P
CPU_TEST17_BP3CPU_TEST16_BP2 CPU_SID
CPU_SIC
CPU_TEST25_H_BYPASSCLK_H
LDT_RST#
SB_PWRGD <21,33,45>
CPU_SVD <45>CPU_SVC <45>
H_PWRGD_CPU<19>
LDT_RST#<19>
LDT_STOP#<11,19>
CPU_VDD0_FB_H<45>CPU_VDD0_FB_L<45>
CLK_CPU_BCLK<15>
CLK_CPU_BCLK#<15>
CPU_LDT_REQ# <11,19>
H_THERMTRIP# <21>
H_PROCHOT# <4,46>
THERM_SC#<21>
SMB_CK_CLK0<4,8,9,15,21,30>
SMB_CK_DAT0<4,8,9,15,21,30>
VDD_NB_FB_H <45>VDD_NB_FB_L <45>
CPU_THERMTRIP#_R <4>
+1.8V
+3VS
+1.2V_HT
+2.5VDDA
+2.5VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+CPU_CORE_NB
+CPU_CORE_0
+1.8V
+1.8V
+1.8V
+1.8V
+5VS
+5VS
+3VS
+1.8V
+1.2V_HT+1.8V
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
AMD CPU S1G2 CTRL
Custom
6 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
HDT Connector
0718 Silego -- 216 ohm
Place close to CPU wihtin 1.5"
VDDA=300mA
Close to CPU
Close to CPU
AMD recommend NC 10/15
10/29 HP
11/6 HP
9/23 HP
10/29 HP
10/29 HP
10/29 HP
route as differential
as short as possible
test point under the package
10/29 HP
10/29 HP
11/6 HP
11/6 HP
11/6 HP
change from +1.8VS to +1.8V
for lekage issue HP 12/18
HP 3/30
HP 3/30
HP 4/6
HP, 6/12
R8 300_0402_5% 1 2
R30 300_0402_5%@12
R3
92
20
_0
40
2_
5%
@1
2
R26 300_0402_5%12
R1210K_0402_5%
12
SAMTEC_ASP-68200-07
JP2
2468
101214161820222423
21191715131197531
26
R490 390_0402_5%
1 2
T16PAD
Q5A
DMN66D0LDW-7_SOT363-6
61
2
T12PAD
Q4A
DMN66D0LDW-7_SOT363-6
61
2
R19
300_0402_5%
12
L1
FBM_L11_201209_300L_08051 2
R35
560_0402_5%
12
Q5B
DMN66D0LDW-7_SOT363-6
3
5
4
T17 PAD
C19 3900P_0402_50V7K 1 2
Q4B
DMN66D0LDW-7_SOT363-6
3
5
4
R572
1K_0402_1%
12
22
0_
04
02
_5
%@
R3
71
2
C170.22U_0603_16V4Z
1
2
U3
NC7SZ08P5X_NL_SC70-5
B2
A1
Y4
P5
G3
R33 300_0402_5%@12
C20 220P_0402_25V8J
1
2
R3
82
20
_0
40
2_
5%
@1
2
R15 44.2_0402_1%1 2
C154.7U_0805_10V4Z
1
2
C183900P_0402_50V7K 1 2
R11 1K_0402_5%
1 2
C7050.1U_0402_25V6
1
2
R17 10_0402_5% 1 2
R509510_0402_5%
1 2
C16
3300P_0402_50V7K
1
2
T10PAD
R141K_0402_5%
12
R24 300_0402_5%1 2
R16 10_0402_5%
1 2
R4
03
00
_0
40
2_
5%
12
R32 300_0402_5%@12
R491 390_0402_5%
1 2T11PAD
T18 PAD
T2PAD
R42
1K_0402_5%
12
22
0_
04
02
_5
%@
R3
61
2
R10 1K_0402_5%
1 2
R508 590_0402_1% @
1 2
R28 300_0402_5%@12
C21 220P_0402_25V8J
1
2
+C14100U_D2_10VM
@
1
2
T9PAD
R43
4.7K_0402_5%
12
R4
12
20
_0
40
2_
5%
@1
2
C
B
E
Q11
PMBT3904_SOT23
1
2
3
R510 300_0402_5% 1 2
R9169_0402_1%
12
R20 10_0402_5% 1 2
T1PAD
C
B
E
Q10
PMBT3904_SOT23
1
2
3
R18 10_0402_5%
1 2
R13 44.2_0402_1%1 2
JCPU1D
FOX_PZ6382A-284S-41F_GRIFFINCONN@
VDDA1F8
VDDA2F9
RESET_LB7
PWROKA7
LDTSTOP_LF10
SICAF4
SIDAF5
HT_REF1P6
HT_REF0R6
VDD0_FB_HF6
VDD0_FB_LE6
VDDIO_FB_HW9
VDDIO_FB_LY9
THERMTRIP_LAF6
PROCHOT_LAC7
RSVD2A5
LDTREQ_LC6
SVCA6
SVDA4
RSVD6C5
RSVD4B5
RSVD1A3
CLKIN_HA9
CLKIN_LA8
DBRDYG10
TMSAA9
TCKAC9
TRST_LAD9
TDIAF9
DBREQ_LE10
TDOAE9
TEST25_HE9
TEST25_LE8
TEST19G9
TEST18H10
RSVD8AA7
TEST9C2
TEST17D7
TEST16E7
TEST15F7
TEST14C7
TEST12AC8
TEST7C3
TEST6AA6
THERMDCW7
THERMDAW8
VDD1_FB_HY6
VDD1_FB_LAB6
TEST29_HC9
TEST29_LC8
TEST24AE7
TEST23AD7
TEST22AE8
TEST21AB8
TEST20AF7
TEST28_HJ7
TEST28_LH8
TEST27AF8
ALERT_LAE6
TEST10K8
TEST8C4
RSVD3B3
RSVD5C1
VDDNB_FB_HH6
VDDNB_FB_LG6
RSVD7D5
KEY2W18
MEMHOT_LAA8
RSVD10H18
RSVD9H19
KEY1M11
R489 300_0402_5%
1 2
T15PAD
R25
300_0402_5%
12
R7
680_0402_5%
1 2
R34
1.5K_0402_5%
1
2
R27 300_0402_5%12
![Page 7: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/7.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+0.9V
+CPU_CORE_0
+CPU_CORE_0
+CPU_CORE_0
+1.8V
+1.8V
+1.8V
+1.8V +1.8V
+0.9V
+0.9V
+CPU_CORE_NB
+1.8V
+1.8V
+CPU_CORE_0
+CPU_CORE_0
+CPU_CORE_0
+CPU_CORE_NB
+CPU_CORE_0+CPU_CORE_0
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
AMD CPU S1G2 PWR & GND
Custom
7 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
Between CPU Socket and DIMM
180PF Qt'y follow the distance between
CPU socket and DIMM0. <2.5inch>
Under CPU Socket
Athlon 64 S1
Processor Socket
Near CPU Socket
VTT decoupling.
VDD(+CPU_CORE) decoupling.
VDDIO decoupling.+CPU_CORE_NB decoupling.
C: Change to NBO CAP
C: Change to NBO CAP
Under CPU Socket
Near CPU Socket Right side.
Near CPU Socket Left side.
Near Power Supply
Athlon 64 S1
Processor Socket
L 18A/720mil/36vias L18A/720mil/36vias
10/6 HP
+0.8V~+1.1V, 3A
(+-25mV_dc, +-125mV_ac)
2A ,(+-100mV_dc,
+-150mV_ac)
C350.01U_0402_25V4Z
1
2
+ C22330U_X_2VM_R6M
1
2
JCPU1E
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
VDD1_25AC4
VDD1_26AD2
VDD0_1G4
VDD0_2H2
VDD0_3J9
VDD0_4J11
VDD0_5J13
VDD0_7K6
VDD0_8K10
VDD0_9K12
VDD0_10K14
VDD0_11L4
VDD0_12L7
VDD0_13L9
VDD0_14L11
VDD0_15L13
VDD0_17M2
VDD0_18M6
VDD0_19M8
VDD0_20M10
VDD0_21N7
VDD0_22N9
VDD0_23N11
VDD1_1P8
VDD1_2P10
VDD1_3R4
VDD1_4R7
VDD1_5R9
VDD1_6R11
VDD1_7T2
VDD1_8T6
VDD1_9T8
VDD1_10T10
VDD1_11T12
VDD1_12T14
VDD1_13U7
VDD1_14U9
VDD1_15U11
VDD1_16U13
VDD1_18V6
VDD1_19V8
VDD1_20V10
VDD1_21V12
VDD1_22V14
VDD1_23W4
VDD1_24Y2
VDD0_6J15
VDDNB_1K16
VDD0_16L15
VDDNB_2M16
VDDNB_3P16
VDDNB_4T16
VDD1_17U15
VDDNB_5V16
VDDIO1H25
VDDIO2J17
VDDIO3K18
VDDIO4K21
VDDIO5K23
VDDIO6K25
VDDIO7L17
VDDIO8M18
VDDIO9M21
VDDIO10M23
VDDIO11M25
VDDIO12N17
VDDIO13P18
VDDIO14P21
VDDIO15P23
VDDIO16P25
VDDIO17R17
VDDIO18T18
VDDIO19T21
VDDIO20T23
VDDIO21T25
VDDIO22U17
VDDIO23V18
VDDIO24V21
VDDIO25V23
VDDIO26V25
VDDIO27Y25
C544.7U_0805_10V4Z
1
2
C39180P_0402_50V8J
1
2
+ C49
220U_Y_4VM
1
2
C4022U_0805_6.3V6M
1
2
C340.22U_0603_16V4Z
1
2
C380.01U_0402_25V4Z
1
2
C2822U_0805_6.3V6M
1
2
C591000P_0402_25V8J
1
2
C64180P_0402_50V8J
1
2
C75180P_0402_50V8J
1
2
C60180P_0402_50V8J
1
2
C4422U_0805_6.3V6M
1
2
C804.7U_0805_10V4Z
1
2
C694.7U_0805_10V4Z
1
2
C65180P_0402_50V8J
1
2
C2722U_0805_6.3V6M
1
2
C4322U_0805_6.3V6M
1
2
C46
0.22U_0603_16V4Z
1
2
C4122U_0805_6.3V6M
1
2
C630.01U_0402_25V4Z
1
2
C61180P_0402_50V8J
1
2
+ C23330U_X_2VM_R6M
1
2
+ C24330U_X_2VM_R6M
1
2
C36180P_0402_50V8J
1
2
C530.22U_0603_16V4Z
1
2
C784.7U_0805_10V4Z
1
2
C510.22U_0603_16V4Z
1
2
C520.22U_0603_16V4Z
1
2 C554.7U_0805_10V4Z
1
2
C3122U_0805_6.3V6M
1
2
+ C25330U_X_2VM_R6M
1
2
C570.22U_0603_16V4Z
1
2
C721000P_0402_25V8J
1
2
C710.22U_0603_16V4Z
1
2
C3222U_0805_6.3V6M
1
2
C67180P_0402_50V8J
1
2
C3022U_0805_6.3V6M
1
2
+ C76
220U_Y_4VM
@
1
2
JCPU1F
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
VSS1AA4
VSS2AA11
VSS3AA13
VSS4AA15
VSS5AA17
VSS6AA19
VSS7AB2
VSS8AB7
VSS9AB9
VSS10AB23
VSS11AB25
VSS12AC11
VSS13AC13
VSS14AC15
VSS15AC17
VSS16AC19
VSS17AC21
VSS18AD6
VSS19AD8
VSS20AD25
VSS21AE11
VSS22AE13
VSS23AE15
VSS24AE17
VSS25AE19
VSS26AE21
VSS27AE23
VSS28B4
VSS29B6
VSS30B8
VSS31B9
VSS32B11
VSS33B13
VSS34B15
VSS35B17
VSS36B19
VSS37B21
VSS38B23
VSS39B25
VSS40D6
VSS41D8
VSS42D9
VSS43D11
VSS44D13
VSS45D15
VSS46D17
VSS47D19
VSS48D21
VSS49D23
VSS50D25
VSS51E4
VSS52F2
VSS53F11
VSS54F13
VSS55F15
VSS56F17
VSS57F19
VSS58F21
VSS59F23
VSS60F25
VSS61H7
VSS62H9
VSS63H21
VSS64H23
VSS65J4
VSS66J6
VSS67J8
VSS68J10
VSS69J12
VSS70J14
VSS71J16
VSS72J18
VSS73K2
VSS74K7
VSS75K9
VSS76K11
VSS77K13
VSS78K15
VSS79K17
VSS80L6
VSS81L8
VSS82L10
VSS83L12
VSS84L14
VSS85L16
VSS86L18
VSS87M7
VSS88M9
VSS89AC6
VSS90M17
VSS91N4
VSS92N8
VSS93N10
VSS94N16
VSS95N18
VSS96P2
VSS97P7
VSS98P9
VSS99P11
VSS100P17
VSS101R8
VSS102R10
VSS103R16
VSS104R18
VSS105T7
VSS106T9
VSS107T11
VSS108T13
VSS109T15
VSS110T17
VSS111U4
VSS112U6
VSS113U8
VSS114U10
VSS115U12
VSS116U14
VSS117U16
VSS118U18
VSS119V2
VSS120V7
VSS121V9
VSS122V11
VSS123V13
VSS124V15
VSS125V17
VSS126W6
VSS127Y21
VSS128Y23
VSS129N6
C774.7U_0805_10V4Z
1
2
C66180P_0402_50V8J
1
2
C74180P_0402_50V8J
1
2
C684.7U_0805_10V4Z
1
2
C620.01U_0402_25V4Z
1
2
C581000P_0402_25V8J
1
2
C794.7U_0805_10V4Z
1
2
C560.22U_0603_16V4Z
1
2
C2622U_0805_6.3V6M
1
2
C500.22U_0603_16V4Z
1
2
C2922U_0805_6.3V6M
1
2
C48
180P_0402_50V8J
1
2
C700.22U_0603_16V4Z
1
2
C4222U_0805_6.3V6M
1
2
C45
0.22U_0603_16V4Z
1
2
C47
180P_0402_50V8J
1
2
C3322U_0805_6.3V6M
1
2
C370.22U_0603_16V4Z
1
2
C731000P_0402_25V8J
1
2
![Page 8: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/8.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+V_DDR_MCH_REF
DDR_A_RAS#
DDR_CS1_DIMMA#
DDR_CKE0_DIMMA
DDR_A_ODT1
DDR_A_WE#
DDR_A_D4
DDR_A_CAS# DDR_A_ODT0
DDR_CS0_DIMMA#
DDR_CKE1_DIMMA
DDR_A_D29
DDR_A_D30
DDR_A_D35
DDR_A_D26
DDR_A_D38
DDR_A_BS#0
DDR_A_D28
DDR_A_D34
DDR_A_D36DDR_A_D33
DDR_A_D31
DDR_A_D32
DDR_A_D27
DDR_A_D53
DDR_A_D46DDR_A_D43
DDR_A_D48
DDR_A_D41
DDR_A_D44
DDR_A_D50
DDR_A_D45
DDR_A_D49
DDR_A_D37
DDR_A_D55
DDR_A_D39
DDR_A_D51
DDR_A_D40
DDR_A_D47DDR_A_D42
DDR_A_D63
DDR_A_D54
DDR_A_D6
DDR_A_D14
DDR_A_D52
DDR_A_D3
DDR_A_D59DDR_A_D58
DDR_A_D9
DDR_A_D61DDR_A_D60
DDR_A_D57
DDR_A_D7
DDR_A_D8
DDR_A_D56
DDR_A_D5
DDR_A_D24
DDR_A_D23
DDR_A_D12
DDR_A_D15
DDR_A_D21
DDR_A_BS#1
DDR_A_D22
DDR_A_D16 DDR_A_D20
DDR_A_BS#2
DDR_A_D10
DDR_A_D13
DDR_A_D19DDR_A_D18
DDR_A_D17
DDR_A_D11
DDR_A_DM5
DDR_A_MA11
DDR_A_DM6
DDR_A_DM4
DDR_A_D0
DDR_A_DM7
DDR_A_D62
DDR_A_DM1
DDR_A_DM0
DDR_A_MA4
DDR_A_DM2
DDR_A_D25
DDR_A_D1
DDR_A_DM3
DDR_A_D2
DDR_A_MA8
DDR_A_MA12
DDR_A_MA14
DDR_A_MA9
DDR_A_MA10
DDR_A_DQS#0
DDR_A_MA13
DDR_A_MA1 DDR_A_MA0DDR_A_MA2
DDR_A_MA7
DDR_A_MA15
DDR_A_MA3DDR_A_MA5
DDR_A_MA6
DDR_A_DQS2
DDR_A_DQS6
DDR_A_DQS1
DDR_A_DQS0
DDR_A_DQS#6
DDR_A_DQS3DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS#2
DDR_A_DQS7
DDR_A_DQS#4
DDR_A_DQS#7
DDR_A_DQS#5
DDR_A_DQS#1
DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]
+V_DDR_MCH_REF
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_CKE1_DIMMADDR_A_MA15
DDR_A_MA14
DDR_A_MA6
DDR_A_MA11DDR_A_MA7
DDR_A_MA2DDR_A_MA4
DDR_A_RAS#DDR_CS0_DIMMA#
DDR_A_MA13DDR_A_ODT0
DDR_A_MA8DDR_A_MA9DDR_A_MA12
DDR_A_MA5
DDR_A_MA10DDR_A_MA1DDR_A_MA3
DDR_A_BS#0
DDR_A_CAS#DDR_A_WE#
DDR_CS1_DIMMA#DDR_A_ODT1
DDR_A_MA0DDR_A_BS#1
DDR_A_CLK0 <5>DDR_A_CLK#0 <5>
DDR_CKE0_DIMMA<5>
DDR_A_BS#2<5>
DDR_A_BS#0<5>DDR_A_WE#<5>
DDR_A_CAS#<5>DDR_CS1_DIMMA#<5>
DDR_A_ODT1<5>
DDR_A_CLK1 <5>DDR_A_CLK#1 <5>
DDR_CS0_DIMMA# <5>
DDR_A_ODT0 <5>
DDR_A_RAS# <5>DDR_A_BS#1 <5>
DDR_CKE1_DIMMA <5>
DDR_A_MA[0..15] <5>
DDR_A_D[0..63] <5>
DDR_A_DQS[0..7] <5>
DDR_A_DM[0..7] <5>
DDR_A_DQS#[0..7] <5>
SMB_CK_DAT0<4,6,9,15,21,30>SMB_CK_CLK0<4,6,9,15,21,30>
+V_DDR_MCH_REF <9,44>
+1.8V+1.8V
+3VS
+1.8V
+1.8V+0.9V
+1.8V
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
DDRII SO-DIMM 1
Custom
8 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
9/20 SP07000BZ00/SP07000EU00
DDR2 SOCKET H9.2 (REV)
Cross between +1.8V and +0.9V power plan
Compal EMI 6/11
RP3
47_0804_8P4R_5%
18273645
RP6
47_0804_8P4R_5%
18273645
C91
0.1U_0402_16V4Z
1
2
C83 0.1U_0402_16V4Z
1 2
R480 47_0402_5%
12
C89 0.1U_0402_16V4Z
1 2
RP4
47_0804_8P4R_5%
18273645
C90
1000P_0402_25V8J
1
2
R441K_0402_1%
@
12
RP5
47_0804_8P4R_5%
18273645
C970.1U_0402_16V4Z
1
2
C94 0.1U_0402_16V4Z
1 2
R451K_0402_1%
@
12
R479 47_0402_5%
12
C95 0.1U_0402_16V4Z
1 2
RP1
47_0804_8P4R_5%
18273645 C82 0.1U_0402_16V4Z
1 2
C81 0.1U_0402_16V4Z
1 2
JDIMMA
TYCO_292527-4
CONN@
VREF1
VSS3
DQ05
DQ17
VSS9
DQS0#11
DQS013
VSS15
DQ217
DQ319
VSS21
DQ823
DQ925
VSS27
DQS1#29
DQS131
VSS33
DQ1035
DQ1137
VSS39
VSS41
DQ1643
DQ1745
VSS47
DQS2#49
DQS251
VSS53
DQ1855
DQ1957
VSS59
DQ2461
DQ2563
VSS65
DM367
NC69
VSS71
DQ2673
DQ2775
VSS77
CKE079
VDD81
NC83
BA285
VDD87
A1289
A991
A893
VDD95
A597
A399
A1101
VDD103
A10/AP105
BA0107
WE#109
VDD111
CAS#113
NC/S1#115
VDD117
NC/ODT1119
VSS121
DQ32123
DQ33125
VSS127
DQS4#129
DQS4131
VSS133
DQ34135
DQ35137
VSS139
DQ40141
DQ41143
VSS2
DQ44
DQ56
VSS8
DM010
VSS12
DQ614
DQ716
VSS18
DQ1220
DQ1322
VSS24
DM126
VSS28
CK030
CK0#32
VSS34
DQ1436
DQ1538
VSS40
VSS42
DQ2044
DQ2146
VSS48
NC50
DM252
VSS54
DQ2256
DQ2358
VSS60
DQ2862
DQ2964
VSS66
DQS3#68
DQS370
VSS72
DQ3074
DQ3176
VSS78
NC/CKE180
VDD82
NC/A1584
NC/A1486
VDD88
A1190
A792
A694
VDD96
A498
A2100
A0102
VDD104
BA1106
RAS#108
S0#110
VDD112
ODT0114
NC/A13116
VDD118
NC120
VSS122
DQ36124
DQ37126
VSS128
DM4130
VSS132
DQ38134
DQ39136
VSS138
DQ44140
DQ45142
VSS144
VSS145
DM5147
VSS149
DQ42151
DQ43153
VSS155
DQ48157
DQ49159
VSS161
NC,TEST163
VSS165
DQS6#167
DQS6169
VSS171
DQ50173
DQ51175
VSS177
DQ56179
DQ57181
VSS183
DM7185
VSS187
DQ58189
DQ59191
VSS193
SDA195
SCL197
VDDSPD199
DQS5#146
DQS5148
VSS150
DQ46152
DQ47154
VSS156
DQ52158
DQ53160
VSS162
CK1164
CK1#166
VSS168
DM6170
VSS172
DQ54174
DQ55176
VSS178
DQ60180
DQ61182
VSS184
DQS7#186
DQS7188
VSS190
DQ62192
DQ63194
VSS196
SAO198
SA1200
GND202
GND201
C96 0.1U_0402_16V4Z
1 2
RP7
47_0804_8P4R_5%
18273645
C87 0.1U_0402_16V4Z
1 2
C84 0.1U_0402_16V4Z
1 2
C7200.1U_0402_16V4Z
@
1
2
R481 47_0402_5%
12
R478 47_0402_5%
12
C88 0.1U_0402_16V4Z
1 2
C721
0.1U_0402_16V4Z
@
1
2
C93 0.1U_0402_16V4Z
1 2
C85 0.1U_0402_16V4Z
1 2
C86 0.1U_0402_16V4Z
1 2
C92 0.1U_0402_16V4Z
1 2
![Page 9: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/9.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDR_B_BS#0
DDR_B_D26
DDR_B_D29
DDR_B_D27DDR_B_D30
DDR_B_D33
DDR_B_D31
DDR_B_D32
DDR_B_D28
DDR_B_D34DDR_B_D35
DDR_B_D38
DDR_B_D36
DDR_B_D39
DDR_B_D37
DDR_B_D41
DDR_B_D42
DDR_B_D44DDR_B_D40
DDR_B_D43 DDR_B_D47
DDR_B_D48
DDR_B_D45
DDR_B_D46
DDR_B_D49 DDR_B_D53
DDR_B_D51 DDR_B_D55DDR_B_D50
DDR_B_D52
DDR_B_D56
DDR_B_D54
DDR_B_D59
DDR_B_D57
DDR_B_D58
DDR_B_D61
DDR_B_D63
DDR_B_D60
DDR_B_D3
DDR_B_D8
DDR_B_D6DDR_B_D7
DDR_B_D5
DDR_B_D14
DDR_B_D13
DDR_B_D11DDR_B_D10
DDR_B_D9
DDR_B_D15
DDR_B_D12
DDR_B_D17DDR_B_D20
DDR_B_D18 DDR_B_D22DDR_B_D19
DDR_B_D24
DDR_B_D16
DDR_B_D23
DDR_B_BS#2
DDR_B_BS#1
DDR_B_D25
DDR_B_D62
DDR_B_DM7
DDR_B_DM2
DDR_B_DM4
DDR_B_DM3
DDR_B_DM1
DDR_B_DM0
DDR_B_DM6
DDR_B_DM5
DDR_B_MA4
DDR_B_D0
DDR_B_D2
DDR_B_D1
DDR_B_D4
DDR_B_MA11
DDR_B_MA10
DDR_B_MA12DDR_B_MA9
DDR_B_MA6DDR_B_MA8
DDR_B_MA5
DDR_B_MA7
DDR_B_MA3DDR_B_MA0
DDR_B_MA13
DDR_B_MA15
DDR_B_MA2DDR_B_MA1
DDR_B_MA14
DDR_B_DQS2
DDR_B_DQS#0
DDR_B_DQS4
DDR_B_DQS0
DDR_B_DQS#1
DDR_B_DQS5
DDR_B_DQS7
DDR_B_DQS3
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS#4
DDR_B_DQS#2
DDR_B_DQS#6
DDR_B_DQS#3
DDR_B_DQS1
DDR_B_DQS#5
DDR_B_ODT1
DDR_CKE0_DIMMB
DDR_CS1_DIMMB#
DDR_B_RAS#DDR_B_WE#
DDR_CKE1_DIMMB
DDR_B_CAS# DDR_B_ODT0
DDR_CS0_DIMMB#
DDR_B_MA4
DDR_B_D[0..63]
DDR_B_MA[0..15]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_DQS#[0..7]
DDR_B_WE#DDR_B_CAS#DDR_CS1_DIMMB#DDR_B_ODT1
DDR_B_MA3DDR_B_MA1
DDR_B_MA13DDR_B_ODT0
DDR_CS0_DIMMB#DDR_B_MA0DDR_B_MA2DDR_B_MA6
DDR_B_MA7DDR_B_MA11DDR_B_MA14
DDR_B_D21
DDR_B_MA15DDR_CKE1_DIMMB
DDR_CKE0_DIMMBDDR_B_BS#2
DDR_B_RAS#DDR_B_BS#1
DDR_B_MA5DDR_B_MA8
DDR_B_MA9DDR_B_MA12
DDR_B_BS#0DDR_B_MA10
+V_DDR_MCH_REF<8,44>
DDR_B_CLK0 <5>DDR_B_CLK#0 <5>
DDR_CKE0_DIMMB<5>
DDR_B_BS#2<5>
DDR_B_BS#0<5>DDR_B_WE#<5>
DDR_B_CAS#<5>DDR_CS1_DIMMB#<5>
DDR_B_ODT1<5>
DDR_B_CLK1 <5>DDR_B_CLK#1 <5>
DDR_B_ODT0 <5>
DDR_B_RAS# <5>DDR_B_BS#1 <5>
DDR_CKE1_DIMMB <5>
DDR_CS0_DIMMB# <5>
DDR_B_MA[0..15] <5>
DDR_B_D[0..63] <5>
DDR_B_DQS[0..7] <5>
DDR_B_DM[0..7] <5>
DDR_B_DQS#[0..7] <5>
SMB_CK_DAT0<4,6,8,15,21,30>SMB_CK_CLK0<4,6,8,15,21,30>
+1.8V+1.8V
+3VS
+0.9V +1.8V
+3VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
DDRII SO-DIMM 2
Custom
9 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
9/20 SP07000ET00/SP07000GN00
Cross between +1.8V and +0.9V power plan
change 8P4R to 0402 for improve layout placement. Compal 12/5
R526 47_0402_5%
12
RP14
47_0804_8P4R_5%
18273645
C103 0.1U_0402_16V4Z
12
C108 0.1U_0402_16V4Z
1 2
C107 0.1U_0402_16V4Z
12
RP9
47_0804_8P4R_5%
18273645
C99 0.1U_0402_16V4Z
1 2
R527 47_0402_5%
12
R524 47_0402_5%
12
RP11
47_0804_8P4R_5%
18273645
C104 0.1U_0402_16V4Z
1 2
C1130.1U_0402_16V4Z
1
2
RP8
47_0804_8P4R_5%
18273645
C105 0.1U_0402_16V4Z
12
C102 0.1U_0402_16V4Z
1 2
C106 0.1U_0402_16V4Z
1 2
JDIMMB
TYCO_292527-4
CONN@
VREF1
VSS3
DQ05
DQ17
VSS9
DQS0#11
DQS013
VSS15
DQ217
DQ319
VSS21
DQ823
DQ925
VSS27
DQS1#29
DQS131
VSS33
DQ1035
DQ1137
VSS39
VSS41
DQ1643
DQ1745
VSS47
DQS2#49
DQS251
VSS53
DQ1855
DQ1957
VSS59
DQ2461
DQ2563
VSS65
DM367
NC69
VSS71
DQ2673
DQ2775
VSS77
CKE079
VDD81
NC83
BA285
VDD87
A1289
A991
A893
VDD95
A597
A399
A1101
VDD103
A10/AP105
BA0107
WE#109
VDD111
CAS#113
NC/S1#115
VDD117
NC/ODT1119
VSS121
DQ32123
DQ33125
VSS127
DQS4#129
DQS4131
VSS133
DQ34135
DQ35137
VSS139
DQ40141
DQ41143
VSS2
DQ44
DQ56
VSS8
DM010
VSS12
DQ614
DQ716
VSS18
DQ1220
DQ1322
VSS24
DM126
VSS28
CK030
CK0#32
VSS34
DQ1436
DQ1538
VSS40
VSS42
DQ2044
DQ2146
VSS48
NC50
DM252
VSS54
DQ2256
DQ2358
VSS60
DQ2862
DQ2964
VSS66
DQS3#68
DQS370
VSS72
DQ3074
DQ3176
VSS78
NC/CKE180
VDD82
NC/A1584
NC/A1486
VDD88
A1190
A792
A694
VDD96
A498
A2100
A0102
VDD104
BA1106
RAS#108
S0#110
VDD112
ODT0114
NC/A13116
VDD118
NC120
VSS122
DQ36124
DQ37126
VSS128
DM4130
VSS132
DQ38134
DQ39136
VSS138
DQ44140
DQ45142
VSS144
VSS145
DM5147
VSS149
DQ42151
DQ43153
VSS155
DQ48157
DQ49159
VSS161
NC,TEST163
VSS165
DQS6#167
DQS6169
VSS171
DQ50173
DQ51175
VSS177
DQ56179
DQ57181
VSS183
DM7185
VSS187
DQ58189
DQ59191
VSS193
SDA195
SCL197
VDDSPD199
DQS5#146
DQS5148
VSS150
DQ46152
DQ47154
VSS156
DQ52158
DQ53160
VSS162
CK1164
CK1#166
VSS168
DM6170
VSS172
DQ54174
DQ55176
VSS178
DQ60180
DQ61182
VSS184
DQS7#186
DQS7188
VSS190
DQ62192
DQ63194
VSS196
SAO198
SA1200
GND202
GND201
C100
1000P_0402_25V8J
1
2
C109 0.1U_0402_16V4Z
12
R525 47_0402_5%
12
C111 0.1U_0402_16V4Z
12
C110 0.1U_0402_16V4Z
1 2
RP12
47_0804_8P4R_5%
18273645
C98 0.1U_0402_16V4Z
12
C112 0.1U_0402_16V4Z
1 2
C101 0.1U_0402_16V4Z
12
RP13
47_0804_8P4R_5%
18273645
![Page 10: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/10.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
H_CADIN0H_CADIP1H_CADIN1
H_CADIN2H_CADIP2
H_CADIN3H_CADIP3
H_CTLIN0H_CTLIP0
H_CTLON0
H_CADIN4H_CADIP4
H_CADIN5H_CADIP5
H_CADIN6H_CADIP6
H_CADIN7H_CADIP7
H_CADIN8H_CADIP8
H_CADIN9H_CADIP9
H_CADIN10H_CADIP10
H_CTLOP0
H_CADIP11H_CADIN11H_CADIP12H_CADIN12
H_CADIN13H_CADIP13
H_CADIN14H_CADIP14
H_CADIN15H_CADIP15
H_CADOP0H_CADON0H_CADOP1H_CADON1
H_CTLIP1H_CTLIN1
H_CADON2
H_CTLOP1
H_CADOP2
H_CTLON1
H_CADOP3H_CADON3
H_CADON4H_CADOP4
H_CADOP5H_CADON5H_CADOP6H_CADON6H_CADOP7H_CADON7
H_CADOP15H_CADON15
H_CADOP14H_CADON14
H_CADOP13H_CADON13
H_CADOP12H_CADON12
H_CADOP11H_CADON11
H_CADON10H_CADOP10H_CADON9H_CADOP9
H_CADOP8H_CADON8
H_CADIP0
PCIE_PTX_DRX_P1PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P3PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P0PCIE_PTX_DRX_N0
SB_TX2P_CSB_TX2N_CSB_TX3P_CSB_TX3N_C
SB_TX0P_CSB_TX0N_CSB_TX1P_C
H_CADIN[0..15]
H_CADIP[0..15]H_CADOP[0..15]
H_CADON[0..15]
SB_TX1N_C
PCIE_PTX_DRX_P4PCIE_PTX_DRX_N4
H_CLKIN0 <4>H_CLKIP0 <4>
H_CTLIN0 <4>H_CTLIP0 <4>
H_CLKON0<4>H_CLKOP0<4>
H_CLKOP1<4>H_CLKON1<4>
H_CTLOP0<4>H_CTLON0<4>
H_CLKIN1 <4>H_CLKIP1 <4>
H_CTLIN1 <4>H_CTLIP1 <4>H_CTLOP1<4>
H_CTLON1<4>
PCIE_PTX_C_DRX_P3 <31>PCIE_PTX_C_DRX_N3 <31>
PCIE_PRX_DTX_P0<25>PCIE_PRX_DTX_N0<25>
PCIE_PRX_DTX_P3<31>PCIE_PRX_DTX_N3<31>
H_CADIP[0..15] <4>
H_CADON[0..15]<4> H_CADIN[0..15] <4>
H_CADOP[0..15]<4>
SB_RX1P<19>SB_RX1N<19>
SB_RX0P<19>SB_RX0N<19>
SB_TX0P <19>
SB_TX1N <19>
SB_TX0N <19>SB_TX1P <19>
SB_RX3P<19>SB_RX3N<19>
SB_RX2P<19>SB_RX2N<19>
SB_TX2P <19>SB_TX2N <19>
SB_TX3N <19>SB_TX3P <19>
PCIE_PTX_C_DRX_P0 <25>PCIE_PTX_C_DRX_N0 <25>PCIE_PTX_C_DRX_P1 <31>PCIE_PTX_C_DRX_N1 <31>
PCIE_PRX_DTX_P1<31>PCIE_PRX_DTX_N1<31>
PCIE_PTX_C_DRX_P4 <27>PCIE_PTX_C_DRX_N4 <27>
PCIE_PRX_DTX_P4<27>PCIE_PRX_DTX_N4<27>
DPB_TXP3 <32>DPB_TXN3 <32>
DPB_TXP2 <32>DPB_TXN2 <32>
DPB_TXP1 <32>DPB_TXN1 <32>
DPB_TXP0 <32>DPB_TXN0 <32>
DPC_TXP3 <32>DPC_TXN3 <32>
DPC_TXP2 <32>DPC_TXN2 <32>
DPC_TXP1 <32>DPC_TXN1 <32>
DPC_TXP0 <32>DPC_TXN0 <32>
DPA_TXP2 <18>DPA_TXN2 <18>
DPA_TXP1 <18>DPA_TXN1 <18>
DPA_TXP0 <18>DPA_TXN0 <18>
DPA_TXP3 <18>DPA_TXN3 <18>
+1.1VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
RS880-HT/PCIE
Custom
10 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
Place within 1"layout 1:2 (W/S=5mil/10mil)
Place within 1"layout 1:2 (W/S=5mil/10mil)
NIC
WLAN
EXP
Media Card
DP0GFX_TX0,TX1,TX2 and TX3
RS780M Display Port Support (muxed on GFX)
DP1GFX_TX4,TX5,TX6 and TX7
AUX0 and HPD0
AUX1 and HPD1
9/20 SA00001ZG00(A11) S IC 216-0674001-00/RS780M FCBGA528P 0FH
Display Port
remove UWB , 10/21 HPremove UWB , 10/21 HP
C131 0.1U_0402_16V7K 1 2
C128 0.1U_0402_16V7K 1 2C129 0.1U_0402_16V7K 1 2
C120 0.1U_0402_16V7K 1 2
PART 2 OF 6
PC
IE I/F
G
FX
PCIE I/F GPP
PCIE I/F SB
U4B
RS880MN_FCBGA528
SB_TX3PAD5
SB_TX3NAE5
GPP_TX2PAA2
GPP_TX2NAA1
GPP_TX3PY1
GPP_TX3NY2
SB_RX3PW5
SB_RX3NY5
GPP_RX2PAD1
GPP_RX2NAD2
GPP_RX3PV5
GPP_RX3NW6
SB_TX0PAD7
SB_TX0NAE7
SB_TX1PAE6
SB_TX1NAD6
SB_RX0PAA8
SB_RX0NY8
SB_RX1PAA7
SB_RX1NY7
PCE_CALRP(PCE_BCALRP)AC8
PCE_CALRN(PCE_BCALRN)AB8
SB_TX2NAC6
SB_RX2PAA5
SB_RX2NAA6
SB_TX2PAB6
GPP_RX0PAE3
GPP_RX0NAD4
GPP_RX1PAE2
GPP_RX1NAD3
GPP_TX0PAC1
GPP_TX0NAC2
GPP_TX1PAB4
GPP_TX1NAB3
GFX_RX0PD4
GFX_RX0NC4
GFX_RX1PA3
GFX_RX1NB3
GFX_RX2PC2
GFX_RX2NC1
GFX_RX3PE5
GFX_RX3NF5
GFX_RX4PG5
GFX_RX4NG6
GFX_RX5PH5
GFX_RX5NH6
GFX_RX6PJ6
GFX_RX6NJ5
GFX_RX7PJ7
GFX_RX7NJ8
GFX_RX8PL5
GFX_RX8NL6
GFX_RX9PM8
GFX_RX9NL8
GFX_RX10PP7
GFX_RX10NM7
GFX_RX11PP5
GFX_RX11NM5
GFX_RX12PR8
GFX_RX12NP8
GFX_RX13PR6
GFX_RX13NR5
GFX_RX14PP4
GFX_RX14NP3
GFX_RX15PT4
GFX_RX15NT3
GFX_TX0PA5
GFX_TX0NB5
GFX_TX1PA4
GFX_TX1NB4
GFX_TX2PC3
GFX_TX2NB2
GFX_TX3PD1
GFX_TX3ND2
GFX_TX4PE2
GFX_TX4NE1
GFX_TX5PF4
GFX_TX5NF3
GFX_TX6PF1
GFX_TX6NF2
GFX_TX7PH4
GFX_TX7NH3
GFX_TX8PH1
GFX_TX8NH2
GFX_TX9PJ2
GFX_TX9NJ1
GFX_TX10PK4
GFX_TX10NK3
GFX_TX11PK1
GFX_TX11NK2
GFX_TX12PM4
GFX_TX12NM3
GFX_TX13PM1
GFX_TX13NM2
GFX_TX14PN2
GFX_TX14NN1
GFX_TX15PP1
GFX_TX15NP2
GPP_TX4PY4
GPP_TX4NY3
GPP_TX5PV1
GPP_TX5NV2
GPP_RX4PU5
GPP_RX4NU6
GPP_RX5PU8
GPP_RX5NU7
C119 0.1U_0402_16V7K 1 2
R46 1.27K_0402_1% 1 2
C116 0.1U_0402_16V7K 1 2
C118 0.1U_0402_16V7K 1 2
PART 1 OF 6
HY
PE
R T
RA
NS
PO
RT
CP
U I/F
U4A
RS880MN_FCBGA528
HT_RXCAD15PU19
HT_RXCAD15NU18
HT_RXCAD14PU20
HT_RXCAD14NU21
HT_RXCAD13PV21
HT_RXCAD13NV20
HT_RXCAD12PW21
HT_RXCAD12NW20
HT_RXCAD11PY22
HT_RXCAD11NY23
HT_RXCAD10PAA24
HT_RXCAD10NAA25
HT_RXCAD9PAB25
HT_RXCAD9NAB24
HT_RXCAD8PAC24
HT_RXCAD8NAC25
HT_RXCAD7PN24
HT_RXCAD7NN25
HT_RXCAD6PP25
HT_RXCAD6NP24
HT_RXCAD5PP22
HT_RXCAD5NP23
HT_RXCAD4PT25
HT_RXCAD4NT24
HT_RXCAD3PU24
HT_RXCAD3NU25
HT_RXCAD2PV25
HT_RXCAD2NV24
HT_RXCAD1PV22
HT_RXCAD1NV23
HT_RXCAD0PY25
HT_RXCAD0NY24
HT_RXCLK1PAB23
HT_RXCLK1NAA22
HT_RXCLK0PT22
HT_RXCLK0NT23
HT_RXCTL0PM22
HT_RXCTL0NM23
HT_RXCTL1PR21
HT_RXCTL1NR20
HT_RXCALPC23
HT_RXCALNA24
HT_TXCAD15PP18
HT_TXCAD15NM18
HT_TXCAD14PM21
HT_TXCAD14NP21
HT_TXCAD13PM19
HT_TXCAD13NL18
HT_TXCAD12PL19
HT_TXCAD12NJ19
HT_TXCAD11PJ18
HT_TXCAD11NK17
HT_TXCAD10PJ20
HT_TXCAD10NJ21
HT_TXCAD9PG20
HT_TXCAD9NH21
HT_TXCAD8PF21
HT_TXCAD8NG21
HT_TXCAD7PK23
HT_TXCAD7NK22
HT_TXCAD6PK24
HT_TXCAD6NK25
HT_TXCAD5PJ25
HT_TXCAD5NJ24
HT_TXCAD4PH23
HT_TXCAD4NH22
HT_TXCAD3PF23
HT_TXCAD3NF22
HT_TXCAD2PF24
HT_TXCAD2NF25
HT_TXCAD1PE24
HT_TXCAD1NE25
HT_TXCAD0PD24
HT_TXCAD0ND25
HT_TXCLK1PL21
HT_TXCLK1NL20
HT_TXCLK0PH24
HT_TXCLK0NH25
HT_TXCTL0PM24
HT_TXCTL0NM25
HT_TXCTL1PP19
HT_TXCTL1NR18
HT_TXCALPB24
HT_TXCALNB25
R48 301_0402_1%1 2
C121 0.1U_0402_16V7K 1 2
R49 301_0402_1%1 2
C130 0.1U_0402_16V7K 1 2
R47 2K_0402_1% 1 2
C117 0.1U_0402_16V7K 1 2
C115 0.1U_0402_16V7K 1 2
C114 0.1U_0402_16V7K 1 2
C124 0.1U_0402_16V7K 1 2C125 0.1U_0402_16V7K 1 2C126 0.1U_0402_16V7K 1 2C127 0.1U_0402_16V7K 1 2
![Page 11: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/11.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+VDDA18HTPLL
+NB_HTPVDD
+AVDD2
NB_THERMAL_DCNB_THERMAL_DA
NB_RESET#
+AVDD1
D_RED
D_BLUE
CRT_VSYNC
D_GREEN
CRT_HSYNC
NB_PWRGD
NB_ALLOW_LDTSTOPNB_LDTSTOP#
+VDDLT18
+AVDDQ
+VDDLTP18+NB_PLLVDD
+VDDA18PCIEPLL
NB_LDTSTOP#
NB_ALLOW_LDTSTOP
NB_PWM
ENAVDDENABLT
ENABLT
ENAVDD
CRT_DDC_CLK<16,32>CRT_DDC_DATA<16,32>
HDMIDAT_UMA<18,32>
NB_PWRGD<21>
CRT_HSYNC<14,16>CRT_VSYNC<14,16>
ENAVDD <17>INV_PWM <17>
NBGFX_CLK<15>NBGFX_CLK#<15>
CLK_SBLINK_BCLK<15>CLK_SBLINK_BCLK#<15>
CLK_NBHT<15>CLK_NBHT#<15>
PLT_RST#<19,25,27,29,31,34>
D_RED<16>
D_GREEN<16>
D_BLUE<16>
AUX_CAL<14>
SUS_STAT# <21>
LVDS_A2+ <17>
LVDS_A0+ <17>
LVDS_A1+ <17>
LVDS_ACLK- <17>
HDMICLK_UMA<18,32>
LVDS_ACLK+ <17>
LVDS_A2- <17>
LVDS_A0- <17>
LVDS_A1- <17>
DDC2_DATA<17>DDC2_CLK<17>
NB_OSC_14.318M<15>
LDT_STOP#<6,19>
CPU_LDT_REQ#<6,19>
LVDS_B2+ <17>
LVDS_B0+ <17>
LVDS_B1+ <17>
LVDS_B2- <17>
LVDS_B0- <17>
LVDS_B1- <17>
LVDS_BCLK- <17>LVDS_BCLK+ <17>
ENABLT <17>
NB_THERMAL_DC <4>NB_THERMAL_DA <4>
DYN_PWR_EN<43>
DOCK_AUX+<32>DOCK_AUX-<32>
HPD <18>
DPC_HPD <32>
+3VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+1.1VS
+1.8VS
+1.8VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
RS880 VEDIO/CLK GEN
Custom
11 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
AVDD=150mA
Strap pin
L 0.08A/10mil/1vias
LVDS
install 10/25 HP
HP request 12/02
HP 2/6
L10
FBMA-L11-160808-221LMT_06031 2
R53 0_0402_5%
1 2
R60 100K_0402_5%
1 2
C1410.1U_0402_16V4Z
1
2
R652K_0402_5%
12
C1332.2U_0603_6.3V4Z
1
2
R61 0_0402_5%
1 2
PART 3 OF 6
PM
CL
OC
Ks
PL
L P
WR
MIS.
CR
T/T
VO
UT
LV
TM
U4C
RS880MN_FCBGA528
VDDA18HTPLLH17
SYSRESETbD8
POWERGOODA10
LDTSTOPbC10
ALLOW_LDTSTOPC12
REFCLK_P/OSCIN(OSCIN)E11
PLLVDD(NC)A12
HPD(NC)D10
DDC_CLK0/AUX0P(NC)A8
DDC_DATA0/AUX0N(NC)B8
THERMALDIODE_PAE8
THERMALDIODE_NAD8
I2C_CLKB9
STRP_DATAB10
GFX_REFCLKPT2
GFX_REFCLKNT1
GPP_REFCLKPU1
GPP_REFCLKNU2
PLLVDD18(NC)D14
PLLVSS(NC)B12
TXOUT_L0P(NC)A22
TXOUT_L0N(NC)B22
TXOUT_L1P(NC)A21
TXOUT_L1N(NC)B21
TXOUT_L2P(NC)B20
TXOUT_L2N(DBG_GPIO0)A20
TXOUT_L3P(NC)A19
TXOUT_U0P(NC)B18
TXOUT_L3N(DBG_GPIO2)B19
TXOUT_U0N(NC)A18
TXOUT_U1P(PCIE_RESET_GPIO3)A17
TXOUT_U1N(PCIE_RESET_GPIO2)B17
TXOUT_U2P(NC)D20
TXOUT_U2N(NC)D21
TXOUT_U3P(PCIE_RESET_GPIO5)D18
TXOUT_U3N(NC)D19
TXCLK_LP(DBG_GPIO1)B16
TXCLK_LN(DBG_GPIO3)A16
TXCLK_UP(PCIE_RESET_GPIO4)D16
TXCLK_UN(PCIE_RESET_GPIO1)D17
VDDLTP18(NC)A13
VSSLTP18(NC)B13
C_Pr(DFT_GPIO5)E17
Y(DFT_GPIO2)F17
COMP_Pb(DFT_GPIO4)F15
RED(DFT_GPIO0)G18
TMDS_HPD(NC)D9
I2C_DATAA9
TESTMODED13
HT_REFCLKNC24
HT_REFCLKPC25
SUS_STAT#(PWM_GPIO5)D12
GREEN(DFT_GPIO1)E18
BLUE(DFT_GPIO3)E19
DAC_VSYNC(PWM_GPIO6)B11
DAC_HSYNC(PWM_GPIO4)A11
DAC_RSET(PWM_GPIO1)G14
AVDD1(NC)F12
AVDD2(NC)E12
REDb(NC)G17
GREENb(NC)F18
AVDDDI(NC)F14
AVSSDI(NC)G15
AVDDQ(NC)H15
AVSSQ(NC)H14
VDDLT18_2(NC)B15
VDDLT33_1(NC)A14
VDDLT33_2(NC)B14
VSSLT1(VSS)C14
VSSLT2(VSS)D15
VDDLT18_1(NC)A15
VSSLT3(VSS)C16
VSSLT4(VSS)C18
VSSLT5(VSS)C20
LVDS_DIGON(PCE_TCALRP)E9
LVDS_BLON(PCE_RCALRP)F7
LVDS_ENA_BL(PWM_GPIO2)G12
VSSLT6(VSS)E20
VDDA18PCIEPLL1D7
VDDA18PCIEPLL2E7
BLUEb(NC)F19
AUX_CAL(NC)C8
GPPSB_REFCLKP(SB_REFCLKP)V4
GPPSB_REFCLKN(SB_REFCLKN)V3
DDC_DATA1/AUX1N(NC)A7
DDC_CLK1/AUX1P(NC)B7
DAC_SCL(PCE_RCALRN)F8
DAC_SDA(PCE_TCALRN)E8
REFCLK_N(PWM_GPIO3)F11
VSSLT7(VSS)C22
RSVDG11
R59 10K_0402_5%
1 2
L9
FBMA-L11-160808-221LMT_06031 2
C1380.1U_0402_16V4Z
1
2
L5
FBMA-L11-160808-221LMT_06031 2
R641.8K_0402_5%
1 2
R63 5.1K_0402_1%
12
R54 300_0402_5%
1 2
L3
0_0603_5%
R572.2K_0402_5%
1 2
L2
BLM18PG121SN1D_0603
1 2
C136
2.2U_0603_6.3V4Z
1
2C139
2.2U_0603_6.3V4Z
1
2
R51
0_0402_5%
1 2
C1322.2U_0603_6.3V4Z
1
2
L8
FBMA-L11-160808-221LMT_06031 2
R52 715_0402_1%
1 2
C1402.2U_0603_6.3V4Z
1
2
C1372.2U_0603_6.3V4Z
1
2
L4
FBMA-L11-160808-221LMT_06031 2
R564.7K_0402_5%
1 2
R550_0402_5%1 2
R58 10K_0402_5%
1 2
C1424.7U_0805_10V4Z
1
2
C1342.2U_0603_6.3V4Z
1
2
L6
FBMA-L11-160808-221LMT_06031 2
L7
FBMA-L11-160808-221LMT_06031 2
R50
0_0402_5%
1 2
C135
2.2U_0603_6.3V4Z
1
2
![Page 12: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/12.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+VDDA11PCIE
+1.8V_VDD_MEM
+VDDHTRX
+VDDHT
+VDDA18PCIE
+1.8V_VDD_SP
+VDDHTTX
+1.1VS
+1.8VS
+NB_VDDC
+1.8VS
+3VS
+1.8VS
+1.2V_HT
+1.1VS
+1.8VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
RS880 PWR/GND
Custom
12 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
2A
2A
2A
2A
VDDA_12=2.5A
VDD_CORE=5A
L 0.6A/50mil/4vias
L 0.45A/40mil/3vias
L 0.5A/50mil/4vias
L 0.25A/30mil/2vias
L 0.7A/60mil/4vias
L 7A/280mil/16vias
L 0.15A/30mil/2vias
10/09 HP
10/09 HP
10/07 HP
C181
0.1U_0402_16V4Z
1
2
C152 1U_0402_6.3V4Z
1 2
C155
0.1U_0402_16V4Z
1
2
C162
0.1U_0402_16V4Z
1
2
C163
0.1U_0402_16V4Z
1
2
C1920.1U_0402_16V4Z
1 2
C185 0.1U_0402_16V4Z12
C150 1U_0402_6.3V4Z
1 2
C1
68
0.1
U_
04
02
_1
6V
4Z
1
2
C1910.1U_0402_16V4Z
1 2
C187 0.1U_0402_16V4Z12
L12
FBMA-L11-201209-221LMA30T_0805
1 2
C1
72
0.1
U_
04
02
_1
6V
4Z
1
2
L14
FBMA-L11-201209-221LMA30T_0805
1 2
C184 4.7U_0805_10V4Z12
C1
70
0.1
U_
04
02
_1
6V
4Z
1
2
C1440.1U_0402_16V4Z
1
2
C182
0.1U_0402_16V4Z
1
2
PART 6/6
GR
OU
ND
U4F
RS880MN_FCBGA528
VSSAHT1A25
VSSAHT2D23
VSSAHT3E22
VSSAHT4G22
VSSAHT5G24
VSSAHT6G25
VSSAHT7H19
VSSAHT8J22
VSSAHT9L17
VSSAHT10L22
VSSAHT11L24
VSSAHT12L25
VSSAHT13M20
VSSAHT14N22
VSSAHT15P20
VSSAHT16R19
VSSAHT17R22
VSSAHT18R24
VSSAHT19R25
VSSAHT21U22
VSSAHT22V19
VSSAHT23W22
VSSAHT24W24
VSSAHT25W25
VSSAHT26Y21
VSSAHT27AD25
VSS2D11
VSS3G8
VSS4E14
VSS5E15
VSS7J12
VSS8K14
VSS9M11
VSS10L15
VSS11L12
VSS12M14
VSS13N13
VSS14P12
VSS15P15
VSS16R11
VSS17R14
VSS18T12
VSS19U14
VSS20U11
VSS21U15
VSS22V12
VSS23W11
VSS24W15
VSS25AC12
VSS26AA14
VSS27Y18
VSS28AB11
VSS29AB15
VSS30AB17
VSS31AB19
VSS32AE20
VSSAPCIE1A2
VSSAPCIE2B1
VSSAPCIE3D3
VSSAPCIE4D5
VSSAPCIE5E4
VSSAPCIE6G1
VSSAPCIE7G2
VSSAPCIE8G4
VSSAPCIE9H7
VSSAPCIE10J4
VSSAPCIE11R7
VSSAPCIE12L1
VSSAPCIE13L2
VSSAPCIE14L4
VSSAPCIE15L7
VSS34K11
VSSAPCIE16M6
VSSAPCIE17N4
VSSAPCIE18P6
VSSAPCIE19R1
VSSAPCIE20R2
VSSAPCIE21R4
VSSAPCIE22V7
VSSAPCIE23U4
VSSAPCIE24V8
VSSAPCIE25V6
VSSAPCIE26W1
VSSAPCIE27W2
VSSAPCIE28W4
VSSAPCIE29W7
VSSAPCIE30W8
VSSAPCIE31Y6
VSSAPCIE32AA4
VSSAPCIE33AB5
VSSAPCIE34AB1
VSSAPCIE35AB7
VSSAPCIE36AC3
VSSAPCIE37AC4
VSSAPCIE38AE1
VSSAPCIE39AE4
VSSAPCIE40AB2
VSS1AE14
VSSAHT20H20
VSS33AB21
VSS6J15
C157
0.1U_0402_16V4Z
1
2
+C166
330U_D2E_2.5VM_R15
1
2C1784.7U_0805_10V4Z
1
2
L15
FBMA-L11-201209-221LMA30T_0805
1 2 C1
69
0.1
U_
04
02
_1
6V
4Z
1
2
C1
76
10
U_
08
05
_1
0V
4Z
1
2
C1
67
0.1
U_
04
02
_1
6V
4Z
1
2
C1434.7U_0805_10V4Z
1
2
C190
1U_0402_6.3V4Z
1
2
C180
0.1U_0402_16V4Z
1
2
C147
0.1U_0402_16V4Z
1
2
C148 10U_0805_10V4Z
C1
77
10
U_
08
05
_1
0V
4Z
1
2
C149 10U_0805_10V4Z
C158 1U_0402_6.3V4Z
1 2C159 0.1U_0402_16V4Z 12
C1
73
0.1
U_
04
02
_1
6V
4Z
1
2
C1
75
0.1
U_
04
02
_1
6V
4Z
1
2
C1891U_0402_6.3V4Z
1
2
C1
74
0.1
U_
04
02
_1
6V
4Z
1
2
C161
4.7U_0805_10V4Z
1
2
C1560.1U_0402_16V4Z
1
2 C160 0.1U_0402_16V4Z 12
C164
0.1U_0402_16V4Z
1
2
C154
0.1U_0402_16V4Z 1
2
PART 5/6
PO
WE
R
U4E
RS880MN_FCBGA528
VDDHT_1J17
VDDHT_2K16
VDDHT_3L16
VDDHT_4M16
VDDHT_5P16
VDDHT_6R16
VDDHT_7T16
VDDHTTX_1AE25
VDDHTTX_2AD24
VDDHTTX_3AC23
VDDHTTX_4AB22
VDDHTTX_5AA21
VDDHTTX_6Y20
VDDHTTX_7W19
VDDHTTX_8V18
VDDHTRX_1H18
VDDHTRX_2G19
VDDHTRX_3F20
VDDHTRX_4E21
VDDHTRX_5D22
VDD18_1F9
VDD18_2G9
VDD18_MEM1(NC)AE11
VDD18_MEM2(NC)AD11
VDDA18PCIE_1J10
VDDA18PCIE_2P10
VDDA18PCIE_3K10
VDDA18PCIE_10Y9
VDDA18PCIE_11AA9
VDDA18PCIE_12AB9
VDDA18PCIE_13AD9
VDDA18PCIE_14AE9
VDDA18PCIE_6W9
VDDA18PCIE_7H9
VDDPCIE_1A6
VDDPCIE_2B6
VDDPCIE_3C6
VDDPCIE_4D6
VDDPCIE_5E6
VDDPCIE_6F6
VDDPCIE_7G7
VDDPCIE_8H8
VDDPCIE_9J9
VDDA18PCIE_4M10
VDDA18PCIE_5L10
VDDC_1K12
VDDC_2J14
VDDC_3U16
VDDPCIE_11M9
VDDC_4J11
VDDC_5K15
VDDPCIE_10K9
VDDC_6M12
VDDC_7L14
VDDC_8L11
VDDC_9M13
VDDC_10M15
VDDC_11N12
VDDC_12N14
VDDC_13P11
VDDC_14P13
VDDC_15P14
VDDC_16R12
VDDC_17R15
VDDC_18T11
VDDC_19T15
VDDC_20U12
VDDC_21T14
VDD33_1(NC)H11
VDD33_2(NC)H12
VDD_MEM1(NC)AE10
VDD_MEM2(NC)AA11
VDD_MEM3(NC)Y11
VDD_MEM4(NC)AD10
VDD_MEM6(NC)AC10
VDD_MEM5(NC)AB10
VDDA18PCIE_8T10
VDDC_22J16
VDDPCIE_12L9
VDDA18PCIE_9R10
VDDPCIE_13P9
VDDPCIE_14R9
VDDPCIE_15T9
VDDPCIE_16V9
VDDPCIE_17U9
VDDA18PCIE_15U10
VDDHTRX_6B23
VDDHTRX_7A23
VDDHTTX_9U17
VDDHTTX_10T17
VDDHTTX_11R17
VDDHTTX_12P17
VDDHTTX_13M17
C1534.7U_0805_10V4Z
1
2
C179
4.7U_0805_10V4Z
1
2
C151 1U_0402_6.3V4Z
1 2
C1
71
0.1
U_
04
02
_1
6V
4Z
1
2
C186 0.1U_0402_16V4Z12
C183
0.1U_0402_16V4Z
1
2
C145
0.1U_0402_16V4Z
1
2
C1460.1U_0402_16V4Z
1
2
C188 0.1U_0402_16V4Z12
C165
0.1U_0402_16V4Z
1
2
![Page 13: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/13.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
MEM_DQS_P0
MEM_DQS_P1MEM_DQS_N0
MEM_A9
MEM_A2 MEM_A12
MEM_DQ9
MEM_DQS_P0
+MEM_VREF
MEM_DQS_N0
MEM_ODT
MEM_DQS_P1
MEM_DM1
MEM_DQS_N1
MEM_DQ12 MEM_A2
MEM_DQ2
MEM_A8
MEM_DQ15
MEM_A1
MEM_A3
+MEM_VREF
MEM_A0
MEM_DQ0
MEM_DQ7MEM_DQ3
MEM_DQ5
MEM_DQ1
MEM_DQ14
MEM_DQ6
MEM_A11
MEM_BA0MEM_BA1
MEM_CKE
MEM_WE#MEM_CS#
MEM_A4
MEM_DQS_N1MEM_RAS#MEM_CAS#
MEM_BA2
MEM_DM1
MEM_CLKPMEM_CLKN
MEM_ODT
MEM_DM0
MEM_A10
MEM_DQ8
+MEM_VREF1
MEM_A11
MEM_A8MEM_A9
MEM_CAS#
MEM_CS#
MEM_CLKN
MEM_CKE
MEM_RAS#
MEM_CLKP
MEM_WE#
MEM_DM0
MEM_BA0
MEM_A7
MEM_DQ11
+MEM_VREF1
MEM_A0
MEM_A10
MEM_BA2
MEM_A3
MEM_DQ10
MEM_BA1
MEM_A6
+VDDL
MEM_DQ13 MEM_A1
MEM_A6MEM_A7
MEM_A4MEM_A5
MEM_DQ4
MEM_DQ2
MEM_DQ0MEM_DQ1
MEM_DQ3
MEM_DQ10
MEM_DQ7
MEM_DQ11
MEM_DQ8
MEM_DQ5MEM_DQ6
MEM_DQ9
MEM_DQ15
MEM_DQ13MEM_DQ14
MEM_DQ4
MEM_DQ12
MEM_A12
MEM_A5
MEM_COMP_P
MEM_COMP_N
+1.8V_IOPLLVDD+NB_IOPLLVDD
+1.8VS
+1.8V_MEM_VDDQ
+1.8V_MEM_VDDQ
+1.8V_MEM_VDDQ+1.8V_MEM_VDDQ
+1.8V_MEM_VDDQ
+1.8V_MEM_VDDQ
+1.8VS
+1.1VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
RS880 Side-Port DDR2 SDRAM
Custom
13 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
Side Port disable,VREF need connect to +1.8VS for DDR2
Layout Note: 50 mil for VSSDL
220 ohm @ 100MHz,2A
15mA
AMD recommends 200 Ohm @ 100Mhz
MEM_COMP_P and MEM_COMP_N tracewidth >=10mils and 10mils spacing fromother Signals in X,Y,Z directions
10/07 HP
10/22 HP
L44
FBMA-L11-160808-221LMT_06031 2
C2
00
1U
_0
40
2_
6.3
V4
Z
1
2
C2
01
0.1
U_
04
02
_1
6V
4Z
1
2
C1932.2U_0603_6.3V4Z
1
2
C2
04
0.1
U_
04
02
_1
6V
4Z
1
2
C1
99
1U
_0
40
2_
6.3
V4
Z
1
2
C1942.2U_0603_6.3V4Z
1
2
R7
4
1K
_0
40
2_
1%
12
L17
FBMA-L11-160808-221LMT_06031 2
R68
100_0402_1%
@
12
C1
98
0.1
U_
04
02
_1
6V
4Z
1
2 R7
2
1K
_0
40
2_
1%
12
C1950.1U_0402_16V4Z
1
2R70 40.2_0402_1%12
U5
K4N51163QG-HC25 FBGA84 ~D
@
VREFJ2
LDMF3
UDMB3
DQ14B1
DQ13D9
DQ12D1
DQ11D3
DQ10D7
DQ9C2
DQ8C8
DQ7F9
DQ6F1
DQ5H9
DQ4H1
DQ3H3
DQ2H7
DQ1G2
DQ0G8
BA1L3
BA0L2
A11P7
A10/APM2
A9P3
A8P8
A7P2
A6N7
A5N3
A4N8
A3N2
A0M8
A1M3
A2M7
RASK7
CKEK2
ODTK9
CSL8
CASL7
CKJ8
CKK8
WEK3
VDDQ10G9
VDDQ1A9
VDDQ2C1
VDDQ3C3
VDDQ4C7
VDDQ5C9
VDDQ6E9
VDDQ7G1
VSSQ1A7
VSSQ2B2
VSSQ3B8
VSSQ4D2
VSSQ5D8
VSSQ6E7
VSSQ7F2
VSSQ8F8
VSSQ9H2
VSSQ10H8
VSS1A3
VSS2E3
VSS3J3
VSS4N1
VSS5P9
UDQSA8
UDQSB7
LDQSE8
LDQSF7
VDDQ8G3
VDDQ9G7
VDD1A1
VDD2E1
VDD3J9
VDD4M9
VDD5R1
A12R2
DQ15B9
VDDLJ1
VSSDLJ7
NC#R8R8
NC#A2A2
NC#L1L1
NC#R3R3
NC#R7R7
NC#E2E2
C2
02
0.1
U_
04
02
_1
6V
4Z
1
2
C1
97
0.1
U_
04
02
_1
6V
4Z
1
2
C1961U_0603_10V6K
1
2
R69 40.2_0402_1%12
R7
1
1K
_0
40
2_
1%
12
R7
3
1K
_0
40
2_
1%
12
L16
FBMA-L11-160808-221LMT_06031 2
C203
22
U_
08
05
_6
.3V
6M
1
2
C2
05
0.1
U_
04
02
_1
6V
4Z
1
2
SBD_MEM/DVO_I/F
PAR 4 OF 6
U4D
RS880MN_FCBGA528
MEM_A0(NC)AB12
MEM_A1(NC)AE16
MEM_A2(NC)V11
MEM_A3(NC)AE15
MEM_A4(NC)AA12
MEM_A5(NC)AB16
MEM_A6(NC)AB14
MEM_A7(NC)AD14
MEM_A8(NC)AD13
MEM_A9(NC)AD15
MEM_A10(NC)AC16
MEM_A11(NC)AE13
MEM_A12(NC)AC14
MEM_A13(NC)Y14
MEM_BA0(NC)AD16
MEM_BA1(NC)AE17
MEM_BA2(NC)AD17
MEM_RASb(NC)W12
MEM_CASb(NC)Y12
MEM_WEb(NC)AD18
MEM_CSb(NC)AB13
MEM_CKE(NC)AB18
MEM_ODT(NC)V14
MEM_CKP(NC)V15
MEM_CKN(NC)W14
MEM_DM0(NC)W17
MEM_DM1/DVO_D8(NC)AE19
MEM_DQS0P/DVO_IDCKP(NC)Y17
MEM_DQS0N/DVO_IDCKN(NC)W18
MEM_DQS1P(NC)AD20
MEM_DQS1N(NC)AE21
MEM_DQ0/DVO_VSYNC(NC)AA18
MEM_DQ1/DVO_HSYNC(NC)AA20
MEM_DQ2/DVO_DE(NC)AA19
MEM_DQ3/DVO_D0(NC)Y19
MEM_DQ4(NC)V17
MEM_DQ5/DVO_D1(NC)AA17
MEM_DQ6/DVO_D2(NC)AA15
MEM_DQ7/DVO_D4(NC)Y15
MEM_DQ8/DVO_D3(NC)AC20
MEM_DQ9/DVO_D5(NC)AD19
MEM_DQ10/DVO_D6(NC)AE22
MEM_DQ11/DVO_D7(NC)AC18
MEM_DQ12(NC)AB20
MEM_DQ13/DVO_D9(NC)AD22
MEM_DQ14/DVO_D10(NC)AC22
MEM_DQ15/DVO_D11(NC)AD21
MEM_COMPP(NC)AE12
MEM_COMPN(NC)AD12
MEM_VREF(NC)AE18
IOPLLVDD18(NC)AE23
IOPLLVSS(NC)AD23
IOPLLVDD(NC)AE24
![Page 14: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/14.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CRT_HSYNC<11,16>
CRT_VSYNC<11,16>
AUX_CAL<11>
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
RS880 STRAPS
Custom
14 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)1. Disable (RS740/RS780) 0 : Enable (RS740/RS780)
RX780: Enables the Test Debug Bus using PCIE bus1 : Disable ( Can still be enabled using nbcfg register access )0 : Enable
DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb
Enables the Test Debug Bus using GPIO.1 : Disable (RS780) Enable (RX780)0 : Enable (RS780) Disable (RX780)PIN: RX780:NB_TV_C; RS740: RS740_DFT_GPIO5; RS780: VSYNC#
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
RS780 use HSYNC to enable SIDE PORT (internal pull high)
RS780 DFT_GPIO5 mux at CRT_VSYNC pull low to 3K
R77 150_0402_1%1 2
R79 3K_0402_5%@
12
R76 1K_0402_5%@12
R78 3K_0402_5%12
R75 1K_0402_5%12
![Page 15: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/15.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
NB_OSC_14.318M_R
CRD_REQ#
CLK_XTAL_OUT
CL
K_
XT
AL
_IN
CLK_PCIE_LAN_REQ#_R
CLK
_X
TA
L_
OU
T
NB_OSC_14.318M
CLK_XTAL_IN
CPPE_NC#_R
CPPE_NC#_R
CRD_REQ#
27M
_S
EL
NB
_O
SC
_1
4.3
18
M_
RS
EL_S
AT
A
CLK_PCIE_WLAN_REQ#
CLK_PCIE_WLAN_REQ#
CLK_48M_USB_R
CLK_CPU_BCLK_R
CLK_CPU_BCLK#_R
CLK_PCIE_LAN_REQ#_R
CLK_CPU_BCLK# <6>
CLK_CPU_BCLK <6>
SMB_CK_CLK0<4,6,8,9,21,30>SMB_CK_DAT0<4,6,8,9,21,30>
CLK_48M_USB <21>
CLK_PCIE_EXP<31>CLK_PCIE_EXP#<31>
CLK_PCIE_MCARD#<27>CLK_PCIE_MCARD<27>
NB_OSC_14.318M <11>
CLK_PCIE_LAN# <25>
NBGFX_CLK <11>
CLK_SBSRC_BCLK# <19>
CLK_SBLINK_BCLK <11>
CLK_NBHT <11>CLK_NBHT# <11>
CLK_PCIE_LAN <25>
NBGFX_CLK# <11>
CLK_SBLINK_BCLK# <11>
CLK_PCIE_WLAN_REQ# <27>
CPPE_NC#<20,21,31>
CLK_SBSRC_BCLK <19>
CLK_14M_KBC <33>
CLK_SB_14M <19>
CLK_14M_SIO <34>
CRD_REQ# <21,31>CLK_PCIE_CARD <31>CLK_PCIE_CARD# <31>
LP_EN# <21,25>
+3VS_CLK
+VDDCLK_IO
+3VS_CLK
+3VS
+VDDCLK_IO+1.2V_HT
+3VS_CLK
+3VS_CLK
+3
VS
_C
LK
+VDDCLK_IO
+3VS_CLK
+3VS_CLK
+V
DD
CL
K_
IO
+3VS_CLK
+VDDCLK_IO
+3VS_CLK
+3
VS
_C
LK
+3VS_CLK
+3VS_CLK
+VDDCLK_IO
+3
VS
_C
LK
+3
VS
_C
LK
+3VS
+3VS_CLK
+3VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
Clock generator
Custom
15 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
CPU
Routing the trace at least 10mil
NIC
NB
NB GFX
Media Card
SB LINK
For ICS need to pull high.
For SLG is NC
SB SRC
EXP
WLAN
100M DIFF(IN/OUT)*
HT_REFCLKP
RX780 RS780
NB CLOCK INPUT TABLE
100M DIFF100M DIFF100M DIFF
100M DIFF
14M SE (1.8V) 14M SE (1.1V)
NB CLOCKS
NC vref
HT_REFCLKN
REFCLK_P
REFCLK_N
GFX_REFCLK 100M DIFF
10/6 HP
10/22 HP
10/29 HP
add CLK_14M_SIO for super IO. Compal 12/4
change CLK_PCIE_CARD/# from Pin25,26 to Pin22,23 HP 12/8
C215
0.1U_0402_16V4Z
1
2
R523 33_0402_5%1 2
R94 10K_0402_5%
12
R87 0_0402_5%1 2
C213
1U_0402_6.3V4Z
1
2
R49310K_0402_5%
1 2
C210
0.1U_0402_16V4Z
1
2
R88261_0402_1%@
12
R84 33_0402_5%
12
C20622U_0805_6.3V6M
1
2
C66712P_0402_50V8J
@12
C223
0.1U_0402_16V4Z
1
2
C212
0.1U_0402_16V4Z
1
2C216
0.1U_0402_16V4Z
1
2
C66812P_0402_50V8J @
1 2
C2244.7P_0402_50V8C
1 2
C221
0.1U_0402_16V4Z
1
2
C220
0.1U_0402_16V4Z
1
2
L43
FBMA-L11-201209-221LMA30T_0805
1 2
C211
0.1U_0402_16V4Z
1
2
Y1
14.31818MHZ_20P_6X1430004201
12
R91 158_0402_1% 1 2
C209
0.1U_0402_16V4Z
1
2
Q6BDMN66D0LDW-7_SOT363-6
3
5
4
R968.2K_0402_5%
12
C226
22P_0402_50V8J
1
2
R93 90.9_0402_1%1 2
R49210K_0402_5%
12
R85 33_0402_5%1 2
ICS9LPRS476EKLFT_QFN72_10x10
U6
VDD_CPU54
VDD_CPU_I/O53
VSS_CPU52
CLKREQ_1#51
CLKREQ_2#50
VDD_A49
VS
S_
SR
C1
9
SR
C_
1#
20
SR
C_
12
1
SR
C_
0#
22
SR
C_
02
3
CL
KR
EQ
_0
#2
4
AT
IGC
LK
_2
#2
5
AT
IGC
LK
_2
26
VS
S_
AT
IG2
7
VD
D_
AT
IG_
IO2
8
VD
D_
AT
IG2
9
AT
IGC
LK
_1
#3
0
AT
IGC
LK
_1
31
AT
IGC
LK
_0
#3
2
VS
S_
SB
_S
RC
36
SB
_S
RC
_1
35
SB
_S
RC
_1
#3
4A
TIG
CL
K_
03
3
VSS_A48
VSS_SATA47
SRC_6/SATA46
SRC_6#/SATA#45
VDD_SATA44
CLKREQ_3#43
CLKREQ_4#42
SB_SRC_SLOW#41
SB_SRC_040
SB_SRC_0#39
VDD_SB_SRC38
VDD_SB_SRC_IO37
RE
F_
1/S
EL
_S
AT
A6
4
RE
F_
2/S
EL
_2
76
3
VD
D_
RE
F6
2
VD
D_
HT
T6
1
HT
T_
0/6
6M
_0
60
HT
T_
0#
/66
M_
15
9
VS
S_
HT
T5
8
PD
#5
7
CP
U_
K8
_0
56
CP
U_
K8
_0
#5
5
SCL1
SDA2
VDD_DOT3
SRC_7#/27M4
SRC_7/27M_SS5
VSS_DOT6
SRC_5#7
SRC_58
SRC_4#9
SRC_410
VSS_SRC11
VDD_SRC_IO12
SRC_3#13
SRC_314
SRC_2#15
SRC_216
VDD_SRC17
VDD_SRC_IO18
RE
F_
0/S
EL
_H
TT
66
65
VS
S_
RE
F6
6X
TA
L_
IN6
7X
TA
L_
OU
T6
8V
DD
_4
86
94
8M
Hz_
17
04
8M
Hz_
07
1V
SS
_4
87
2
GN
D7
3
C219
0.1U_0402_16V4Z
1
2
R928.2K_0402_5%
12
C218
0.1U_0402_16V4Z
1
2
R86 4.7K_0402_5%
1 2
R95 10K_0402_5%
12
C222
0.1U_0402_16V4Z
1
2
C217
0.1U_0402_16V4Z
1
2
Q6A
DMN66D0LDW-7_SOT363-6
6 1
2
C208
0.1U_0402_16V4Z
1
2
C207
0.1U_0402_16V4Z
1
2
R82 22_0402_5%
1 2
R90 10K_0402_5%1 2
L45
FBMA-L11-201209-601LMT_0805~D
1 2
C225
22P_0402_50V8J
1
2
R89 0_0402_5%1 2
C21422U_0805_6.3V6M
1
2
![Page 16: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/16.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
D_D DCDATA
D_DDCC LK
HS Y NC
V SYNC
D_ HSYNC
D_VSYNC
D_REDD_G REEN
D_G REEN
D_RED
RE D
GR EEN
B LUE
D _BLUE
D _BLUE
B LUE
GR EEN
RE D
D_ HSYNC
D_VSYNC
CRT_HSY NC<11,14>
CRT_V SYNC<11,14>
D_ HSYNC <32>
D_VSYNC <32>
CRT_DDC_DATA <11,32>
CRT_DDC_CLK <11,32>
D_DDCDATA<11,32>
D_DDCCLK<11,32>
VGA_RED<32>
VGA_GRN<32>
VGA_BLU<32>
D_RED<11>
D_GREEN<11>
D_BLUE<11>
R ED_R <32>
GRE EN_R <32>
B LUE_R <32> +CRTVDD+RCRT_VCC+5VS
+5VS
+5VS
+5VS
+CRTVDD
+CRTVDD
+CRTVDD
Title
Size Document Number R e v
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
CRT Connector
16 54Thursday, August 27, 2009
2008/09/15 2009/09/15Compal Electronics, Inc.
layout note: D_HSYNC
& D_VSYNC should be
routed to docking
connector then to VGA
connector
L Place cloce to NB
W=40mils
L Place cloce to NB
L Place cloce to NB
Place cloce to JCRT1
10/23 HP
change to LCL filtter 10/23 HP
10/29 HP
because RS880 confirmed +5V torelence on I2C DDC, level-shifter is not required. (DB2 11/28)
01/16 ESD
R9
81
50
_0
40
2_
1%
12
R477 0_0805_5%1 2
R100 0_0402_5%
1 2
C2340.1U_0402_16V4Z
1 2
L19CS0805-68NJ-S_0805
1 2
D6
CM1293A-02SR_SOT143-4@
GND1
IO12
IO23
VIN4
L21CS0805-68NJ-S_0805
1 2
R9
71
50
_0
40
2_
1%
12
C2
31
27
P_
04
02
_5
0V
8J
1
2
L24CS0805-68NJ-S_0805
1 2
D7
CM1293A-02SR_SOT143-4@
GND1
IO12
IO23
VIN4
C237
5P_0402_50V8C
1
2
R473 0_0805_5%1 2
U7M74VHC1GT125DF2G SC70
A2
Y4O
E#
1
G3
P5
R4740_0805_5%
1 2
C236
5P_0402_50V8C
1
2
R105 0_0402_5%
1 2
R4720_0805_5%
1 2
D4CH491D_SC59
2 1
R475 0_0805_5%1 2
C6
88
10
P_
04
02
_5
0V
8J
@
1
2
C2350.1U_0402_16V4Z
1 2
L23CS0805-68NJ-S_0805
1 2
D5
CM1293A-02SR_SOT143-4@
GND1
IO12
IO23
VIN4
R4760_0805_5%
1 2
R1
03
4.7
K_
04
02
_5
%
12
L22CS0805-68NJ-S_0805
1 2
U8
M74VHC1GT125DF2G SC70
A2
Y4O
E#
1
G3
P5
R4
61
14
0_
04
02
_1
%
12
R9
91
50
_0
40
2_
1%
12
C6
87
10
P_
04
02
_5
0V
8J
@
1
2
R4
62
14
0_
04
02
_1
%
12
C6
86
10
P_
04
02
_5
0V
8J
@
1
2
L20CS0805-68NJ-S_0805
1 2
C227
0.1U_0402_16V4Z
1
2
R4
63
14
0_
04
02
_1
%
12
F11.1A_6VDC_FUSE
21
R1
04
4.7
K_
04
02
_5
%
12
JCRT1
SUYIN_070912HR015S239ZR_15P
C ONN@
61117
1228
1339
144
10155
1617
C2
33
27
P_
04
02
_5
0V
8J
1
2
C2
32
27
P_
04
02
_5
0V
8J
1
2
![Page 17: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/17.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CAMERA_OFF#
USB20_P4_R
U SB20_N4_RENABLT
LI D_SW#
D ISP_OFF#
DDC2_ CLK
D DC2_DATA
DAC _BRIG
INV_PWM
USB20_P4_RU SB20_N4_R
INV_PWMD ISP_OFF#
DAC _BRIG
D DC2_DATADDC2_ CLK
CAMERA_OFF#
USB20_P4_RU SB20_N4_R
ENAVDD<11>
ENABLT <11>
LID_SW# <21,28,33>INV_PWM <11>
LVDS_BCLK+ <11>LVDS_BCLK- <11>
LVDS_A2-<11>LVDS_A2+<11>
LVDS_A1-<11>LVDS_A1+<11>
LVDS_A0-<11>LVDS_A0+<11>
LVDS_ACLK-<11>LVDS_ACLK+<11>
LVDS_B0+ <11>LVDS_B0- <11>
LVDS_B1+ <11>LVDS_B1- <11>
LVDS_B2+ <11>LVDS_B2- <11>
DDC2_DATA <11>DDC2_CLK <11>
CAMERA_OFF<20>
USB20_P4<21>USB20_N4<21>
+LCDVDD+LCDV DD +3VS
+5VS +5V_WEBCAM
+5VS
+3VS+LCDV DD INVPWR_B+ B+
+3VS
+3VS
+3VS
+5V_WEBCAM
INVPWR_B+
+LCDV DD
+5VS
+3VS
Title
Size Document Number R e v
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
LCD CONN & Q-Switch & GPIO Ext.
17 54Thursday, August 27, 2009
2008/09/15 2009/09/15Compal Electronics, Inc.
LCD POWER CIRCUIT
LCD/PANEL BD. CONN.
For CCFL panel
Compal ME request 12/03
solved panel flashing issue HP 2/6
ESD 2/18
HP, 4/8
4/11 HP
4/11 HP
HP, 4/17
compal EMI , 6/13
JLVDS1
ACES_87216-4016_40PC ONN@
4242
11
33
55
77
99
1111
1313
1515
1717
1919
2121
2323
2525
2727
2929
3131
3333
3535
3737
3939
22
44
66
88
1010
1212
1414
1616
1818
2020
2222
2424
2626
2828
3030
3232
3434
3636
3838
4040
4141
C6
72
47
P_
04
02
_5
0V
8J
@
12
C2
45
4.7
U_
08
05
_1
0V
4Z
1
2
C6
55
47
P_
04
02
_5
0V
8J
@
12
R5061K_0402_1%
12
R108100K_0402_1%
12
D 10
CM1293A-02SR_SOT143-4
GND1
IO12
IO23
VIN4
C6
58
68
0P
_0
40
2_
50
V7
K
1
2
R4534.7K_0402_5%
1 2
R116100_0402_1%
12
C2
42
1U
_0
60
3_
10
V4
Z
1
2
R437 0_0402_5%@
1 2
C249 0.1U_0402_16V4Z1 2
C6
56
68
0P
_0
40
2_
50
V7
K
1
2
G
D S
Q26AP2301GN 1P_SOT23
2
1 3
C653680P_0402_50V7K
1
2
R438 0_0402_5%@1 2
D 42
CH751H-40PT_SOD323-2
2 1
Q28DTC124EKAT146_SC59-3
IN2
OU
T1
GN
D3
Q7A
DMN66D0LDW-7_SOT363-6
61
2
R540
2K_0402_5%
1 2
C6
57
47
P_
04
02
_5
0V
8J
@
12
C654680P_0402_50V7K
12
C2
44
0.1
U_
04
02
_1
6V
4Z
1
2
L49
WCM2012F2S-900T04_0805
11
22
33
44
R117 1M_0402_5%1 2
R118 47K_0402_5%1 2
R439 0_0805_5%1 2
R119100K_0402_1%
12
C2514.7U_0805_10V4Z
1
2
R4524.7K_0402_5%
1 2
C2524.7U_0805_10V4Z
1
2
R5071.8K_0402_1%
12
R1
12
4.7
K_
04
02
_5
% 1
2
C2500.1U_0402_16V4Z
1
2
C2
43
0.0
1U
_0
40
2_
16
V7
K
1
2
R447
100K_0402_1%
12
Q7B
DMN66D0LDW-7_SOT363-6
3
5
4
![Page 18: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/18.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DP AUX+
DP AUX-
NB_CAD
HDMI_HPD
NB_CAD
R_DPA_TXN0
R_DPA_TXN1
R_DPA_TXP0
R_DPA_TXN3
R_DPA_TXN2
R_DPA_TXP1
R_DPA_TXP3
R_DPA_TXP2
DP AUX+
DP AUX-HDMI_HPD
DOCK_ID
DOCK_ID
DPB_HPD
HPD <11>
DPA_TXN2<10>
DPA_TXP1<10>
DPA_TXP3<10>
DPA_TXP2<10>
DPA_TXN0<10>
DPA_TXN3<10>
DPA_TXN1<10>
DPA_TXP0<10>
HDMIDAT_UMA<11,32>
HDMICLK_UMA<11,32>
DOCK_ID <20,32>
DPB_HPD <32>
+3VS
B+ +3VS
+DPA_3V
+DPA_VCC
+3VS
+3VS
B+
B+
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
Display port
Custom
18 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
10/17 HP
Display port Connector
10/25 HPHP 12/02
HP 12/02
add level sfit for displayport. HP 12/15
HP 2/6
compal 2/19
HP, 611
Q9B
DMN66D0LDW-7_SOT363-6
3
5
4
Q20A
DMN66D0LDW-7_SOT363-6
6 1
2
C7020.1U_0402_16V4Z 12
R4
85
0_
12
06
_5
%
@
12
C7191U_0603_10V6K
@
12
R4
88
1M
_0
40
2_
5%
12
Q22B
DMN66D0LDW-7_SOT363-6
3
5
4
C503
0.1U_0402_16V4Z
12
Q113B
DMN66D0LDW-7_SOT363-6
3
5
4
Q20B
DMN66D0LDW-7_SOT363-6
3
5
4
R409100K_0402_5%
12
R568470K_0402_5%
1 2
R410
100K_0402_5%
12
F2
NA
NO
SM
DC
05
0F
0.5
A 1
3.2
V P
OL
Y-F
US
E
21
Q113A
DMN66D0LDW-7_SOT363-6 61
2
D4
6S
DM
10
U4
5-7
_S
OD
52
3-2
@
21
Q21A
DMN66D0LDW-7_SOT363-6
6 1
2
Q98A
DMN66D0LDW-7_SOT363-6 61
2
R412
100K_0402_5%
12
R569
470K_0402_5%
12
R4
84
0_
12
06
_5
%
12
JDP1
MOLEX_105020-0001_20P
DP_PWR20
RTN19
HP_DET18
AUX_CH-17
GND16
AUX_CH+15
GND14
CA_DET13
LAN3-12
LAN3_shield11
LAN3+10
LAN2-9
LAN2_shield8
LAN2+7
LAN1-6
LAN1_shield5
LAN1+4
LAN0-3
LAN0_shield2
LAN0+1
GND24
GND23
GND22
GND21
C6960.1U_0402_16V4Z 12
C7010.1U_0402_16V4Z 12
C6950.1U_0402_16V4Z 12
C6970.1U_0402_16V4Z 12
R4
87
5.1
M_
04
02
_5
%
12
Q22A
DMN66D0LDW-7_SOT363-6
61
2Q98B
DMN66D0LDW-7_SOT363-6
3
5
4
R486
200K_0402_5%
12
C6
93
0.0
1U
_0
40
2_
16
V7
K
1
2
C6980.1U_0402_16V4Z 12
C502
0.1U_0402_16V4Z
12
R411
100K_0402_5%
12
C6
94
10
U_
08
05
_1
0V
4Z
1
2
Q21B
DMN66D0LDW-7_SOT363-6
3
5
4
C6990.1U_0402_16V4Z 12
R535200K_0402_5%
1 2
C7000.1U_0402_16V4Z 12
Q9A
DMN66D0LDW-7_SOT363-6
61
2
R125100K_0402_5%
12
![Page 19: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/19.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
PLT_RST#NB_RST#_R
SB_RX0P_CSB_RX0N_CSB_RX1P_CSB_RX1N_C
CPU_LDT_REQ#
NB_RST#_R
SB_32KHI
SB_32KHO
NB_RST#_R
+SB_PCIEVDD
PCI_PIRQH#
SB_RX2P_CSB_RX2N_CSB_RX3P_CSB_RX3N_C
CLK_PCI_EC_RLPCCLK1
SB_32KHI
SB_32KHO
PCI_AD23PCI_AD24PCI_AD25PCI_AD26PCI_AD27PCI_AD28
H_PWRGD_SBH_PWRGD_SB
CLK_PCI_EC
CLK_PCI_EC
LPC_LDRQ#0
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0
BMREQ#BMREQ#
CLK_PCI_TPMCLK_PCI_SIOPCI_CLK2CLK_PCI_KBCCLK_PCI_DBPCI_CLK5
CLK_PCI_KBC
PCI_CLK5
CLK_PCI_TPMCLK_PCI_SIOPCI_CLK2
CLK_PCI_DB
CLK_PCI_SIO_RPCI_CLK2_R
PCI_CLK5_R
CLK_PCI_TPM_R
CLK_PCI_DB_RCLK_PCI_KBC_R
LPCCLK1
PROCHOT#
PROCHOT#
LPCCLK1
PCI_CLK5 <22>
PLT_RST# <11,25,27,29,31,34>
CLK_PCI_DB <22,29>
SB_RX0P<10>SB_RX0N<10>SB_RX1P<10>SB_RX1N<10>
SB_TX1P<10>SB_TX1N<10>
SB_TX0P<10>SB_TX0N<10>
SB_TX2P<10>SB_TX2N<10>SB_TX3P<10>SB_TX3N<10>
SB_RX2P<10>SB_RX2N<10>SB_RX3P<10>SB_RX3N<10>
RTC_CLK <22>
LPC_LFRAME# <27,29,33,34>
LPC_LAD1 <27,29,33,34>LPC_LAD2 <27,29,33,34>
LPC_LAD0 <27,29,33,34>
LPC_LAD3 <27,29,33,34>
LDT_STOP#<6,11>
CPU_LDT_REQ#<6,11>
SIRQ <29,33,34>
CLK_SBSRC_BCLK<15>CLK_SBSRC_BCLK#<15>
LDT_RST#<6>
ACCEL_INT# <30>
PCI_AD23 <22>
PCI_SERR# <29,33>
PCI_AD24 <22>PCI_AD25 <22>PCI_AD26 <22>PCI_AD27 <22>PCI_AD28 <22>
H_PWRGD_CPU<6>
CLK_PCI_EC <22>
LPC_LDRQ#0 <34>
PCI_RST# <27,29>
CLK_SB_14M<15>
CLK_PCI_TPM <29>CLK_PCI_SIO <34>
CLK_PCI_KBC <22,33>PCI_CLK2 <22>
PM_CLKRUN# <29,33,34>
CLK_PCI_DEBUG <27>
LPCCLK1 <22>
+3VALW
+PCIE_VDDR
+1.2V_HT
+3VS
+RTCVCC
+3VS
BATT1.1+VREG3_51125+RTCVCC
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
SB710-PCIE/PCI/ACPI/LPC/RTC
Custom
19 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
EC & Debug
STRAP PIN
STRAP PIN
Check AMD need pull low or not
Close to SB
Close to SB
W=20mils
Place near IBEX-M
W=20milsW=20mils
for 80 port debug card 10/31
for battery life cycle issue ,HP 2/11
R147 22_0402_5%
1 2
PC
I E
XP
RE
SS
IN
TE
RF
AC
E
Part 1 of 5
SB710
PC
I IN
TE
RF
AC
E
LP
CR
TC
CP
U
RT
C X
TA
L
PC
I C
LK
S
CL
OC
K G
EN
ER
AT
OR
U10A
218S7EALA11FG_BGA528_SB700
A_RST#N2
PCIE_RX2PR20
PCIE_RX2NR21
PCIE_RX3PR18
PCIE_TX3NT22
PCIE_TX3PT23
PCIE_TX2NU24
PCIE_TX2PU25
PCIE_RX1PU19
PCIE_RX1NV19
PCIE_RX0PU22
PCIE_RX0NU21
PCIE_TX1NV25
PCIE_TX1PV24
PCIE_TX0NV22
PCIE_TX0PV23
PCIE_RCLKP/NB_LNK_CLKPN25
PCIE_RCLKN/NB_LNK_CLKNN24
PCIE_CALRPT25
PCIE_CALRNT24
PCIE_PVDDP24
GPP_CLK1NL19
X1A3
X2B3
VBATB2
GPP_CLK0NJ18
GPP_CLK2PM19
ALLOW_LDTSTPF23
CPU_HT_CLKNM18
GPP_CLK2NM20
SLT_GFX_CLKPM23
CPU_HT_CLKPP17
LDT_RST#G24
PCICLK0P4
PCICLK1P3
PCICLK2P1
PCICLK3P2
PCIRST#N1
CBE0#W2
CBE1#U7
CBE2#AA7
CBE3#Y1
FRAME#AA6
DEVSEL#W5
IRDY#AA5
TRDY#Y5
PARU6
STOP#W6
PERR#W4
REQ0#AC3
REQ1#AD4
REQ2#AB7
REQ3#/GPIO70AE6
GNT0#AD2
GNT1#AE4
GNT2#AD5
GNT3#/GPIO72AC6
SERR#V7
CLKRUN#AD6
LAD0H24
LAD1H23
LAD2J25
LAD3J24
LFRAME#H25
LDRQ0#H22
SERIRQV15
PCICLK4T4
LPCCLK0G22
LPCCLK1E22
AD0U2
AD1P7
AD2V4
AD3T1
AD4V3
AD5U1
AD6V1
AD7V2
AD8T2
AD9W1
AD10T9
AD12R7
AD13R5
AD14U8
AD15U5
AD16Y7
AD17W8
AD18V9
AD19Y8
AD20AA8
AD21Y4
AD22Y3
AD23Y2
AD24AA2
AD25AB4
AD26AA1
AD27AB3
AD28AB2
AD29AC1
AD30AC2
AD31AD1
AD11R6
REQ4#/GPIO71AB6
GNT4#/GPIO73AE5
LDRQ1#/GNT5#/GPIO68AB8
GPP_CLK1PL20
RTCCLKC3
PCIE_RX3NR17
INTE#/GPIO33AD3
INTF#/GPIO34AC4
INTG#/GPIO35AE2
INTH#/GPIO36AE3
LOCK#V5
PCIE_PVSSP25
PCICLK5/GPIO41T3
BMREQ#/REQ5#/GPIO65AD7
NB_HT_CLKPM24
LDT_PGF22
LDT_STP#G25
GPP_CLK3NP22
INTRUDER_ALERT#C2
NB_DISP_CLKPK23
25M_48M_66M_OSCL18
GPP_CLK0PJ19
NB_HT_CLKNM25
SLT_GFX_CLKNM22
GPP_CLK3PN22
14M_X1J21
14M_X2J20
NB_DISP_CLKNK22
PROCHOT#F24
R148 22_0402_5%
1 2
R15910K_0402_5% @1 2
C272 0.1U_0402_16V7K 1 2
C268 0.1U_0402_16V7K 1 2
Y2
32.768KHZ_12.5PF_Q13MC14610050_10PPM
OSC4
OSC1
NC3
NC2
C276 22P_0402_50V8J 1 2
R165 10K_0402_5%12
L29FBMA-L11-201209-221LMA30T_0805
1 2
R167
0_0402_5%
1 2
R451 0_0402_5%12
R149 33_0402_5%
12
R155 1K_0402_5%
12
R16310K_0402_5% @1 2
C281
18P_0402_50V8J
1 2
R142 8.2K_0402_5%@1 2
R456
1K_0402_5%
1 2
C267 0.1U_0402_16V7K 1 2
C676 12P_0402_50V8J@
1 2
C264 0.1U_0402_16V7K 1 2
C274 22P_0402_50V8J 1 2
C265 0.1U_0402_16V7K 1 2
C271 22P_0402_50V8J 1 2
C282
18P_0402_50V8J
1 2
C277 22P_0402_50V8J 1 2
C2801U_0402_6.3V4Z
1
2
C263
0.1U_0402_16V4Z@
12
U9
NC7SZ08P5X_NL_SC70-5@
B2
A1
Y4
P5
G3
C679
0.1U_0402_16V4Z 1
2
R144 22_0402_5%
1 2
C270 0.1U_0402_16V7K 1 2
R143 22_0402_5%
1 2
R1661M_0402_5%1 2
R151 2.05K_0402_1% 12
C273 22P_0402_50V8J 1 2
C278 12P_0402_50V8J1 2
C27910U_0805_10V4Z
1
2
R495 33_0402_5%
1 2
R156 0_0402_5%
12
R145 22_0402_5%
1 2
C269 0.1U_0402_16V7K 1 2
R146 22_0402_5%
1 2
D43
DAN202U_SC70
2
31
C681
1U_0603_10V4Z
1
2
R16010K_0402_5% @1 2
R15710K_0402_5% @1 2
R150 562_0402_1% 12
R152 20M_0402_5%@
1 2
R154
20M_0402_5%
12
C275 22P_0402_50V8J 1 2
R153 33_0402_5%
1 2
R158 33_0402_5%
1 2
JBATT1E-T_3801-E02N-01R_2P
CONN@
1 2
C266 0.1U_0402_16V7K 1 2
R16410K_0402_5%1 2
R16110K_0402_5% @1 2
![Page 20: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/20.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+XTLVDD_SATA
+SB_AVDD
SATA_STX_DRX_P1SATA_STX_DRX_N1
SATA_STX_DRX_P0SATA_STX_DRX_N0
SATA_X2
SATA_X1
SATA_CAL
SATA_X2
SATA_X1
SATA_SRX_C_DTX_N0SATA_SRX_C_DTX_P0
SATA_SRX_C_DTX_N1SATA_SRX_C_DTX_P1
SATA_STX_DRX_P2
SATA_SRX_DTX_N2SATA_SRX_DTX_P2
SATA_STX_DRX_N3SATA_STX_DRX_P3
SATA_SRX_DTX_N3SATA_SRX_DTX_P3
+PLLVDD_SATA
GPIO53
GPIO53 GPIO52
GPIO52
CRD_REQ#_RCPPE_NC#
SATA_STX_DRX_N2
SATA_STX_C_DRX_P0<24>SATA_STX_C_DRX_N0<24>
SATA_SRX_C_DTX_P0<24>SATA_SRX_C_DTX_N0<24>
SATA_LED#<31,32>
SATA_STX_C_DRX_P1<24>SATA_STX_C_DRX_N1<24>
SATA_SRX_C_DTX_N1<24>SATA_SRX_C_DTX_P1<24>
SATA_STX_DRX_P2<32>SATA_STX_DRX_N2<32>
SATA_SRX_DTX_N2<32>SATA_SRX_DTX_P2<32>
SATA_STX_DRX_P3<32>SATA_STX_DRX_N3<32>
SATA_SRX_DTX_N3<32>SATA_SRX_DTX_P3<32>
KBC_SPI_SO <33>KBC_SPI_SI <33>KBC_SPI_CLK <33>
KBC_SPI_CS0# <33>
NPCI_RST# <33,34>
WXMIT_OFF# <27>
CAMERA_OFF <17>
HDD_HALTLED <31>
ADP_PRES <25,31,33,36,39,46>
CRD_REQ#_R <21>CPPE_NC# <15,21,31>
DOCK_ID <18,32>
+3VALW
+3VS
+1.2V_HT
+3VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
SB710 SATA/IDE/SPI
Custom
20 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
HDD
ODD
Dock
Dock
remove UWB , 10/21 HP
change to 0603 for layout placement
HP 2/5
VRAM ID, Compal 2/17
VRAM ID GPIO52 GPIO53
Samsung 128MB
Hynix 64MB 0
1
0
0
1
Hynix 128MB
0
1 1
(2nd source)
(main source)
HP 4/9
(2nd source)
Samsung 128MB (2nd source)
HP 5/29
HP 5/29
HP 5/29
HP, 6/10
HP, 6/10
HP, 6/10
C285 0.01U_0402_25V7K
1 2
R170 150K_0402_5%1 2
C2931U_0402_6.3V4Z
1
2
C2972.2U_0603_6.3V4Z
1
2
R549
10K_0402_5%
@
12
R176
10K_0402_5%
<>
@
12
Y3
25MHz_20pF_6X25000017
12
C28410P_0402_50V8J
12
C677
10U_0603_6.3V6M
1
2
R573 0_0402_5%@
1 2
R178 10K_0402_5%12
L30
FBMA-L11-201209-221LMA30T_0805
1 2
R172 10K_0402_5%
1 2
R175
100K_0402_5%
12
C288 0.01U_0402_25V7K
1 2
R177 150_0402_1%1 2
C286 0.01U_0402_25V7K
1 2
C287 0.01U_0402_25V7K
1 2
C28310P_0402_50V8J
12
R171 1K_0402_1%
12
R169
10M_0402_5%
12
R551
10K_0402_5%
@
12
AT
A 6
6/1
00
/13
3
Part 2 of 5
SB710
SA
TA
PW
RS
ER
IAL
AT
A
SP
I R
OM
HW
MO
NIT
OR
U10B
218S7EALA11FG_BGA528_SB700
IDE_IORDYAA24
IDE_IRQAA25
IDE_A0Y22
IDE_A1AB23
IDE_A2Y23
IDE_DACK#AB24
IDE_DRQAD25
IDE_IOR#AC25
IDE_IOW#AC24
IDE_CS1#Y25
IDE_CS3#Y24
IDE_D0/GPIO15AD24
IDE_D1/GPIO16AD23
IDE_D2/GPIO17AE22
IDE_D3/GPIO18AC22
IDE_D4/GPIO19AD21
IDE_D5/GPIO20AE20
IDE_D6/GPIO21AB20
IDE_D7/GPIO22AD19
IDE_D8/GPIO23AE19
IDE_D9/GPIO24AC20
IDE_D10/GPIO25AD20
IDE_D11/GPIO26AE21
IDE_D12/GPIO27AB22
IDE_D13/GPIO28AD22
IDE_D14/GPIO29AE23
IDE_D15/GPIO30AC23
XTLVDD_SATAW12
PLLVDD_SATAAA11
SATA_TX2PAB12
SATA_TX2NAC12
SATA_RX2PAD12
SATA_RX2NAE12
SATA_TX3PAD13
SATA_TX3NAE13
SATA_RX3PAC14
SATA_RX3NAB14
SATA_TX0PAD9
SATA_TX0NAE9
SATA_RX0NAB10
SATA_RX0PAC10
SATA_TX1PAE10
SATA_TX1NAD10
SATA_RX1NAD11
SATA_RX1PAE11
SATA_CALV12
SATA_X1Y12
SATA_X2AA12
SATA_ACT#/GPIO67W11
SPI_DI/GPIO12G6
SPI_DO/GPIO11D2
SPI_CLK/GPIO47D1
SPI_HOLD#/GPIO31F4
SPI_CS1#/GPIO32F3
FANOUT1/GPIO48M5
FANOUT2/GPIO49M7
FANIN0/GPIO50P5
FANIN1/GPIO51P8
FANIN2/GPIO52R8
LAN_RST#/GPIO13U15
ROM_RST#/GPIO14J1
VIN0/GPIO53A4
VIN1/GPIO54B4
VIN2/GPIO55C4
VIN3/GPIO56D4
VIN4/GPIO57D5
VIN5/GPIO58D6
VIN6/GPIO59A7
VIN7/GPIO60B7
TEMPIN0/GPIO61B6
TEMPIN1/GPIO62A6
TEMPIN2/GPIO63A5
TEMPIN3/TALERT#/GPIO64B5
FANOUT0/GPIO3M8
AVDDF6
AVSSG7
TEMP_COMMC6
SATA_TX4PAE14
SATA_TX4NAD14
SATA_RX4NAD15
SATA_RX4PAE15
SATA_TX5PAB16
SATA_TX5NAC16
SATA_RX5NAE16
SATA_RX5PAD16
R550
10K_0402_5%
@
12
G
D
S
Q112
2N7002_SOT23-3
2
13
C294
1U_0402_6.3V4Z
1
2
C2951U_0402_6.3V4Z
1
2
L31
FBMA-L11-201209-221LMA30T_0805
1 2
C2960.1U_0402_16V4Z
1
2
![Page 21: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/21.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
NB_PWRGD
USB20_N0USB20_P0
USB20_N1USB20_P1
USB20_P2USB20_N2
USB20_P3USB20_N3
USB20_N5USB20_P5
USB20_N6USB20_P6
USB20_P7USB20_N7
USB20_N8USB20_P8
SMB_CK_DAT1SMB_CK_CLK1
SUS_STAT#
H_THERMTRIP#
USB_RCOMP
SMB_CK_CLK0
SMB_CK_DAT0
SUS_STAT#
HDA_SDIN1HDA_SDIN0
HDA_SDOUT
HDABITCLK
HDA_SYNC
HDARST#
SMB_CK_DAT0SMB_CK_CLK0
SMB_CK_CLK1
SMB_CK_DAT1
HDA_BIT_CLK_CODEC
HDA_BITCLK_MDC
HDA_SDOUT_MDC
HDA_SDOUT_CODEC
USB20_N4USB20_P4
PM_RSMRST#
XMIT_OFF#
USB20_P13USB20_N13
WOL_EN
SATA_ISO#
HDA_SDIN0HDA_SDIN1
SATA_ISO#
CRD_REQ#_R
CRD_REQ#_R
USB20_P11USB20_N11
SLP_S5#
CPPE_NC#<15,20,31>
LANLINK_STATUS#<25,26,32>
USB20_N0 <30>USB20_P0 <30>
USB20_N1 <31>USB20_P1 <31>
USB20_P2 <31>USB20_N2 <31>
USB20_P3 <30>USB20_N3 <30>
USB20_N5 <30>USB20_P5 <30>
USB20_N6 <32>USB20_P6 <32>
USB20_P7 <27>USB20_N7 <27>
USB20_N8 <32>USB20_P8 <32>
HDARST#<22>
PM_RSMRST#<33,42>
SMB_CK_DAT0<4,6,8,9,15,30>SMB_CK_CLK0<4,6,8,9,15,30>
H_THERMTRIP#<6>
HDA_SPKR<31>
CLK_48M_USB <15>
SUS_STAT#<11>
HDA_SDIN0<31>HDA_SDIN1<28>
HDA_SDOUT_MDC<28>HDA_SDOUT_CODEC<31>
HDA_BIT_CLK_CODEC<31>HDA_BITCLK_MDC<28>
HDA_SYNC_MDC<28>HDA_SYNC_CODEC<31>
HDA_RST#_CODEC<31>HDA_RST#_MDC<28>
SB_PWRGD<6,33,45>
RUNSCI_EC#<33>
GPIO16 <22>GPIO17 <22>
USB20_N4 <17>USB20_P4 <17>
BT_OFF<30>
SLP_S5#<36,42>SLP_S3#<31,33,36,39>
WLAN_OFF<27>XMIT_OFF#<27>
NB_PWRGD<11>
USB20_P13 <29>USB20_N13 <29>
WOL_EN<25>
LAN_PCIE_WAKE#<25,27,31>
KB_RST#<33>
GATEA20<33>
PREP#<32>
LOM_PWR#<26>
THERM_SC#<6>
ON/OFFBTN#<25,28,32>
LP_EN#<15,25>
CRD_REQ#<15,31>
USB20_P11 <30>USB20_N11 <30>
CRD_REQ#_R <20>
LID_SW#<17,28,33>
+3VS
+3VALW
+3VS
+3VS
+3VALW
+3VALW
+3VL
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
SB710 USB/AC97
Custom
21 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
STRAP PIN
USB-0 Left side (S/W Debug Port)
USB-5 left side
USB-4 USB Camera
USB-8 Dock
STRAP PIN
USB-3 left side
USB-2 daughter board
USB-1 Express card
USB-6 Dock
STRAP PIN
USB-7 MiniCard(WWAN)
USB-13 FPR
10/21 HP
delete USB20_P10/N10 for remove NIC8075. HP 12/5
change +3VALW to +3VL Compal 2/3
HP 2/6
USB-11 Bluetooth
HP 4/7
HP, 4/13
HP, 7/3
C299 82P_0402_50V8J
1 2
R188 10K_0402_5%12
U11
SN74LVC1G17DBVR SOT23-5
O4
I2
P5
G3
NC1
R196 33_0402_5%
1 2
G
D SQ110
2N7002_SOT23-3
2
1 3
R182 2.2K_0402_5% 1 2
R563 10K_0402_5%12
C298
4.7U_0603_6.3V6M
1 2
G
D
S
Q29
2N7002_SOT23-3
2
13
C302 82P_0402_50V8J
1 2
R181 4.7K_0402_5%
1 2
R189 2.2K_0402_5% 1 2
C300 82P_0402_50V8J
1 2
R187 2.2K_0402_5% 1 2
R191 10K_0402_5%12
R455 10K_0402_5%12
R198 33_0402_5%
1 2
R185 10K_0402_5%12
C301 82P_0402_50V8J
1 2
R195 33_0402_5%
1 2
R192 33_0402_5%
1 2
R190 100K_0402_5%1 2
R184 10K_0402_5%12
US
B 2
.0
Part 4 of 5SB710
AC
PI
/ W
AK
E U
P E
VE
NT
S
GP
IO
HD
AU
DIO
US
B O
C
US
B 1
.1
US
B M
ISC
INT
EG
RA
TE
D u
C
INT
EG
RA
TE
D u
C
U10D
218S7EALA11FG_BGA528_SB700
USBCLK/14M_25M_48M_OSCC8
USB_RCOMPG8
USB_OC6#/IR_TX1/GEVENT6#B9
USB_HSD5PC12
USB_HSD5ND12
USB_HSD4PB12
USB_HSD4NA12
USB_HSD3PG12
USB_HSD3NG14
USB_HSD2PH14
USB_HSD2NH15
USB_HSD1PA13
USB_HSD1NB13
USB_HSD0PB14
USB_HSD0NA14
USB_OC4#/IR_RX0/GPM4#A8
USB_OC3#/IR_RX1/GPM3#A9
USB_OC1#/GPM1#F8
USB_OC2#/GPM2#E5
USB_HSD7PG11
USB_HSD7NH12
USB_HSD6PE12
USB_HSD6NE14
USB_OC0#/GPM0#E4
DDR3_RST#/GEVENT7#G5
SATA_IS0#/GPIO10AE18
AZ_SDIN3/GPIO46M3
PCI_PME#/GEVENT4#E1
RI#/EXTEVNT0#E2
SLP_S3#F5
SLP_S5#G1
PWR_BTN#H2
PWR_GOODH1
SUS_STAT#K3
TEST1H4
TEST0H3
GA20IN/GEVENT0#Y15
KBRST#/GEVENT1#W15
SMBALERT#/THRMTRIP#/GEVENT2#J6
LPC_PME#/GEVENT3#K4
LPC_SMI#/EXTEVNT1#K24
S3_STATE/GEVENT5#F1
SYS_RESET#/GPM7#J2
WAKE#/GEVENT8#H6
RSMRST#D3
CLK_REQ3#/SATA_IS1#/GPIO6AD18
NB_PWRGDW14
SMARTVOLT1/SATA_IS2#/GPIO4AA19
SMARTVOLT2/SHUTDOWN#/GPIO5Y19
SPKR/GPIO2W21
SCL0/GPOC0#AA18
SDA0/GPOC1#W18
DDC1_SCL/GPIO9AA20
DDC1_SDA/GPIO8Y18
AZ_BITCLKM1
AZ_SDOUTM2
AZ_SYNCL6
AZ_RST#M4
USB_HSD9PA11
USB_HSD9NB11
USB_HSD8PC10
USB_HSD8ND10
LLB#/GPIO66C1
AZ_DOCK_RST#/GPM8#L5
SLP_S2/GPM9#H7
USB_OC5#/IR_TX0/GPM5#B8
BLINK/GPM6#F2
SCL1/GPOC2#K1
SDA1/GPOC3#K2
TEST2H5
CLK_REQ0#/SATA_IS3#/GPIO0W17
AZ_SDIN2/GPIO44L8
AZ_SDIN1/GPIO43J8
AZ_SDIN0/GPIO42J7
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39V17
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40W20
USB_FSD13PE6
USB_FSD13NE7
USB_FSD12PF7
USB_FSD12NE8
USB_HSD11PH11
USB_HSD11NJ10
USB_HSD10PE11
USB_HSD10NF11
IMC_GPIO9B18
IMC_PWM0/IMC_GPIO10F21
SCL2/IMC_GPIO11D21
SDA2/IMC_GPIO12F19
SCL3_LV/IMC_GPIO13E20
SDA3_LV/IMC_GPIO14E21
IMC_PWM1/IMC_GPIO15E19
IMC_PWM2/IMC_GPO16D19
IMC_PWM3/IMC_GPO17E18
IMC_GPIO18G20
IMC_GPIO19G21
IMC_GPIO20D25
IMC_GPIO21D24
IMC_GPIO22C25
IMC_GPIO23C24
IMC_GPIO24B25
IMC_GPIO25C23
IMC_GPIO0H19
IMC_GPIO1H20
SPI_CS2#/IMC_GPIO2H21
IDE_RST#/F_RST#/IMC_GPO3F25
IMC_GPIO4D22
IMC_GPIO5E24
IMC_GPIO6E25
IMC_GPIO7D23
IMC_GPIO8A18
IMC_GPIO26B24
IMC_GPIO27B23
IMC_GPIO28A23
IMC_GPIO29C22
IMC_GPIO30A22
IMC_GPIO31B22
IMC_GPIO32B21
IMC_GPIO33A21
IMC_GPIO34D20
IMC_GPIO35C20
IMC_GPIO36A20
IMC_GPIO37B20
IMC_GPIO38B19
IMC_GPIO39A19
IMC_GPIO40D18
IMC_GPIO41C18
R199 33_0402_5%
1 2
R183 2.2K_0402_5% 1 2
R179
6.81K_0402_5%
12
R193 33_0402_5%
1 2
R18011.8K_0402_1%
1 2
R197 33_0402_5%
1 2
R194 33_0402_5%
1 2
D12
CH751H-40PT_SOD323-2
21
G
D
S
Q104
2N7002_SOT23-3
2
13
R454 10K_0402_5%12
![Page 22: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/22.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
PCI_AD28<19>PCI_AD27<19>PCI_AD26<19>PCI_AD25<19>PCI_AD24<19>PCI_AD23<19>
PCI_CLK2<19>CLK_PCI_KBC<19,33>
CLK_PCI_DB<19,29>PCI_CLK5<19>
CLK_PCI_EC<19>LPCCLK1<19>RTC_CLK<19>HDARST#<21>
GPIO17<21>GPIO16<21>
+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
SB710 STRAPS
Custom
22 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
Internal pull up
RESERVED
DEBUG STRAPS
PCI_AD25 PCI_AD24
USE EEPROMPCIE STRAPS
USE DEFAULTPCIE STRAPS
DEFAULT
BYPASSACPIBCLK
USE ACPIBCLK
DEFAULT
USE IDEPLL
USELONGRESET
USESHORTRESET
USE PCIPLL
DEFAULT
BYPASS IDEPLL
PULLHIGH
DEFAULT
BYPASSPCI PLL
PCI_AD27 PCI_AD26
PULLLOW
DEFAULT
PCI_AD28
SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]
PCI_AD23
LPC_CLK0
ENABLE PCIMEM BOOT
EXT. RTC (PD on X1,apply32KHz toRTC_CLK)DEFAULT
GP17
NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK
DISABLE PCIMEM BOOT
PULLLOW
PULLHIGH
REQUIRED STRAPS
INTERNALRTC
DEFAULT
RTC_CLKLPC_CLK1
CLKGENENABLED
DEFAULT
CLKGENDISABLED
AZ_RST_CD#
ECENABLED
ECDISABLED
DEFAULT
GP16PCI_CLK2
BOOTFAILTIMERENABLED
DEFAULT
BOOTFAILTIMERDISABLED
PCI_CLK3
RESERVED
DEFAULT
IGNOREDEBUGSTRAPS
USEDEBUGSTRAPS
PCI_CLK4 PCI_CLK5
RESERVED
L,H = LPC ROM (Default)
H,H = Reserved
H,L = SPI ROM
L,L = FWH ROM
R2
25
2.2
K_
04
02
_5
%
@
12
R2
03
10
K_
04
02
_5
%
@
12
R2
22
2.2
K_
04
02
_5
%
@
12
R2
04
10
K_
04
02
_5
%
@
12
R2
05
10
K_
04
02
_5
%
@
12
R2
07
10
K_
04
02
_5
%
@
12
R2
14
2.2
K_
04
02
_5
%
12
R2
02
10
K_
04
02
_5
%
@
12
R2
19
2.2
K_
04
02
_5
%
12
R2
08
2.2
K_
04
02
_5
%
12
R2
00
2.2
K_
04
02
_5
%
12
R209
2.2K_0402_5%
@
12
R2
11
2.2
K_
04
02
_5
%
12
R2
10
2.2
K_
04
02
_5
%@
12
R2
21
2.2
K_
04
02
_5
%
@
12
R2
15
2.2
K_
04
02
_5
%
12
R2
01
10
K_
04
02
_5
%
@
12
R2
20
2.2
K_
04
02
_5
%
@
12
R2
17
2.2
K_
04
02
_5
%
12
R2
13
10
K_
04
02
_5
%
@
12
R2
23
2.2
K_
04
02
_5
%
@
12
R2
24
2.2
K_
04
02
_5
%
@
12
R2
06
10
K_
04
02
_5
%
@
12
R2
12
10
K_
04
02
_5
%
@
12
R2
18
2.2
K_
04
02
_5
%
@
12
R2
16
2.2
K_
04
02
_5
%
@
12
![Page 23: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/23.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+AVDDCK_1.2V
+1.2V_CKVDD
+AVDDCK_3.3V
+V5_VREF
+S5_3V
+AVDDCK_3.3V
+AVDDCK_1.2V
+AVDDC
+S5_1.2V
+1.2_USB
+1.2V_SB_CORE+3VS
+1.2V_HT
+1.2V_HT
+3VALW
+3VS
+3VS
+5VS
+1.2V_HT
+1.2V_HT
+PCIE_VDDR
+1.2V_SATA
+3VALW
+AVDD_USB
+1.2VALW
+1.2VALW
+1.2V_HT
+3VALW
+3VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
SB710 PWR/GND
Custom
23 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
L 0.45A/40mil/3vias ?
L 0.8A/50mil/4vias
L <1.25A/50mil/4vias
L <1.25A/50mil/4vias?
L 0.6A/50mil/4vias
L 0.3A/30mil/2vias
L 0.1A/30mil/2vias ?
10/07 HP
10/07 HP
10/07 HP
10/07 HP
10/07 HP
remove C320, C324, C326 for layout 10/22 HP
remove C319, C321, C325 for layout 10/22 HP
HP 2/5
C305 1U_0402_6.3V4Z
1 2
C323 1U_0402_6.3V4Z@ 1 2
C3371U_0402_6.3V4Z
12
C342 22U_0805_6.3V6M
12
C313 1U_0402_6.3V4Z
1 2
C3441U_0402_6.3V4Z
12
L38
FBMA-L11-201209-221LMA30T_0805
1 2
C317 0.1U_0402_16V4Z
1 2
C3081U_0402_6.3V4Z
12
C358 0.1U_0402_16V4Z
1 2
C3541U_0603_10V4Z
1
2
C352 10U_0805_10V4Z
1 2
C3351U_0402_6.3V4Z
12
C3632.2U_0603_6.3V4Z
12
+
C34922U_A_4VM
1 2
C355 10U_0805_10V4Z
1 2
C357 1U_0402_6.3V4Z
1 2
C327 10U_0805_10V4Z@ 1 2
C330 1U_0402_6.3V4Z
1 2
C3652.2U_0603_6.3V4Z
12
C3620.1U_0402_16V4Z 12
L34
FBMA-L11-201209-221LMA30T_0805
1 2
C3381U_0402_6.3V4Z
12
C3612.2U_0603_6.3V4Z
12
C303 22U_0805_6.3V6M
12
C356 1U_0402_6.3V4Z
1 2
C309 1U_0402_6.3V4Z
1 2
C334 0.1U_0402_16V4Z
1 2
+
C30422U_A_4VM
1 2
C328 4.7U_0805_10V4Z
12
C3460.1U_0402_16V4Z
12
C33222U_0805_6.3V6M
1 2
C3121U_0402_6.3V4Z
12
L39
FBMA-L11-201209-221LMA30T_0805
1 2
C359 0.1U_0402_16V4Z
1 2
C3640.1U_0402_16V4Z 12
C3511U_0402_6.3V4Z
12
C678 10U_0805_10V6K
12
R2301K_0402_5%
12
C348 0.1U_0402_16V4Z
1 2
C3390.1U_0402_16V4Z
12
C318 0.1U_0402_16V4Z
1 2
Part 3 of 5
SB710
POWER
PC
I/G
PIO
I/O
CO
RE
S0
3.3
V_
S5
I/O
CO
RE
S5
A-L
INK
I/O
SA
TA
I/O
US
B I
/O PL
LC
LK
GE
N I
/O
IDE
/FL
SH
I/O
U10C
218S7EALA11FG_BGA528_SB700
VDDQ_2M9
VDDQ_6U17
VDDQ_3T15
VDDQ_11AB5
VDDQ_1L9
VDDQ_4U9
VDDQ_5U16
VDDQ_12AB21
VDDQ_10AA4
VDDQ_7V8
VDDQ_8W7
VDDQ_9Y6
S5_3.3V_1A17
S5_3.3V_2A24
S5_3.3V_3B17
S5_3.3V_4J4
S5_3.3V_5J5
S5_1.2V_2G4
S5_1.2V_1G2
USB_PHY_1.2V_1A10
USB_PHY_1.2V_2B10
V5_VREFAE7
AVDDCK_3.3VJ16
AVDDCK_1.2VK17
AVDDCE9
AVDDTX_0A16
AVDDTX_1B16
AVDDTX_2C16
AVDDTX_3D16
AVDDTX_5E17
AVDDTX_4D17
AVDDRX_2F18
AVDDRX_0F15
AVDDRX_5G18
AVDDRX_4G17
PCIE_VDDR_4P21
PCIE_VDDR_3P20
PCIE_VDDR_7R25
PCIE_VDDR_2P19
PCIE_VDDR_5R22
PCIE_VDDR_1P18
PCIE_VDDR_6R24
AVDD_SATA_1AA14
AVDD_SATA_4AB18
AVDD_SATA_2AA15
AVDD_SATA_3AA17
AVDD_SATA_5AC18
AVDD_SATA_6AD17
AVDD_SATA_7AE17
VDD_1L15
VDD_2M12
VDD_3M14
VDD_4N13
VDD_5P12
VDD_6P14
VDD_7R11
VDD_9T16
VDD_8R15
AVDDRX_1F17
AVDDRX_3G15
VDD33_18_2AA21
VDD33_18_4AE25
VDD33_18_3AA22
VDD33_18_1Y20
CKVDD_1.2V_2L22
CKVDD_1.2V_1L21
CKVDD_1.2V_4L25
CKVDD_1.2V_3L24
S5_3.3V_7L2
S5_3.3V_6L1
C3400.1U_0402_16V4Z
12
L37
FBMA-L11-201209-221LMA30T_0805
1 2D13
CH751H-40PT_SOD323-2
21
C3160.1U_0402_16V4Z
12
C333 1U_0402_6.3V4Z
1 2
C360 0.1U_0402_16V4Z
1 2
C3140.1U_0402_16V4Z
12
C322 1U_0402_6.3V4Z@ 1 2
L40
FBMA-L11-201209-221LMA30T_0805
1 2
C347 0.1U_0402_16V4Z
1 2
C343 1U_0805_16V7K
1 2
C315 1U_0402_6.3V4Z
1 2
C3500.1U_0402_16V4Z
12
C3061U_0402_6.3V4Z
12
C3410.1U_0402_16V4Z
12
C311 1U_0402_6.3V4Z
1 2
C331 1U_0402_6.3V4Z
1 2
C345 1U_0805_16V7K
1 2
C3530.1U_0402_16V4Z
1
2
C336 0.1U_0402_16V4Z
1 2
C3101U_0402_6.3V4Z
12
L33
FBMA-L11-201209-221LMA30T_0805
1 2
C307 1U_0402_6.3V4Z
1 2
R5390_0402_5%
12
SB710
GR
OU
ND
Part 5 of 5
218S7EALA11FG_BGA528_SB700
U10E
VSS_4D7
VSS_2A25
VSS_21M13
VSS_10K16
VSS_11L4
VSS_1A2
VSS_17L16
VSS_8K9
VSS_9K11
VSS_46AB1
VSS_13L10
VSS_14L11
VSS_15L12
VSS_16L14
VSS_18M6
VSS_19M10
VSS_20M11
VSS_22M15
VSS_23N4
VSS_26P6
VSS_27P9
VSS_28P10
VSS_29P11
VSS_32R1
VSS_33R2
VSS_34R4
VSS_36R10
VSS_37R12
VSS_3B1
VSS_35R9
VSS_30P13
AVSS_SATA_15AB13
AVSS_SATA_18AC8
AVSS_SATA_5V11
AVSS_SATA_11Y17
AVSS_SATA_19AD8
VSS_31P15
VSS_24N12
AVSS_SATA_14AB11
AVSS_SATA_2U10
AVSS_SATA_3U11
AVSS_SATA_1T10
AVSS_SATA_17AB17
AVSS_SATA_4U12
AVSS_SATA_12AA9
AVSS_SATA_6V14
AVSS_SATA_10Y14
AVSS_SATA_7W9
AVSS_SATA_8Y9
AVSS_SATA_16AB15
AVSS_SATA_20AE8
AVSS_SATA_13AB9
AVSS_USB_5D9
AVSS_USB_8D14
AVSS_USB_4D8
AVSS_USB_3C14
AVSS_USB_6D11
AVSS_USB_7D13
AVSS_USB_2B15
AVSS_USB_21K10
AVSS_USB_10E15
AVSS_USB_20J15
AVSS_USB_22K12
AVSS_USB_11F12
AVSS_USB_12F14
AVSS_USB_23K14
AVSS_USB_16J9
AVSS_USB_15H17
AVSS_USB_19J14
AVSS_USB_14H9
AVSS_USB_1A15
AVSS_USB_24K15
VSS_12L7
AVSS_USB_17J11
AVSS_USB_18J12
VSS_7H8
VSS_25N14
VSS_6G19
AVSS_USB_13G9
AVSS_USB_9D15
AVSSCKL17
PCIE_CK_VSS_3J22
PCIE_CK_VSS_14U20
PCIE_CK_VSS_13U18
PCIE_CK_VSS_12T17
PCIE_CK_VSS_18W19
PCIE_CK_VSS_6M17
PCIE_CK_VSS_11R19
PCIE_CK_VSS_8P16
PCIE_CK_VSS_7M21
PCIE_CK_VSS_17V21
PCIE_CK_VSS_16V20
PCIE_CK_VSS_15V18
VSS_50AE24
PCIE_CK_VSS_21W25
PCIE_CK_VSS_19W22
PCIE_CK_VSS_20W24
AVSSCF9
PCIE_CK_VSS_2J17
PCIE_CK_VSS_1H18
PCIE_CK_VSS_4K25
VSS_5F20
PCIE_CK_VSS_5M16
PCIE_CK_VSS_9P23
PCIE_CK_VSS_10R16
VSS_49AE1
VSS_44V6
VSS_45Y21
VSS_42U4
VSS_48AB25
VSS_47AB19
VSS_41T14
VSS_43U14
VSS_38R14
VSS_39T11
VSS_40T12
AVSS_SATA_9Y11
C329 1U_0402_6.3V4Z
1 2
C3660.1U_0402_16V4Z 12
![Page 24: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/24.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SATA_SRX_C_DTX_P0SATA_SRX_C_DTX_N0
SATA_SRX_C_DTX_P1SATA_SRX_C_DTX_N1SATA_SRX_DTX_N1
SATA_SRX_DTX_P1
SATA_STX_C_DRX_N1SATA_STX_C_DRX_P1
SATA_SRX_DTX_N0
SATA_STX_C_DRX_P0
SATA_SRX_DTX_P0
SATA_STX_C_DRX_N0
SATA_SRX_C_DTX_N0 <20>SATA_SRX_C_DTX_P0 <20>
SATA_STX_C_DRX_P1 <20>SATA_STX_C_DRX_N1 <20>
SATA_SRX_C_DTX_N1 <20>SATA_SRX_C_DTX_P1 <20>
SATA_STX_C_DRX_N0 <20>SATA_STX_C_DRX_P0 <20>
+5VS
+5VS
+5VS
+5VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
HDD/CDROM
Custom
24 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
CD-ROM Connector
Placea caps. near ODD CONN.
HDD Connector
Near CONN side.
Near CONN side.
JHDD1
SUYIN_127043FR022G528_22P_NR-TCONN@
GND1
A+2
A-3
GND4
B-5
B+6
GND7
V338
V339
V3310
GND11
GND12
GND13
V514
V515
V516
GND17
Reserved18
GND19
V1220
V1221
V1222
R2320_0402_5%1 2
C368
0.1U_0402_16V4Z
1
2
C369
0.1U_0402_16V4Z
1
2C372 0.01U_0402_16V7K12
C3
80
1U
_0
60
3_
10
V4
Z
1
2
C3
67
10
U_
08
05
_1
0V
4Z
1
2
C378 0.01U_0402_16V7K12
C3
70
0.1
U_
04
02
_1
6V
4Z
1
2
C3
79
0.1
U_
04
02
_1
6V
4Z
1
2
C38210U_0805_10V4Z
1
2
JODD1
SANTA_202001-1_13P-T
CONN@
GND1
A+2
A-3
GND4
B-5
B+6
GND7
DP8
V59
V510
MD11
GND12
GND13
C3
81
10
U_
08
05
_1
0V
4Z
1
2
C371 0.01U_0402_16V7K12
C377 0.01U_0402_16V7K12
![Page 25: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/25.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCIE_RXN0_LAN
LAN_EE_CLK
LAN_X1
LAN_X1
LAN_X2
LAN_X2
LAN_EE_DATA
PCIE_RXP0_LAN
LAN_EE_DATALAN_EE_CLK
CTRL18
CTRL12
CTRL12CTRL18
LAN_PCIE_WAKE#
LP_EN
LAN_PCIE_WAKE#
LAN_ACT#
PLT_RST#_R
LAN_DIS#
PLT_RST#_R
LP_EN
LP_EN#
PCIE_PTX_C_DRX_P0<10>PCIE_PTX_C_DRX_N0<10>
PCIE_PRX_DTX_N0<10>PCIE_PRX_DTX_P0<10>
CLK_PCIE_LAN<15>CLK_PCIE_LAN#<15>
PLT_RST#<11,19,27,29,31,34>
LAN_MDI0N<26>
LAN_MDI3P<26>LAN_MDI3N<26>
LAN_MDI1P<26>
LAN_MDI2P<26>LAN_MDI2N<26>
LAN_MDI0P<26>
LAN_MDI1N<26>
LAN_ACT# <26,32>
ADP_PRES<20,31,33,36,39,46>
WOL_EN<21>
SLP_S5<30,31,32,36>
ON/OFFBTN#<21,28,32>
LP_EN#<15,21>
LANLINK_STATUS# <21,26,32>
LAN_PCIE_WAKE# <21,27,31>
+3V_LAN
+3V_LAN
+3V_LAN
V1.2_LAN
V1.8_LANV1.2_LAN
V1.2_LAN
+3VALW+3V_LAN
+3V_LAN+3VS
+3V_LAN
V1.2_LAN
+3V_LAN
V1.8_LAN
+3V_LAN
+3V_LAN
V1.2_LAN+1.2VALW
+3V_LANV1.8_LAN
+3V_LAN
+3V_LAN
+5VALW
B+
+3VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
1.0
25 54Thursday, August 27, 2009
2008/09/15 2009/09/15Compal Electronics, Inc.
+1.2VALW to V1.2_LAN
10/08 HP
workaround a out-of-box S4 WOL issue with SB70010/08 HP
remove 8075@, HP 12/5
remove 8075@, HP 12/5
remove 8075@, HP 12/5
remove 8075@, HP 12/5
remove 8075@, HP 12/5
remove 8075@ portion
for DC mode can't boot issue1/15 HP
Giga LAN 88E8072
HP 2/14
HP 2/14
HP 2/14
HP 2/14
HP 2/14
power-down NIC instead of low-power mode HP, 3/23
HP 3/25
HP, 4/13
5/9 HP
for can't power on in AC mode 5/9 HP
5/9 HP
5/9 HP
HP 5/29
R544 0_0402_5%
1 2
R239 10K_0402_5%
1 2
C402
0.1U_0402_16V4Z
1
2Q2B
DMN66D0LDW-7_SOT363-6
3
5
4
R546 0_0402_5%1 2
C396
0.1U_0402_16V4Z
1
2
Q2A
DMN66D0LDW-7_SOT363-6
6 1
2
C397
0.1U_0402_16V4Z
1
2
R2504.7K_0402_5%
12
C7120.022U_0402_16V7K
1
2
R233 100K_0402_5%1 2
R547 0_0402_5%1 2
C383
0.1U_0402_16V4Z
1
2
C5690.1U_0603_25V7K
@
1
2
R246
4.99K_0402_1%1 2
R236 10K_0402_5%
1 2
C389
0.1U_0402_16V4Z
1
2
Q19A
DMN66D0LDW-7_SOT363-6
61
2
R242 10K_0402_5%
12
C4010.1U_0402_16V4Z 12
R499 750K_0402_5%
1 2
C384
0.1U_0402_16V4Z
1
2
G
DS
Q107
2N7002_SOT23-3
2
13
C571
1U_0402_6.3V4Z
1
2
R545 0_0402_5%1 2
R548 0_0402_5%1 2
R249
100K_0402_5%
12
Q19B
DMN66D0LDW-7_SOT363-6
3
5
4
C388
0.1U_0402_16V4Z
1
2
R554
15K_0402_5%
12
C385
0.1U_0402_16V4Z
1
2
C398
0.1U_0402_16V4Z
1
2
Q32
2SB1188T100R_SC62-3
@ 1
23
C5704.7U_0805_10V4Z
1
2
C4064.7U_0805_10V4Z
12
C40927P_0402_50V8J
12
G
D
S
Q31
SSM3K7002FU_SC70-3
2
13
Q1A
DMN66D0LDW-7_SOT363-6
61
2
R234
10K_0402_5%
12
C3870.1U_0402_16V4Z
1
2
R2514.7K_0402_5%
12
C4104.7U_0805_10V4Z
12
C4050.1U_0402_16V4Z
1
2
Q34A
DMN66D0LDW-7_SOT363-6
61
2
C568
4.7U_0805_10V4Z
@ 1
2
Q332SB1188T100R_SC62-3
1
23
C3990.1U_0402_16V4Z
1
2
C40810U_0805_10V4Z
12
C404
0.1U_0402_16V4Z
1
2
C411
0.1U_0402_16V4Z
12
R245 4.7K_0402_5%
12
R237 4.7K_0402_5%@
12
PCI-E
LED
CLOCK
FLASHMEMORY
EEPROM
TEST
Media
Analog
POWER
&
GROUND
No Connect
U12
88E8072 & 88E8075_QFN64
TX_P49
TX_N50
RX_P54
RX_N53
WAKEn6
REFCLKP55
REFCLKN56
PERSTn5
MDIP017
MDIN018
MDIP120
MDIN121
MDIP226
MDIN227
MDIP330
MDIN331
VPD_CLK38
VPD_DATA41
SPI_DO34
SPI_DI35
SPI_CLK37
SPI_CS36
XTALI15
XTALO14
LOM_DISABLEn(USB_DM-)10
VAUX_AVLBL12
SWITCH_VCC(LOM_DISABLEn)11
VMAIN_AVLBL47
SWITCH_VAUX(USB_DP+)9
RSET16
CTRL184
CTRL123
LED_ACTn59
LED_LINK10/100n60
LED_LINK1000n62
LED_DUPLEXn63
TESTMODE46
AVDDH8
AVDD19
NC22
NC23
AVDD28
VDDO_TTL1
VDDO_TTL40
VDDO_TTL45
VDDO_TTL61
VDD2
VDD7
VDD13
VDD33
VDD39
VDD44
VDD48
VDD58
CLKREQn42
EAPD65
(PD18LDO)NC32
NC51
NC52
SMALERTn57
SMCLK64
Reserved24
Reserved25
Reserved29
SMDATA43
U13
CAT24C08WI-GT3 SO 8P
A01
A12
NC3
GND4
VCC8
WP7
SCL6
SDA5
C403
0.1U_0402_16V4Z
1
2
C6850.1U_0603_25V7K
@
1
2
G
DS
Q30SI2301BDS_SOT23
2
13
Q34B
DMN66D0LDW-7_SOT363-6
3
5
4
C41210U_0805_10V4Z
12
R235
47K_0402_5%12
C4000.1U_0402_16V4Z 12
C386
0.1U_0402_16V4Z
1
2
C40727P_0402_50V8J
12
Y425MHZ_20P_1BG25000CK1A
12
Q79
SI4800BDY_SO8
S1
S2
S3
G4
D8
D7
D6
D5
![Page 26: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/26.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TRM_CT
MCT1
TRM_CT
TRM_CT
MCT0
MCT3
MCT2
MDO0-
MDO0+
MDO3-
MDO3+
MDO1-
MDO1+
MDO2-
MDO2+
L AN_MDI0N
LAN_MDI1PL AN_MDI1N
LAN_MDI2PL AN_MDI2N
LAN_MDI3PL AN_MDI3N
LAN_MDI0P
TRM_CT
MDO3+
LANLINK_STATUS#
MDO0+
MDO0-
MDO2+
MDO1-
MDO2-
MDO3-
MDO1+
LAN_ACT#
LAN_MDI0P
L AN_MDI0N
LAN_MDI1P
L AN_MDI1N
LAN_MDI2P
L AN_MDI2N
LAN_MDI3P
L AN_MDI3N
LAN_ACT#
LANLINK_STATUS#
LAN_MDI0P<25>
LAN_MDI0N<25>
LAN_MDI1P<25>LAN_MDI1N<25>
LAN_MDI2P<25>LAN_MDI2N<25>
LAN_MDI3P<25>LAN_MDI3N<25>
MDO0- <32>
MDO0+ <32>
MDO1- <32>
MDO1+ <32>
MDO2- <32>
MDO2+ <32>
MDO3- <32>
MDO3+ <32>
LANLINK_STATUS#<21,25,32>
LAN_ACT#<25,32>
LOM_PWR# <21>
+3V_LAN V_3P3_LAN_LED
V1.8_LAN
+3VALW
V_3P3_LAN_LED
V_3P3_LAN_LED
V_3P3_LAN_LED
V_3P3_LAN_LED
Title
Size Document Number R e v
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
Magnetic & RJ45
26 54Thursday, August 27, 2009
2008/09/15 2009/09/15Compal Electronics, Inc.
20 mil
20 mil
Pin Swap. 10/05
Swap P & N. 10/09
11/04 ESD request
connection the pin10 to GND. 12/31
HP, 4/8
C429680P_0402_50V7K@1 2
JRJ 45
FOX_JM3611A-P1123-7H_14P
PR1-2
PR1+1
PR2+3
PR3+4
PR3-5
PR2-6
PR4+7
PR4-8
Green LED-12
Green LED+11
Yellow LED-14
Yellow LED+13
SHLD115
SHLD116
DETECT PIN19
DETCET PIN210
1:1
1:1
1:1
1:1
T3
NS892402 1G
TCT11
TD1+2
TD1-3
TCT24
TD21+5
TD2-6
TCT37
TD3+8
TD3-9
TCT410
TD4+11
TD4-12
MX4-13
MX3-16
MCT318
MX2-19
MX2+20
MCT221
MX1-22
MX1+23
MCT124
MX4+14
MCT415
MX3+17
C437
0.1U_0402_16V7K
1 2
R4
69
10
K_
04
02
_5
%
12
R258 300_0603_5%1 2
C438 0.01U_0402_50V7K1 2
R26075_0402_1%
1 2
R26275_0402_1%
1 2
D47
PACDN042Y3R_SOT23-3
@
2
31
C431 0.01U_0402_50V7K1 2
R261
0_0402_5%
1 2
R256
0_0805_5%
12
C4330.1U_0402_16V7K
1 2
C436 0.01U_0402_50V7K1 2
R252
10K_0402_5%
12
R25975_0402_1%
1 2
C428680P_0402_50V7K@1 2
C439 1000P_1808_3KV7K1 2
C430
0.1U_0402_16V7K
1 2
R253 300_0603_5%1 2
R25775_0402_1%
1 2
C434 0.01U_0402_50V7K1 2
R2
55
10
K_
04
02
_5
%
12
R254499_0402_1%
1 2
C435
0.1U_0402_16V7K
1 2
C432680P_0402_50V7K@1 2
![Page 27: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/27.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
XMIT_OFF#
WL_LED#_R
LPC_LAD0
LPC_LAD2LPC_LAD1
LPC_LAD3DEG_FRAME#DEBUG_AD3DEBUG_AD2DEBUG_AD1DEBUG_AD0
PCI_RST#_R
PCI_RST#_R
DEG_FRAME#DEBUG_AD3
DEBUG_AD0
DEBUG_AD2DEBUG_AD1
PLT_RST#
UIM_RST
UIM_PWR
UIM_CLKUIM_DATA
UIM_VPP
M_WXMIT_OFF#
UIM_PWR
UIM_VPP
PLT_RST#_WLAN
PLT_RST#_WLAN
WL_LED#_R
UIM_CLKUIM_RSTUIM_PWR
UIM_DATAM_WXMIT_OFF#
MC1_DISABLE
LPC_LAD[0..3] <19,29,33,34>
LPC_LFRAME# <19,29,33,34>
PCI_RST# <19,29>
CLK_PCIE_MCARD#<15>CLK_PCIE_MCARD<15>
CLK_PCI_DEBUG<19>
PCIE_PRX_DTX_N4<10>PCIE_PRX_DTX_P4<10>
PCIE_PTX_C_DRX_N4<10>PCIE_PTX_C_DRX_P4<10>
USB20_N7 <21>USB20_P7 <21>
WW_LED# <31>WLAN_OFF<21>
XMIT_OFF# <21>
PLT_RST#<11,19,25,29,31,34>
WL_LED# <31>
LAN_PCIE_WAKE#<21,25,31>
WXMIT_OFF#<20>
MC1_DISABLE<33>
CLK_PCIE_WLAN_REQ#<15>
SIO_GPIO23 <34>
+1.5VS+3V_WLAN
+3V_WLAN
+3V_WLAN
+3V_WWAN
+3V_WWAN
+3V_WWAN
+3V_WWAN
+3V_WWAN
+1.5VS
+3V_WLAN
+3VS
+5VS
B+
+3VS
+3V_WWAN
+3V_WWAN
+5VS
+3VS
+3VS
+3V_WWAN
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
WLAN&WWAN Mini-Card
27 54Thursday, August 27, 2009
2008/03/13 2009/05/11Compal Electronics, Inc.
Mini Card Slot3--WWAN
Mini Card Slot 1---WLAN Reserve for port80 card use for FCS in factory side.
remove due to AMD platform no support WiMAX 12/02
HP reserve 12/02
power down WWAM circuit. HP 5/29
HP 3/25
HP 3/25
HP 3/25
HP 3/31
HP, 6/11
Q17B
DMN66D0LDW-7_SOT363-6
3
5
4
C4
45 0
.1U
_0
40
2_
16
V4
Z
1
2
T4 PAD
C4
53
39
P_
04
02
_5
0V
8J
@
1
2
R532220K_0402_1%
WWAN@
1 2
C4
51
39
P_
04
02
_5
0V
8J
@
1
2
G
D
S
Q101
2N7002_SOT23-3
WWAN@
2
13
R269
10K_0402_5%
12
C4
52
39
P_
04
02
_5
0V
8J
@
1
2
R263 0_0402_5%1 2
D14
CH751H-40PT_SOD323-2
21
R531
330K_0402_5%
WWAN@
12
Q17A
DMN66D0LDW-7_SOT363-6
61
2
C4
48
0.1
U_
04
02
_1
6V
4Z
WWAN@
1
2
R278 47K_0402_5%
1 2
C4
49
4.7
U_
08
05
_1
0V
4Z
WWAN@
1
2
R268 0_0402_5%1 2
R276
10K_0402_5%
12
C4
42
0.1
U_
04
02
_1
6V
4Z
1
2
C4
64
0.1
U_
04
02
_1
6V
4Z
WWAN@
1
2
R561 0_0402_5%1 2
G
D
S
Q1142N7002_SOT23-3
WWAN@
2
13
Q16B
DMN66D0LDW-7_SOT363-6
3
5
4
JP9
FOXCONN AS0B226-S40N-7F 52P
CONN@
11
33
55
77
99
1111
1313
1515
1717
1919
2121
2323
2525
2727
2929
3131
3333
3535
3737
3939
4141
4343
4545
4747
4949
5151
GND153
22
44
66
88
1010
1212
1414
1616
1818
2020
2222
2424
2626
2828
3030
3232
3434
3636
3838
4040
4242
4444
4646
4848
5050
5252
GND254
R266 0_0402_5%1 2
Q100SI7326DN-T1-GE3_PAK1212-8
WWAN@
35
2
4
1
C6
71
47
P_
04
02
_5
0V
8J
WWAN@
1
2
R277 47K_0402_5%
1 2
R265 0_0402_5%1 2
C4
44
0.0
1U
_0
40
2_
16
V7
K
1
2
R571
470_0805_5%
WWAN@
12
R272
100K_0402_5%
12
R530
0_0402_5%
WWAN@
12
U16
S DIO(BR) NUP4301MR6T1 TSOP-6@
CH11
Vn2
CH23
CH34
Vp5
CH46
R513 0_0402_5% @
1 2
C6
69
47
P_
04
02
_5
0V
8J
1
2
JP12
TAITW_PMPAT6-06GLBS7N14N0CONN@
VCC1
RST2
CLK3
GND4
VPP5
I/O6
GND8
GND9
DET7
R264 0_0402_5%1 2
R273
10K_0402_5%
12
T5 PAD
C6
70
47
P_
04
02
_5
0V
8J
1
2
C4
43
4.7
U_
08
05
_1
0V
4Z
1
2
R570
10K_0402_5%
WWAN@
12
JP10
FOXCONN AS0B226-S40N-7F 52P
CONN@
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
2121
2222
2323
2424
2525
2626
2727
2828
2929
3030
3131
3232
3333
3434
3535
3636
3737
3838
3939
4040
4141
4242
4343
4444
4545
4646
4747
4848
4949
5050
5151
5252
GND153
GND254
C4
46
4.7
U_
08
05
_1
0V
4Z
1
2
R267 0_0402_5%1 2
C4
41
0.0
1U
_0
40
2_
16
V7
K
1
2
C4
63
4.7
U_
08
05
_1
0V
4Z
WWAN@
1
2
Q43
SI2305DS-T1-E3_SOT23-3
2
31
C440 0.022U_0402_25V7K
1 2
R28847K_0402_5%@
12
T6 PAD
C4
47
0.0
1U
_0
40
2_
16
V7
K
WWAN@
1
2
C4
62
18
P_
04
02
_5
0V
8J
WWAN@
1
2
Q16A
DMN66D0LDW-7_SOT363-6
61
2
R529
10K_0402_5%
WWAN@
12
D17DAN217T146_SC59-3@
2
31
![Page 28: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/28.jpg)
HDA_SYNC_MDC
HDA_SDOUT_MDC
HDA_SDIN1_MDC
ON/OFF#
KSI[0..7]
KSO[0..13]
WL/BT_LED#CAP_RST_EC
CAP_CLK
CAP_INTCAP_DAT
STB_LED#
LID_SW#ON/OFF#ON/OFF#
KSI0
KSI1
KSI5
KSI3
KSI4
KSI2
KSI_D_0
KSI_D_8
KSI_D_9
KSI_D_1
KSI_D_2KSI_D_5
KSI_D_10
KSI_D_11
KSI_D_3
KSI_D_13
KSI_D_12
KSI_D_4
KSI6KSI_D_14
KSI_D_6
KSO5KSO2KSO0KSO11
KSI_D_10KSI_D_12KSI_D_8KSI_D_14
KSI_D_2KSI_D_4KSI_D_0
KSI_D_1
KSI_D_12
KSO12
KSI_D_6
KSO4
KSI_D_4
KSI_D_8
KSO9
KSI_D_5
KSO8
KSI_D_14
KSI_D_9
KSO1
KSO3
KSO11
KSO5
KSI_D_11
KSO10
KSI_D_3
KSO0
KSI_D_0
KSO2
KSI_D_13
KSO6
KSI_D_1
KSI_D_10
KSO13
KSI7
KSO7
KSI_D_2
KSI_D_12
KSO12
KSI_D_6
KSO4
KSI_D_4
KSI_D_8
KSO9
KSI_D_5
KSO8
KSI_D_14
KSI_D_9
KSO1
KSO3
KSO11
KSO5
KSI_D_11
KSO10
KSI_D_3
KSO0
KSI_D_0
KSO2
KSI_D_13
KSO6
KSI_D_1
KSI_D_10
KSO13
KSI7
KSO7
KSI_D_2
KSI_D_3KSO3KSO8KSO4
KSO7KSO6KSO10KSO1
KSI_D_5KSI_D_6KSI7
KSI_D_13
KSI_D_11KSI_D_9KSO9KSO12
SP_DATA
KSO13
LID_SW#
HDA_BITCLK_MDC <21>
CAP_CLK<33>CAP_DAT<33>CAP_INT<33>
HDA_SDOUT_MDC<21>
HDA_SYNC_MDC<21>
HDA_SDIN1<21>HDA_RST#_MDC<21>
ON/OFFBTN_KBC# <33>
ON/OFFBTN# <21,25,32>
KSO[0..13]<33>
KSI[0..7]<33>
CAP_RST_EC<33>
STB_LED#<31,32>
WL/BT_LED#<31>
ON/OFF#<21,25,32>
SP_DATA <33>SP_CLK<33>
LID_SW# <17,21,33>
+3VS
+3VL
+3VS
+5VS
+3VS+3VS +VREG3_51125+VREG3_51125+VREG3_51125
+5VS
+VREG3_51125
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
MDC/KBD/ON_OFF/LID
28 54Thursday, August 27, 2009
2008/03/13 2009/05/11Compal Electronics, Inc.
MDC 1.5 Conn.
Power button
Cap SWITCH BOARD. INT_KBD CONN.
TrackPoint CONN.
10/09 EMI
HP request 11/28
correct KB connector Matrix. compal 12/24
delete MODEM_DISABLE# 1/22 HP
for improve battery life
HP 2/11
Compal, 4/1
HP, 7/3
R292 33_0402_5%1 2
D39
DAP202U_SOT323-3
2
31
C4730.1U_0402_10V6K
1
2
CP7
100P_1206_8P4C_50V8K
@
234 5
6781
C4
65
10
00
P_
04
02
_5
0V
7K
1
2
R2
94
10
0K
_0
40
2_
5%
12
R2
89
5.1
K_
04
02
_5
%
12
C46810P_0402_25V8K@
1 2
R574
47K_0402_5%
12
CP2
100P_1206_8P4C_50V8K
@
234 5
6781
JP14
HIROSE FH12HP-30S-1SV 55 30PCONN@
GND262
GND161
11
33
55
77
99
1111
1313
1515
1717
1919
2121
2323
2525
2727
2929
3131
3333
3535
3737
3939
4141
4343
4545
4747
4949
5151
5353
5555
5757
5959
22
44
66
88
1010
1212
1414
1616
1818
2020
2222
2424
2626
2828
3030
3232
3434
3636
3838
4040
4242
4444
4646
4848
5050
5252
5454
5656
5858
6060
GND363
GND464
C651
0.1U_0402_16V4Z
1
2
R537 4.7K_0402_5%
1 2
JP15ACES_88020-12101_12PCONN@
11
33
55
77
99
1111
22
44
66
88
1010
1212
GN
D1
3
GN
D1
4
GN
D1
5
GN
D1
6
GN
D1
7
GN
D1
8
R448 0_0402_5%1 2
JP13
ACES 85203-12021 12P P1.0 CONN@
11
33
55
77
99
1111
1313
1515
1717
1919
2121
2323
22
44
66
88
1010
1212
1414
1616
1818
2020
2222
2424
D38
DAP202U_SOT323-3
2
31
JP33
ACES_87153-08011_8PCONN@
11
33
55
77
99
1111
22
44
66
88
1010
1212
R450 0_0402_5%1 2
C6
73
10
P_
04
02
_5
0V
8J
@
1
2
C703100P_0402_50V8J
@
1 2
CP3
100P_1206_8P4C_50V8K
@
234 5
6781
D36
DAP202U_SOT323-3
2
31
R2
90
5.1
K_
04
02
_5
%
12
R449 0_0402_5%1 2
C4
66
0.1
U_
04
02
_1
6V
4Z
1
2
R2
91
10
K_
04
02
_5
%
12
CP1
100P_1206_8P4C_50V8K
@
234 5
6781
R293 0_0402_5%1 2
C6
75
10
P_
04
02
_5
0V
8J
@
1
2
CP4
100P_1206_8P4C_50V8K
@
234 5
6781
D34
DAP202U_SOT323-3
2
31
D40
DAP202U_SOT323-3
2
31
D37
DAP202U_SOT323-3
2
31
CP6
100P_1206_8P4C_50V8K
@
234 5
6781
C4
67
4.7
U_
08
05
_1
0V
4Z
@
1
2
D35
DAP202U_SOT323-3
2
31
R295 0_0402_5%
1 2
C6
74
10
P_
04
02
_5
0V
8J
@
1
2
CP5
100P_1206_8P4C_50V8K
@
234 5
6781
![Page 29: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/29.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
USB20_N13
U SB20_N1_PWR
USB20_P13 PLT_RST#
TPM_XTALO
TPM_XTALI
TPM_XTALI
TPM_XTALO
TPM_GPIO2TPM_GPIO
LPC_LAD0
LPC_LFRAME#
LPC_LAD2LPC_LAD1
SI RQ
LPC_LAD3
SPI_SO_RSPI_SI
SPI_CS0#
SPI_CLK
SPI_WP#
SPI_WP#
SPI_HOLD#_1
SPI_HOLD#_0 SPI_HOLD#_1
SPI_CLK_JP SPI_CLK
SPI_SI_JP SPI_SI
SPI_CS0#SPI_CS0#_JP
8051_RECOVER#
SPI_SI_JPSPI_SO_JPSPI_HOLD#_0
SPI_CS0#_JPSPI_CLK_JP
8051_RECOVER#
SI RQ
SPI_SO_R SPI_SO_JP
USB20_P13
U SB20_N1_PWRUSB20_N13
SPI_CS0#
PCI_RST#<19,27>
USB20_N13<21>USB20_P13<21>
CLK_PCI_TPM<19>
P M_CLKRUN#<19,33,34>
SPI_CS0#<33>
SPI_CLK<33>
SPI_SI<33> SPI_SO <33> PLT_RST#<11,19,25,27,31,34>SIRQ<19,33,34>
LPC_LFRAME#<19,27,33,34>
CLK_PCI_DB<19,22>
LPC_LAD3<19,27,33,34>LPC_LAD2<19,27,33,34>LPC_LAD1<19,27,33,34>LPC_LAD0<19,27,33,34>
KBC_SPI_CS1#_R<33>
8051TX<33>
8051RX<33>8051_RECOVER#<33>
PCI_SERR#<19,33>
DEBUG_KBCRST<41>
SPI_WP#<33>
+5VALW
+3VALW
+3VS
+3VS
+3VS+3VS
+3VALW
+3VL
+3VL
+3VL
+3VL
51125_PWR
+3VL
+5VALW
Title
Size Document Number R e v
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
TCG/BIOS ROM/PS2/SW LPC DEBUG
29 54Thursday, August 27, 2009
2008/09/15 2009/09/15Compal Electronics, Inc.
Finger printer TPM1.2 on board
0 = 02Eh1 = 04Eh*
Base I/O Address
BIOS ROM
20mils
20mils
20mils
2MB SPI ROM
Add SIRQ and connect to
pin5. LPC Debug Port
HP BIOS request (DB2 12/02)
connect to KBC pin108. HP 2/3
HP 2/11
ESD 2/18
HP 3/25
HP, 4/8
SL B 9635SL B 9635SL B 9635SL B 9635 TT 1.2 TT 1.2 TT 1.2 TT 1.2
U18
SLB 9635 TT 1.2_TSSOP28
NC1
GPIO22
NC3
GN
D4
VS
B5
GPIO6
PP7
TEST18
TESTB1/BADD9
VD
D1
0G
ND
11
NC12
XTALI/32K IN13
XTALO14
CLKRUN#15
LRESET#16
LAD317
GN
D1
8V
DD
19
LAD220
LCLK21
LFRAME#22
LAD123
VD
D2
4G
ND
25
LAD026
SERIRQ27
LPCPD#28
R308 15_0402_5%1 2
R30510M_0402_5%
12
G
D
S
Q502N7002_SOT23-3
2
13
C482 22P_0402_50V8J1 2
R312 0_0402_5%1 2
C4
76
0.1
U_
04
02
_1
6V
4Z
1
2
R560
100K_0402_5%
12
U19
WIESO_G6179-100000_8P
S1
VCC8
Q2
HOLD7
VSS4
D5
C6
W3
R2994.7K_0402_5%
12
R310 0_0402_5%@1 2
Y5
32.768KHZ 1TJS125DJ4A420P
OUT4
IN1
NC3
NC2
R29610K_0402_5%
12
R313 0_0402_5%1 2
&U1
SST25VF016B-50_SO8
@
R314 0_0402_5%1 2
C4
78
0.1
U_
04
02
_1
6V
4Z
1
2
D27
CM1293A-02SR_SOT143-4
GND1
IO12
IO23
VIN4
R298 10K_0402_5%1 2
R3010_0402_5%
1 2
C4
75
0.1
U_
04
02
_1
6V
4Z
1
2
R3024.7K_0402_5%
@1 2
G
DS
Q49 AP2301GN 1P_SOT23
2
13
C4
77
0.1
U_
04
02
_1
6V
4Z
1
2
C48010P_0402_50V8K@
1 2R300 10_0402_5%
@1 2
R3034.7K_0402_5%@
12
C4
79
10
U_
08
05
_1
0V
4Z
1
2
C4830.1U_0402_16V4Z
1
2
R311 0_0402_5%1 2
R309 10K_0402_5%
1 2
R297220K_0402_1%
1 2
R511 0_0402_5%1 2
R306100K_0402_5%
12
JP21
ACES_87216-2404_24PCONN@
Ground1
LPC_PCI_CLK2
Ground3
LPC_FRAME#4
+V3S5
LPC_RESET#6
+V3S7
LPC_AD08
LPC_AD19
LPC_AD210
LPC_AD311
VCC_3VA12
PWR_LED#13
CAPS_LED#14
NUM_LED#15
VCC1_PWRGD16
SPI_CLK17
SPI_CS#18
SPI_SI19
SPI_SO20
SPI_HOLD#21
Reserved22
Reserved23
Reserved24
C481 22P_0402_50V8J1 2
JP20
ACES_85203-04021C ONN@
11
33
55
77
22
44
66
88
T7P AD
R307 3.3K_0402_5%1 2
C4
74
0.1
U_
04
02
_1
6V
4Z
1
2
T8P AD
R3040_0402_5%
12
![Page 30: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/30.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SLP_S5
USB20_N11_RUSB20_P11_R
SLP_S5
SLP_S5
USB20_P3_RU SB20_N3_R
U SB20_N3_R
USB20_P5_RU SB20_N5_R
U SB20_N5_RUSB20_P5_R
U SB20_N0_RUSB20_P0_R
U SB20_N0_RUSB20_P0_R
U SB20_N5_RUSB20_P5_R
USB20_P3_RU SB20_N3_R
USB20_P3_R
U SB20_N0_RUSB20_P0_R
BT_LED <31>USB20_N11 <21>USB20_P11 <21>
BT_OFF<21>
ACCEL_INT#<19>
SLP_S5<25,31,32,36>
SMB_CK_DAT0<4,6,8,9,15,21>SMB_CK_CLK0<4,6,8,9,15,21>
USB20_N3<21>USB20_P3<21>
USB20_N5<21>USB20_P5<21>
USB20_N0<21>USB20_P0<21>
+3VAUX_BT+3VS
+5VALW
USB_VCCA+5VALW
+5VALW
USB_VCCB+5VALW
+3VAUX_BT
+3VS
+3VS
+3VS+3VS
USB_VCCA USB_VCCB
+5VALW
USB _VCCC+5VALW
USB _VCCC
USB_VCCA
Title
Size Document Number R e v
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
USB & BT Connector & Acclerometer
30 54Thursday, August 27, 2009
2008/09/15 2009/09/15Compal Electronics, Inc.
W=100mils
(2A,100mils ,Via NO.=4)
W=100mils
(2A,100mils ,Via NO.=4)
ACCELEROMETER
Change U12 part description fromLIS302DLTR LGA to HP302DLTR8 as HPchange list. 12/03
L Must be placed in the center of the system.
BT Connector
W=100mils
(2A,100mils ,Via NO.=4)
swap JUSB3 & JUSB2 USB signal for USB debug port (USB port 0) HP 2/10
HP 2/12
02/18 ESD
02/18 ESD
C4
89
10
U_
08
05
_1
0V
4Z
1
2
+
C690
15
0U
_D
_6
.3V
M
1
2
C4
92
0.1
U_
04
02
_1
6V
4Z
@
1
2
C490
4.7U_0805_10V4Z
@1
2
L48
WCM2012F2S-900T04_0805
11
22
33
44
J USB3
SUYIN_020167MR004S511ZR_4PC ONN@
11
22
33
44
GND5
GND6
GND7
GND8
U30
TPS2068IDGNG4-R_MSOP8
GND1
IN2
OC#5
OUT6
OUT8
IN3
EN#4
OUT7
R502 0_0402_5%@
1 2
U21
TPS2068IDGNG4-R_MSOP8
@
GND1
IN2
OC#5
OUT6
OUT8
IN3
EN#4
OUT7
R503 0_0402_5%@1 2
R315
10K_0402_5%
12
C4
87
10
00
P_
04
02
_5
0V
7K
1
2
L46
WCM2012F2S-900T04_0805
11
22
33
44
R321 10K_0402_5%12
R482
10K_0402_5%
12
R316 0_0402_5%1 2
C6
92
10
00
P_
04
02
_5
0V
7K
1
2
R505 0_0402_5%@1 2
D28
PJUSB208_SOT23-6@
I/O11
REF12
I/O23
I/O34
REF25
I/O46
J USB2
SUYIN_020167MR004S511ZR_4PC ONN@
11
22
33
44
GND5
GND6
GND7
GND8
C6
91
0.1
U_
04
02
_1
6V
4Z
1
2
C4
88
0.1
U_
04
02
_1
6V
4Z
1
2
R500 0_0402_5%@
1 2
U20
TPS2068IDGNG4-R_MSOP8
GND1
IN2
OC#5
OUT6
OUT8
IN3
EN#4
OUT7
J USB1
SUYIN_020167MR004S511ZR_4PC ONN@
11
22
33
44
GND5
GND6
GND7
GND8
R504 0_0402_5%@
1 2
C4
95
10
U_
08
05
_6
.3V
6M
1
2
D 29
PJUSB208_SOT23-6@
I/O11
REF12
I/O23
I/O34
REF25
I/O46
C484
4.7U_0805_10V4Z
1
2
C4
94
0.1
U_
04
02
_1
6V
4Z
1
2
JP23
ACES_87212-05G0_5PC ONN@
12345
R317 0_0402_5%1 2
LIS302DLU 22
HP302DLTR8_LGA14_3X5
VDD_IO1
GND2
RSVD3
GND4
GND5
VDD6
CS7
INT 18
INT 29
GND10
RSVD11
SDO12
SDA / SDI / SDO13
SCL / SPC14
+
C491
15
0U
_D
_6
.3V
M
@
1
2
L47
WCM2012F2S-900T04_0805
11
22
33
44
R4700_0805_5%
1 2
+
C485
15
0U
_D
_6
.3V
M
1
2
R31910K_0402_5%
12
C689
4.7U_0805_10V4Z
1
2
R320
220K_0402_1%
1 2
C4
93
10
00
P_
04
02
_5
0V
7K
@
1
2
G
DS
Q51
AP2301GN 1P_SOT232
13
R318
10K_0402_5%
@
12
C4
86
0.1
U_
04
02
_1
6V
4Z
1
2
R501 0_0402_5%@1 2
![Page 31: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/31.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BT_LED
BT_LED
WL_LED
WL_LED
WL/BT_LED#
STB_LED#
AQUAWHITE_BATLED#SATA_LED#HDD_HALTLED#
WL/BT_LED#
SLP_S3#
AMBER_BATLED#
PLT_RST#CPPE_NC#
LAN_PCIE_WAKE#
HDA_SDOUT_CODEC
HDA_SYNC_CODECHDA_RST#_CODEC
USB20_N1
TP_CLK
USB20_P1
TP_DATA
PCIE_PTX_C_DRX_P3
CLK_PCIE_EXPCLK_PCIE_EXP#
PCIE_PRX_DTX_P3
PCIE_PTX_C_DRX_N3
PCIE_PRX_DTX_N3
LINE_IN_SENSE LINE_OUT_SENSE
DOCK_LINE_IN_LDOCK_LINE_IN_R
EAPDA_SD#
HDA_SPKR
DLINE_OUT_LDLINE_OUT_R
DCD#1
CTS#1
DSR#1
RI#1
RTS#1RXD1
TXD1
DTR#1
HDA_SDIN0
HDA_BIT_CLK_CODEC
CRD_LOCAL
SLP_S5
PCIE_PRX_DTX_N1PCIE_PRX_DTX_P1
PCIE_PTX_C_DRX_N1PCIE_PTX_C_DRX_P1
CLK_PCIE_CARD#CLK_PCIE_CARD
USB20_N2USB20_P2
SER_SHD
PLT_RST#
CRD_RST#
CRD_LOCAL
CRD_RST#
CRD_LOCAL
BT_LED<30>WL_LED#<27>
WW_LED#<27>
LAN_PCIE_WAKE#<21,25,27>
CPPE_NC#<15,20,21>
AMBER_BATLED#<33>AQUAWHITE_BATLED#<33>
PLT_RST#<11,19,25,27,29,34>
WL/BT_LED#<28>
HDD_HALTLED<20>SATA_LED#<20,32>
HDA_SDOUT_CODEC<21>
HDA_RST#_CODEC<21>HDA_SYNC_CODEC<21>
SLP_S3#<21,33,36,39>PCIE_PRX_DTX_P3 <10>
PCIE_PTX_C_DRX_N3 <10>
PCIE_PTX_C_DRX_P3 <10>
PCIE_PRX_DTX_N3 <10>
USB20_N1 <21>
USB20_P1 <21>
TP_CLK <33>TP_DATA <33>
LINE_IN_SENSE<32> LINE_OUT_SENSE <32>DOCK_LINE_IN_R<32>DOCK_LINE_IN_L<32>
EAPD <33>HDA_SPKR <21>
DLINE_OUT_R <32>DLINE_OUT_L <32>
CLK_PCIE_EXP# <15>CLK_PCIE_EXP <15>
DCD#1<32,34>
RI#1<32,34>DTR#1<32,34>
CTS#1<32,34>
DSR#1<32,34>RXD1<32,34>
TXD1<32,34>RTS#1<32,34>
HDA_SDIN0<21>
HDA_BIT_CLK_CODEC<21>
STB_LED#<28,32>
SLP_S5 <25,30,32,36>
USB20_N2 <21>USB20_P2 <21>
PCIE_PRX_DTX_P1 <10>PCIE_PRX_DTX_N1 <10>
PCIE_PTX_C_DRX_P1 <10>PCIE_PTX_C_DRX_N1 <10>
CLK_PCIE_CARD# <15>CLK_PCIE_CARD <15>
SER_SHD<32>
ADP_PRES <20,25,33,36,39,46>
14vs15_FF_DETECT<33>
CRD_REQ#<15,21>
SIO_GPIO43<34>
+3VS
+3VS
+1.5VS+3VS
+3VALW+VREG3_51125
+5VS
+VREG3_51125 +3VALW +5VS +3VS +1.5VS
+5VS
+5VALW
+3VS+3VS_CD
+3VS_CD
+5VS
+3V_WWAN
+3VS_CD
A_SD# <33>
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
CR&LEDS&PW&Audio&Exp Conn
Custom
31 54Thursday, August 27, 2009
2008/09/01 2010/09/01Compal Electronics, Inc.
Card Reader 7 in 1 + 1 Port USB Connector
Audio/Express Card/TP/LEDs Connector
Serial Port CONN
10/21 move 1394A to card reader USB board
remove UWB LED# 10/31
change board to board contor to wire to board connector. Compal 12/12
correct the net name 1/15 Compal
HP 2/3
power-down of 1394/cardreader chip when no card/1394 insertedHP 3/24
HP 2/17
HP 2/17
change 0.1U to 1U , HP 3/23
HP 4/7
HP 6/8
HP 6/8
HP 6/8HP , 6/13
Q109BDMN66D0LDW-7_SOT363-6
3
5
4
C6
48
1U
_0
40
2_
6.3
V6
K
1
2
G
DS
Q106SI2301BDS_SOT23
2
13
R566
0_0402_5%
@
12
R559
47K_0402_5%
12
C6
84
4.7
U_
08
05
_2
5V
6-K
1
2
C718
0.1U_0402_16V4Z
@1
2
Q18A
DMN66D0LDW-7_SOT363-6
61
2
JP35
E-T_3800K-F12N-03R_12P
CONN@
11
22
33
44
55
66
77
88
99
1010
1111
1212
1414
1313C
64
9
1U
_0
40
2_
6.3
V6
K
1
2
Q18B
DMN66D0LDW-7_SOT363-6
3
5
4
R565
15K_0402_5%
12
R542 15K_0402_5%
1 2
R324 100K_0402_5%
1 2
R322
47K_0402_5%
12
C6
50
1U
_0
40
2_
6.3
V6
K
1
2
R567
680K_0402_5%
1 2
R323 100K_0402_5%
1 2
JP29
P-TWO_196087-18021-3_18P-TCONN@
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
10K
47K
Q53DTA114YKAT146_SOT23-3
2
13
10K
47K
Q52DTA114YKAT146_SOT23-3
2
13
Q8BDMN66D0LDW-7_SOT363-6
3
5
4
C6
46
1U
_0
40
2_
6.3
V6
K
1
2
C717
1U_0402_6.3V4Z
1
2
C6800.1U_0402_16V4Z
1 2
C711
0.022U_0402_16V7K
1
2
C6
47
1U
_0
40
2_
6.3
V6
K
1
2
G
D
S
Q232N7002_SOT23-3
2
13
Q109ADMN66D0LDW-7_SOT363-6
61
2
R55847K_0402_5%
12
Q8ADMN66D0LDW-7_SOT363-6
61
2
R541 10K_0402_5% 1 2
JP34
E-T_1001K-F50E-08E_50P-T
CONN@
11
22
33
44
55
66
77
88
99
1010
1111
1212
3737
3838
1414
1616
1818
2020
1313
1515
1717
1919
2222
2424
2626
2828
3030
3232
3434
3636
2121
2323
2525
2727
2929
3131
3333
3535
3939
4141
4343
4545
4747
4949
4040
4242
4444
4646
4848
5050
5151
5252
![Page 32: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/32.jpg)
DOCK _ID
DPB_TXP2
DPB_TXP1
DPB_TXN0
DOCK _GRNDO CK_BLU
DLINE _IN_RDLI NE_IN_L
DLINE_OUT_LDL INE_OUT_R
DETECT
DPB_TXP0
DETECT
PS2_DATA
KBD_DATAKBD_CLK
VA_ON#
DDC_C LKD DC-DATA
D CD#1
RXD1
DS R#1
RI#1
RTS#1
TXD1
CTS#1D TR#1
PS2_CLK
LPTSTB#
LPTBUSY
L PD3
L PD1
LPTERR#
LPTPELPTSLCT
L PD0
L PD6
LPTSLCTIN#
L PD4
LPTINIT#
L PD7
LPTACK#
L PD5
L PD2
LPTAFD#
PREP#
VA_ON#O N/OFFBTN#
ADP_SIGNAL
DOCK _RED
DPC_TXN3
DPC_TXN0DPC_TXP0
DPC_TXP1
DPC_TXP3
DPC_TXP2
DOCK_AUX+
DOCK _RED
DOCK _ID
DOCK _ID
DOCK _ID
DOCK _GRN
DO CK_BLU
DOCK_AUX-
MDO1-
MDO0+
MDO1+
MDO0-
MDO3+
MDO2-
MDO3-
MDO2+
SATA_SRX_DTX_P2SATA_SRX_DTX_N2
SATA_SRX_DTX_N3SATA_SRX_DTX_P3
SE R_SHD
DOCK_AUX+DOCK_AUX-
HDMICLK_UMAHDMIDAT_UMA
STB_LED#_R
STB_LED#_R
DPC_TXN1
DPC_TXN2
DPB_TXN1
DPB_TXN2
DPB_TXP3DPB_TXN3
LINE_OUT_SENSE
PREP# DOCK _ID
PREP#<21>
DPB_TXN2<10>
DPB_TXP1<10>
DPB_TXP3<10>
DPB_TXP2<10>
DPB_TXN0<10>
DPB_TXN3<10>
DPB_TXN1<10>
D CD#1 <31,34>RI#1 <31,34>DTR#1 <31,34>
CTS#1 <31,34>RTS#1 <31,34>DS R#1 <31,34>
TXD1 <31,34>RXD1 <31,34>
DOCK_LINE_IN_L <31>DOCK _LINE_IN_R <31>
DLINE_OUT_L <31>DLINE_OUT_R <31>
LINE_IN_SENSE <31>
SATA_LED#<20,31>
LINE_OUT_SENSE <31>
USB20_P6 <21>USB20_N6 <21>
DPB_TXP0<10>
LPTACK#<34>LPTBUSY<34>
LPTPE<34>LPTSLCT<34>
LPD7<34>LPD6<34>LPD5<34>LPD4<34>LPD3<34>LPD2<34>LPD1<34>LPD0<34>
LPTSLCTIN#<34>LPTINIT#<34>
KBD_DATA <33>KBD_CLK <33>PS2_DATA <33>PS2_CLK <33>
LPTSTB#<34>LPTAFD#<34>LPTERR#<34>
D_DDCDATA <11,16>D_DDCCLK <11,16>D_VSY NC <16>D_ HSYNC <16>
USB20_P8<21>USB20_N8<21>
DPC_HPD <11>ON/OFFBTN# <21,25,28>
DP B_HPD<18>
DPC_TXN2 <10>
DPC_TXP1 <10>
DPC_TXP3 <10>
DPC_TXP2 <10>
DPC_TXN0 <10>
DPC_TXN3 <10>
DPC_TXN1 <10>
DPC_TXP0 <10>
SLP_S5 <25,30,31,36>
VGA_RED<16>
RED_R <16>
VGA_BLU<16>
BLUE_R <16>
V GA_GRN<16>
GRE EN_R <16>
MDO1- <26>
MDO0+ <26>
MDO1+ <26>
MDO0- <26>
LAN_ACT# <25,26>LANLINK_STATUS# <21,25,26>
MDO3+<26>
MDO2-<26>
MDO3-<26>
MDO2+<26>
SATA_STX_DRX_P2<20>SATA_STX_DRX_N2<20>
SATA_SRX_DTX_P2<20>SATA_SRX_DTX_N2<20>
SATA_STX_DRX_N3<20>SATA_STX_DRX_P3<20>
SATA_SRX_DTX_P3<20>SATA_SRX_DTX_N3<20>
DOCK _ID<18,20>
DOCK_AUX+ <11>DOCK_AUX- <11>
SE R_SHD<31>
HDMIDAT_UMA<11,18>HDMICLK_UMA<11,18>
STB_LED# <28,31>
VA
+5VS
VA
+5VS
VIN VA
GND
GND
GND
ADP_SIGNAL
+5VALW
+5VS
+5VS
+5VS
+5VS
+5VS
+5VALW
+5VALW
Title
Size Document Number R e v
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA -4961P 1.0
DOCK CONNCus tom
32 54Thursday, August 27, 2009
2008/09/15 2009/09/15Compal Electronics, Inc.
DOCKING CONNECTDOCK CONN. 184PIN
(1) PCI Express x1 channels(2) PS/ 2 Interfaces(2) USB 2.channels (2) SATA Channels (2) Display Port Channels (1) Se rial Port(1) Pa rallel Port(1) Line In(1) Line Out(1) RJ45 (10/100/1000)(1 ) VGA(1) 2 LAN indicator LED's(1) Power Button(1) I2C interface
10/17 HP
this circuit will be on dock staton, HP 12/02
HP 10/31
change +5VS to +5VALW for RJ45 LED issue Compal 2/9
HP 12/03
HP 12/03
1/15 HP
1/15 HP
1/15 HP
1/15 HP1/15 HP
1/15 HP
HP 2/3
HP 2/3
HP 2/4HP 2/4
HP 2/4
HP 2/18HP 2/18 HP 2/18
HP 2/18
C522
0.1U_0402_16V4Z
12
U24
TS5A3157_SC70-6
NO1
GND2
NC3
COM4
VCC5
IN6
R538
10K_0402_5%
12
R3391K_0402_5%
12
U 25
TS5A3157_SC70-6
NO1
GND2
NC3
COM4
VCC5
IN6
L41HCB2012KF-121T50_0805
1 2
Q3B
DMN66D0LDW-7_SOT363-6
3
5
4
JDOCKA
FOX_QL0094L-D26601-8H
P1190
G1189
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
2121
2222
2323
2424
2525
2626
2727
2828
2929
3030
3131
3232
3333
3434
3535
3636
3737
3838
3939
4040
4141
4242
4343
4444
4545
144144
145145
146146
147147
148148
149149
150150
151151
152152
153153
154154
155155
156156
157157
158158
159159
160160
161161
162162
163163
164164
165165
166166
167167
168168
169169
170170
171171
172172
173173
174174
175175
176176
177177
178178
179179
180180
181181
182182
183183
184184
185185
186186
187187
188188
JDOCKB
FOX_QL0094L-D26601-8H
4848
4949
5050
5151
5252
5353
5454
5555
5656
5757
5858
5959
6060
6161
6262
6363
6464
6565
6666
6767
6868
6969
7070
7171
7272
7373
7474
7575
7676
7777
7878
7979
8080
8181
8282
8383
8484
8585
8686
8787
8888
8989
9090
9191
9292
9393
9494
9595
9696
9797
9898
9999
100100
101101
102102
103103
104104
105105
106106
107107
108108
109109
110110
111111
112112
113113
114114
115115
116116
117117
118118
119119
120120
121121
122122
123123
124124
125125
126126
127127
128128
129129
130130
131131
132132
133133
134134
135135
136136
137137
138138
139139
140140
141141
4747
4646
143143
142142
G1191
G3193
G5195
G7197
G2192
G4194
G6196
G8198
G9199
G10200
U26
TS5A3157_SC70-6
NO1
GND2
NC3
COM4
VCC5
IN6
C520
0.1U_0402_16V4Z
12
C5050.1U_0402_16V4Z
1
2
Q3A
DMN66D0LDW-7_SOT363-661
2
C5
11
0.1
U_
04
02
_1
6V
4Z
1
2
C5
06
0.1
U_
06
03
_5
0V
4Z
1
2 G
D
S
Q82
2N7002_SOT23-3
2
13
C5
09
0.1
U_
04
02
_1
6V
4Z
1
2
R44010K_0402_5%
1 2
C5
10
0.1
U_
04
02
_1
6V
4Z
1
2
R498
4.7K_0402_5%
12
C5
08
10
U_
08
05
_1
0V
4Z
1
2
C521
0.1U_0402_16V4Z
12
R34010K_0402_5%1 2C
50
70
.1U
_0
60
3_
50
V4
Z
1
2
![Page 33: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/33.jpg)
KSI6
KSI4KSI5
KSI7
AB1B_DATA
AB1A_CLK
AB1B_CLKAB1A_DATA
TP_CLK
TP_DATA
PS2_CLK
SP_CLK
PS2_DATA
SYS_ PWRGD
32K_CLK
AB1B_DATAAB1B_CLK
AB1A_CLKAB1A_DATA
KBRST#
KB C_PWR_ONAQUAWHITE_BATLED#
AB2A_CLKAB2A_DATA
THM_TRAVEL#
KSO6
KSO8KSO7
KSO3
KSO1KSO0
KSO5
KSO9KSO10
KSO4
KSO11
KSO2
KSI4
KSI7
KSI3
KSI0
KSI5
KSI1KSI2
KSI6
TP_CLKTP_DATA
RUNSCI _EC#CLK_PCI_KBC
CRY 1CRY 2
KB C_PWR_ON
PM_RSMRST#
KB_RST#
KSO12KSO13
TEST
PS2_DATAPS2_CLK
PM_RSMRST#
S B_PWRGD
S B_PWRGD8051TX
8051RX
8051TX8051RX
VCC1_ PWRGD
FET_A
FET_B
LATCH
KBD_CLK
KBD_DATA
SP_DATA
SP_CLKSP_DATA
KSI0
KSI3KSI2KSI1
ADP_DET#
14vs15_FF_DETECT
14vs15_FF_DETECT
SLP_S3#
ADP _ID_ADC
A _SD
A _SD
LPC_LAD3<19,27,29,34>LPC_LAD2<19,27,29,34>LPC_LAD1<19,27,29,34>LPC_LAD0<19,27,29,34>
LPC_LFRAME#<19,27,29,34>NPCI_RST#<20,34>
K SI[0..7]<28>
SIRQ<19,29,34>
P M_CLKRUN#<19,29,34>
CLK_PCI_KBC<19,22>
RUNSCI_EC#<21>
TP_CLK<31>TP_DATA<31>
KSO[0..13]<28>
KBC_SPI_SO<20>
SPI_SI<29>KBC_SPI_SI<20>
SPI_CS0#<29>KBC_SPI_CS0#<20>
SPI_SO<29>
SPI_CLK<29>
EAPD <31>
KB_RST# <21>
KBC_PWR_ON <41>AQUAWHITE_BATLED# <31>
BAT_PWM_OUT <39>CHGCTRL <39>
PM_RSMRST# <21,42>
CAP_DAT <28>CAP_CLK <28>CELLS <39>
THM_MAIN# <38>GATEA20 <21>
ADP_PRES <20,25,31,36,39,46>
CAP_INT <28>
CLK_14M_KBC <15>
SYS_PWRGD <44,45>
AMBER_BATLED# <31>
CAP_RST_EC <28>
FAN_PWM <4>
KBC_SPI_CLK<20>
AB1A_CLK <38>AB1A_DATA <38>
AB1B_DATA <38>AB1B_CLK <38>
THM_TRAVEL# <38>
PCI_SERR# <19,29>
8051RX <29>8051TX <29>
KBC_SPI_CS1#_R<29>
SLP_S3# <21,31,36,39>
FET_B <40>
FET_A <40>
PMC<39>
PS2_CLK<32>PS2_DATA<32>
ON/OFFBTN_KBC# <28>
LATCH <40>
OCP <46>
OCP_IN_ADC<46>
A DP_EN <39>SB _PWRGD <6,21,45>
BAT_ALARM<40>
LID_SW# <17,21,28>
ADP_ID_ADC <46>AC_ADP_PRES <39>
SP_CLK<28>SP_DATA<28>
VCC1_PWRGD <39,41>
8051_RECOVER# <29>
KBD_DATA <32>K BD_CLK <32>
ADP_DET# <46>
MC1_DISABLE<27>
SPI_WP# <29>
14vs15_FF_DETECT <31>
A_SD# <31>
SIO_GPIO41 <34>
+5VS
+3VL
+3VL
+3VL
+3VS
+3VL
+RTCVCC
+RTCVCC
+3VL
+3VL
+3VL
Title
Size Document Number R e v
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
KBC1091/1098
33 54Thur s day , August 27, 2009
2008/09/15 2009/09/15Compal Electronics, Inc.
from Power
33pF only for 1070/1091
HP 12/5
add one more 0.1U for SMSC design guideline 12/10
change "BATCON" to ADP_DET# HP 12/12
HP 2/3
HP 4/7
HP, 4/14
add filtering circuit for AD input. HP 5/29
add filtering circuit for AD input. HP 5/29
HP BIOS request (DB2 11/28)
8/25
R368 0_0402_5%1 2
R382 10K_0402_5%
1 2
R367 4.7K_0402_5% 1 2
C5
34
1U
_0
60
3_
10
V4
Z
1
2
R365 10K_0402_5%
1 2
C5
25
0.1
U_
04
02
_1
6V
4Z
1
2
R465 100K_0402_5%1 2
R464 47K_0402_5%
1 2
R370 10K_0402_5%1 2
C716
2200P_0402_50V7K1
2
G
D
S
Q115
2N7002_SOT23-3
@ 2
13
R383 10K_0402_5%
1 2
R375 0_0402_5%
1 2
R378 0_0402_5%1 2
R358 0_0402_5%1 2
R444 10K_0402_5%1 2
R366 0_0402_5%1 2
C529 0.1U_0402_25V61 2
C5
32
33
P_
04
02
_5
0V
8J
1
2
C7152200P_0402_50V7K
1
2
R369 0_0402_5%1 2
R373 10K_0402_5%1 2
R386300_0402_5%
1 2
C531 10P_0402_25V8K@1 2
RP17
10K_0804_8P4R_5%
1 82 73 64 5
Y6
32
.76
8K
HZ
1T
JS
12
5D
J4
A4
20
P
OU
T4
IN1
NC
3
NC
2
C5
23
0.1
U_
04
02
_1
6V
4Z
1
2
R374 0_0402_5%1 2
R381 100K_0402_5%1 2
R575 0_0402_5%
1 2
C7
10
0.1
U_
04
02
_1
6V
4Z
@1
2
R360 10K_0402_5%1 2
C5
33
33
P_
04
02
_5
0V
8J
1
2
R387300_0402_5%
1 2
R445 10K_0402_5%1 2
R371 0_0402_5%1 2R372 10K_0402_5%
1 2
R384 0_0402_5%1 2
C714
2200P_0402_50V7K1 2
R380 100K_0402_5%1 2
R385 0_0402_5%1 2
R362300_0402_5%
1 2
C5
26
0.1
U_
04
02
_1
6V
4Z
1
2
General Purpose I/O InterfaceK
eyboard/Mouse Interface
LPCBus
Power Mgmt/SIRQ
Miscellaneous
Access Bus Interface
SMSC_1098-NU_TQFP-128P
U 27
KBC1098-NU_TQFP128_14X14
AG
ND
72
KSO021
KSO120
KSO219
KSO318
KSO417
KSO516
KSO613
KSO712
KSO810
KSO99
KSO108
KSO117
KSO12/GPIO00/KBRST6
KSO13/GPIO185
KSI029
KSI128
KSI227
KSI326
KSI425
KSI524
KSI623
KSI722
IMCLK35
IMDAT36
KCLK61
KDAT62
EMCLK66
EMDAT67
CLKRUN#55
SER_IRQ57
PCI_CLK54
EC_SCI#76
LAD[3]51
LAD[2]50
LAD[1]48
LAD[0]46
LFRAME#52
LRESET#53
AV
SS
45
XTAL170
XTAL271
VC
C1
14
TEST PIN69
VS
S1
1
VS
S3
7
VS
S4
7
VS
S5
6
VS
S1
04
VS
S8
2
VS
S1
17
VC
C1
39
VC
C1
58
VC
C1
84
VC
C1
10
6
VC
C1
11
9
VC
C2
49
OUT0/(SCI)124
OUT1/IRQ8#125
CFETA/OUT7/nSMI123
OUT8/KBRST122
OUT9/PWM2121
OUT10/PWM0120
PWM_CHRGCTL118
GPIO0279
GPIO0380
GPIO04/KSO1481
GPIO05/KSO1583
GPIO07/PWM385
GPIO08/RXD86
GPIO09/TXD87
GPIO11/AB2A_DATA88
GPIO12/AB2A_CLK89
GPIO13/AB2B_DATA90
GPIO14/AB2B_CLK91
GPIO15/FAN_TACH192
GPIO16/FAN_TACH2101
GPIO17/A20M102
GPIO20/PS2CLK103
GPIO21/PS2DAT105
AB1A_DATA111
AB1A_CLK112
AB1B_DATA109
AB1B_CLK110
GPIO2573
GPIO01107
GPIO26/KSO17108
NC_CLOCKI59
32KHZ_OUT/GPIO22/WK_SE0175
RESET_OUT#/GPIO0660
PWRGD78
VCC1_RST#77
ADC_TO_PWM_OUT/GPIO1938
GPIO24/KSO164
ADP_PRES[CKT#2]/GPIO27/WK_SE0574
CFETB/GPIO10116
BAT_LED#113
PWR_LED#/8051TX115
FDD_LED#/8051RX114
Alarm [CKT#2]/GPIO361
HSTCLK/GPIO412
FLCLK3
GPIO3930
HSTCS1#/GPIO4231
FLCS1#32
GPIO3833
GPIO3734
ADC1/GPIO4643
ADC_TO_PWM_IN44
AVCC40
GPIO3563
GPIO3464
Q/GPIO3365
ADC2/GPIO4042
AC[CKT#2]/GPIO2341
HSTDATAIN/GPIO4394
FLDATAIN95
HSTCS0#/GPIO4496
FLCS0#97
HSTDATAOUT/GPIO45127
FLDATAOUT128
CAP15
GPIO2893
GPIO2998
GPIO3099
GPIO31100
GPIO32126
VCC068
C5
27
4.7
U_
08
05
_1
0V
4Z
1
2
R364 10K_0402_5%1 2
C5
28
0.1
U_
04
02
_1
6V
4Z
1
2
RP16
10K_0804_8P4R_5%
1 82 73 64 5
R564
0_0402_5%
12
C5
24
0.1
U_
04
02
_1
6V
4Z
1
2
R377 0_0402_5%1 2
R376 10_0402_5%@1 2
RP15
10K_0804_8P4R_5%
1 82 73 64 5
C5
35
0.1
U_
04
02
_1
6V
4Z
1
2
RP184.7K_0804_8P4R_5%
1 82 73 64 5
R359 0_0402_5%1 2
R361 10K_0402_5%
1 2
C530 4.7U_0805_6.3V6K
1 2
R562 100K_0402_5%1 2
R443 10K_0402_5% 1 2
R466 100K_0402_5%1 2
![Page 34: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/34.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
D CD#1RI#1CTS#1DS R#1
CLK_PCI_SIO
LPTERR#
L PD2L PD3
L PD1L PD0
L PD7L PD6L PD5L PD4
LPTACK#LPTSLCT
LPTBUSYLPTPE
LPTSLCTIN#
LPTINIT#LPTAFD#
LPTSTB#
SIO_GPIO11
SIO_GPIO42
SIO_GPIO41
SIO_GPIO23
SIO_GPIO46SIO_GPIO45
SIO_GPIO43SIO_GPIO44
SIO_GPIO12SIO_GPIO10
S IO_IRQ
SIO_GPIO41SIO_GPIO42SIO_GPIO43SIO_GPIO44SIO_GPIO45SIO_GPIO46
SIO_GPIO23
SIO_GPIO10
LPC_LAD3
LPC_LAD1LPC_LAD2
LPC_LAD0
CLK_14M_SIO
SIO_PME#
LPC_LFRAME#
L PD0L PD1L PD2L PD3L PD4L PD5L PD6L PD7
SIO_PD#
S IO_IRQ
SIO_GPIO11
CLK_PCI_SIO
SIO_GPIO12
SI RQ
L PC_LDRQ#0
P M_CLKRUN#
LPTBUSY
LPTSLCT
LPTACK#LPTERR#
LPTPE
LPTSTB#LPTAFD#
LPTINIT#LPTSLCTIN#
CTS#1
RI#1
RTS#1
TXD1
D CD#1
RXD1
DS R#1
D TR#1
CLK_14M_SIO<15>
LPC_LAD1<19,27,29,33>
LPC_LFRAME#<19,27,29,33>
LPC_LAD0<19,27,29,33>
LPC_LAD2<19,27,29,33>LPC_LAD3<19,27,29,33>
LP C_LDRQ#0<19>
SIRQ<19,29,33>
P M_CLKRUN#<19,29,33>CLK_PCI_SIO<19>
LPD5 <32>LPD6 <32>
LPD4 <32>LPD3 <32>
LPD7 <32>
LPD0 <32>
LPD2 <32>LPD1 <32>
LPTBUSY <32>LPTPE <32>LPTSLCT <32>
LPTERR# <32>
LPTACK# <32>
LPTINIT# <32>
LPTAFD# <32>LPTSTB# <32>
LPTSLCTIN# <32>
DTR#1 <31,32>
DCD#1 <31,32>
CTS#1 <31,32>
TXD1 <31,32>DS R#1 <31,32>RTS#1 <31,32>
RXD1 <31,32>
RI#1 <31,32>NPCI_RST#<20,33>
SIO_GPIO23<27>
SIO_GPIO43<31>PLT_RST#<11,19,25,27,29,31>
SIO_GPIO41<33>
+3VS
+5VS
+5VS_PRN
+3VS
+3VS
+3VS
+3VS
+3VS
Title
Size Document Number R e v
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
Super I/O LPC47N217Custom
34 54Thur s day , A ugust 27, 2009
2008/09/15 2009/09/15Compal Electronics, Inc.
TO IT8305
Parallel Port
Base I/O Address0 = 02Eh1 = 04Eh*
8/25
RP25
10K_0804_8P4R_5%
18273645
R517 10K_0402_5%
1 2
C706
0.1U_0402_16V4Z
1
2
R39410_0402_5%@
12
R3964.7K_0402_5%1 2
C708
0.1U_0402_16V4Z
1
2
G
D
S
Q116
2N7002_SOT23-3
@
2
13
RP19
4.7K_1206_8P4R_5%
1 82 73 64 5
R522
10K_0402_5%
1 2
R518 10K_0402_5%
1 2
RP24
10K_0804_8P4R_5%
18273645
RP23
2.2K_8P4R_0.05
1 82 73 64 5
RP22
2.2K_8P4R_0.05
1 82 73 64 5
POWER
CLOCK
GPIO
LPC I/F
SERIAL I/F
PARALLEL I/F
U28
LPC47N217N-ABZJ _QFN56
LAD09
LAD111
LAD212
LAD313
LFRAME#14
LDRQ#15
PCI_RESET#16
LPCPD#17
CLKRUN#18
PCI_CLK19
SER_IRQ20
IO_PME#6
INIT#35
SLCTIN#36
PD037
PD139
PD240
PD341
PD442
PD543
PD644
PD745
SLCT47
PE48
BUSY49
ACK#50
ERROR#51
ALF#52
STROBE#53
GPIO4121
GPIO4222
GPIO4324
GPIO4425
GPIO4526
GPIO4627
GPIO4728
GPIO1029
GPIO11/SYSOPT30
GPIO12/IO_SMI#31
GPIO13/IRQIN132
GPIO14/IRQIN233
GPIO2334
CLK148
VTR7
VCC23
VCC46
EPAD57
VCC38
VCC10
RXD154
TXD155
DSR1#56
RTS1#1
CTS1#2
DTR1#3
RI1#4
DCD1#5
RP20
2.2K_8P4R_0.05
1 82 73 64 5
D 32
CH751H-40PT_SOD323-2
21
R519
10K_0402_5%
1 2
RP21
2.2K_8P4R_0.05
1 82 73 64 5
R521
10K_0402_5%
1 2
R389 2.2K_0402_5%
12
C707
0.1U_0402_16V4Z
1
2
R516 1K_0402_5%
1 2
R520
10K_0402_5%
1 2
C709
4.7U_0805_10V4Z
1
2
C53918P_0402_50V8J@
1
2
![Page 35: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/35.jpg)
2VREF_393
SLP_S3
PWR_GD <36,43,44,45>
SLP_S3<36>
VL
+5VS
2VREF_51125
+1.8VS
+3VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
POK CKT
35 54Thursday, August 27, 2009
2008/03/13 2009/05/11Compal Electronics, Inc.
MDC STANDOFF
CPU screw hole
MINI CARD STANDOFF
HP 4/6
HP 4/6
H28HOLEA
1
R398680_0402_5%
12
H17HOLEA
1
ZZZ1
PCB-MB
64@
H16HOLEA
1
FM3
1
H14HOLEA
1
H18HOLEA
1
R400 88.7K_0603_1%
1 2
R407
16.9K_0402_1%
12
H3HOLEA
1
H5HOLEA
1
C542
4700P_0402_16V7K
12
Q15B
DMN66D0LDW-7_SOT363-6
3
5
4
H15HOLEA
1
H26HOLEA
1
H1HOLEA
1
H34HOLEA
1
H19HOLEA
1
H20HOLEA
1
R404 100K_0402_1%
1 2
H2HOLEA
1
FM2
1
C5411000P_0402_50V7K
1
2
FM4
1
FM1
1
H27HOLEA
1
ZZZ1
PCB-MB
14@
ZZZ2
PCB-MB
15.6@
H11HOLEA
1
H4HOLEA
1
H10HOLEA
1
R397
1M_0402_5%1 2
H29HOLEA
1
H7HOLEA
1
H6HOLEA
1
H31HOLEA
1
U29A
LM393DG_SO8
+3
-2
O1
P8
G4
H21HOLEA
1
R402 100K_0402_1%
1 2
H32HOLEA
1
R399 31.6K_0402_1%
1 2
H30HOLEA
1
H33HOLEA
1
J1SHORT PADS
1 2
ZZZ2
PCB-MB
128@
R401 10K_0402_5%
1 2
![Page 36: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/36.jpg)
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
RUNON
VLDT_EN#
VLDT_EN#
PWR_GD
VLDT_EN#
SLP_S3
SLP_S3
SLP_S3
1.8VS_ENABLE
SLP_S3
SLP_S3
RUNON
SLP_S3SLP_S5
SLP_S3
PWR_GD<35,43,44,45>SLP_S3#<21,31,33,39>
SLP_S3<35>
SLP_S5#<21,42>
ADP_PRES<20,25,31,33,39,46>
SLP_S5<25,30,31,32>
B+
+1.2VALW +1.2V_HT
+5VALW +5VS
+5VS
+3VS
+1.8VS
VL
+1.8VS+1.8V
+1.2V_HT
B+
+3VALW +3VS
B+
VL+3VALW
+3VS+1.8VS
+1.5VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
DC/DC Circuits
Custom
36 54Thursday, August 27, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
+1.2VALW TO +1.2V_HT
+5VALW TO +5VS
+1.8V TO +1.8VS
Discharge circuit
+3VALW TO +3VS
10/22 HP
for +1.5VS discharge
HP, 4/19
HP 5/29
R427
100K_0402_5%
12
Q12BDMN66D0LDW-7_SOT363-6
3
5
4
C560
4.7U_0805_10V4Z
1
2
C5554.7U_0805_10V4Z
1
2
Q58
SI4800BDY_SO8
S1
S2
S3
G4
D8
D7
D6
D5
Q13B
DMN66D0LDW-7_SOT363-6
3
5
4
R429
470_0805_5%
12
C545
1U_0402_6.3V4Z
1
2
Q62IRF8113PBF_SO8
365
78
2
4
1
Q59
SI4800BDY_SO8
S1
S2
S3
G4
D8
D7
D6
D5
C548
1U_0402_6.3V4Z
1
2
C557
10U_0805_10V4Z
1
2
Q14A
DMN66D0LDW-7_SOT363-6
61
2
C566
0.01U_0402_16V7K
1
2
G
D
S
Q66
2N7002_SOT23-3
2
13
C5500.1U_0603_25V7K
1
2
C5470.1U_0603_25V7K
1
2
R41547K_0402_5%
12
R421
470_0805_5%
12
C553
0.0
47
U_
04
02
_1
6V
4Z
1
2
C556
1U_0402_6.3V4Z
1
2
R428
100K_0402_5%
12
C5540.1U_0603_25V7K
1
2
R422
470_0805_5%
12
C5640.1U_0603_25V7K
1
2
G
D
S Q642N7002_SOT23-3
2
13
C5510.1U_0603_25V7K
1
2
C559
1U_0402_6.3V4Z
1
2
R419
750K_0402_5%
12
G
D
S
Q60
2N7002_SOT23-3
2
13
R416330K_0402_5%
12
R536
470_0805_5%@
12
C567
0.01U_0402_25V7K
1
2
G
D
S
Q85
2N7002_SOT23-3
2
13
Q61IRF8113PBF_SO8
365
78
2
4
1
R494470_0402_5%
12
G
D
S
Q103
2N7002_SOT23-3
@
2
13
R417820K_0402_5%
12
Q15A
DMN66D0LDW-7_SOT363-6
61
2
Q12A
DMN66D0LDW-7_SOT363-6
61
2
R442
100K_0402_5%1
2
D45
1SS355_SOD323-2
12
C5620.1U_0603_25V7K
1
2C565
4.7U_0805_10V4Z
1
2
Q13A
DMN66D0LDW-7_SOT363-6
61
2
Q14B
DMN66D0LDW-7_SOT363-6
3
5
4
C5610.1U_0603_25V7K
1
2
R418330K_0402_5% 1 2
C5580.1U_0603_25V7K
1
2
C563
4.7U_0805_10V4Z
1
2
R423
470_0805_5%
12
C552
4.7U_0805_10V4Z
1
2
C546
4.7U_0805_10V4Z
1
2
C549
4.7U_0805_10V4Z
1
2
![Page 37: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/37.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P
POWER BLOCK DIAGRAMCustom
37 54Thursday, August 27, 2009
2008/09/15 2009/09/15Compal Electronics, Inc.
RPGOOD
+1.2VALWP 8ATPS51117
(1.2V)
Page42
SLP_S5#
+1.8VP 8ATPS51117
(1.8V)
Page42
EN_PSV
EN_PSV
Page45
+1.2VALW
B+
B+
51125_PWR
+0.9VP 2A+1.2VALW
TPS51100
LDO
(+0.9V)
AC
Adapter
in
Battery
Connector
A
Battery
Connector
B
Battery A
6 Cell
Battery B
8 Cell
TPS51125DC/DC (3V/5V)
ISL6265
(+CPU_CORE0/
+CPU_CORE_NB)
+3VALWP 3A
+5VALWP 4.5A
+CPU_CORE_NB( 4A)
VCC VR_ON
PWR_GD+5VALW
BQ24740Charger
2VREF_51125
B+
SWITCH
BATT_A
BATT_B
BATT
VIN
SWITCHADP_EN#
EN0
SWITCH
PWR_GD
+NB_VDDCP 7ATPS51117
(1.0~1.1V)
Page43EN_PSV
B+
+CPU_CORE0( 35A)
PWR_GD
+1.5VSP 2A+1.8VP
G2992
LDO
(+1.5V)Page44
PWR_GD
+1.1VSP 3A+1.2V_HT
RT9024
LDO
(+1.1V)Page44
+3VS
+2.5VSP 0.2A+3VS
G2916
LDO
(+2.5V)Page44
BatterySelectorCircuit
BATSELB_A
SWITCH
BATSELB_A#
LM331
Thermal
Protector
Page38
Page39
Page40
Page38 Page38
Page43
Page40
EN0
Page44
![Page 38: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/38.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
A DPIN
EN0 <41>
AB1B_DATA <33>
AB1A_CLK <33>
AB1A_DATA <33>
AB1B_CLK <33>
THM_TRAVEL#<33>
THM_MAIN#<33>
OCP_ADJ<46>
VIN
VL2REF_51125
VMB_A
VMB_B
BATT_A
BATT_B
ADP_SIGNAL
+3VL
+3VLVL
VL+3VL
2REF_51125
VL
+3VLTitle
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P
DC-IN/ BATTERY CONNCustom
38 54Thursday, August 27, 2009
2008/09/15 2009/09/15Compal Electronics, Inc.
1.0
Close to CPU
(Need to be checked)
PH1 under CPU botten side :
CPU thermal protection at 90 +-3 degree C
PC111000P_0402_50V7K
12
PD
25
BA
V9
9W
T1
G_
SC
70
-3
2 31
PR4100K_0402_5%
12
PJP2
SUYIN_200046MR008G102ZR
1 1
3 3
4 4
5 5
6 6
8 8
2 2
7 7
G
D
SPQ30
SSM3K7002FU_SC70-3
2
13
PD15BAV99WT1G_SC70-3
2 31
PD1@PJSOT24C_SOT23
2 31
PR9210K_0402_1%
12
PR13
@75K_0402_1%
1 2
PR92294K_0402_1%
1 2
PR
61
00
_0
40
2_
5%
12
PL3SMB3025500YA_2P
1 2
PC
81
00
P_
04
02
_5
0V
8J
12
PC
28
10
0P
_0
40
2_
50
V8
J
12
PR91220K_0402_5%
12
PR
31
K_
04
02
_5
%
12
PR
14
10
0_
04
02
_5
%
12
@LMV331IDCKRG4_SC70-5
PU1
GND2
OUT 4
IN+1
IN-3
VCC+ 5
PR2 1M_0402_1%12
PC
27
10
0P
_0
40
2_
50
V8
J
12
PR12
@150K_0603_1%
1 2
PR7
1K_0402_5%
1 2
PD16BAV99WT1G_SC70-3
2 31
PC21000P_0402_50V7K
12
PD
20
BA
V9
9W
T1
G_
SC
70
-3
2 31
PR90150K_0402_1%
12
PD19PJSOT24CW_SOT323
2 31
PR
15
10
0_
04
02
_5
%
12
PD
26
BA
V9
9W
T1
G_
SC
70
-3
2 31
PC29100P_0402_50V8J
12
PC
71
00
P_
04
02
_5
0V
8J
12
PCN1
SUYIN_20163S-06G1-K
BATT+ 1
TS 5
SMD 2
GND 6
SMC 3
B/I 4
PR89100K_0402_1%
12
PC
11
00
P_
04
02
_5
0V
8J
12
PD
18
PJS
OT
24
CW
_S
OT
32
3
2 31
C
B
E
PQ29MMBT3906_SOT23-3
1
2
3
PH1@100K_0603_1%_TSM1A104F4361RZ
12
[email protected]_0402_1%
12
PR8869.8K_0402_1%
1 2
PL1SMB3025500YA_2P
1 2
PR1
@15K_0402_5%
12
PR
51
00
_0
40
2_
5%
12
PC51000P_0402_50V7K
12
PC
41
00
0P
_0
40
2_
50
V7
K
12
PC3100P_0402_50V8J
12
PR17
@150K_0402_1%
12
PR8
@470K_0402_1%
1 2
PR11
1K_0402_5%
12
PR10
@100K_0402_5%
12
PC100.01U_0402_50V4Z
12
G
D
S
PQ1@SSM3K7002FU_SC70-3
2
13
PJP1
FOX_JPD1131-DB371-7F
ID 3
V+ 1
V+ 2
V-5
V-4
GND_16
GND_27
GND_38
GND_49
PC60.01U_0402_50V4Z
12
PC13@1000P_0402_50V7K
12
PC9100P_0402_50V8J
12
PL2SMB3025500YA_2P
1 2
PC12
@0.022U_0603_25V7K
12
PD17BAV99WT1G_SC70-3
2 31
![Page 39: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/39.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ACDETACDET
DL_CHG
DH_CHG
LX_CHG
CHGEN#
REGN
BA
TT
CHGEN#
BST_CHG
IADAPT
ACDET
IADAPT
VADJ
CHGCTRL
ADP_PRES <20,25,31,33,36,46>
CHGCTRL <33>
BAT_PWM_OUT<33>
SRSET <46>
CELLS <33>
IADAPT<46>
SLP_S3#<21,31,33,36>
VCC1_PWRGD <33,41>
AC_ADP_PRES <33>
PMC <33>
ADP_EN <33>
VIN
BATT
P2
+3VL
VL
CHG_B+
P4P2
P2
P2
+3VL
BQ24740VREF
2VREF_51125
2VREF_51125
+3VL
B+
CHG_B+
P4
+3VL
VL
P2BATT
+3VL
VL
+3VL+3VL
VIN
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
Charger
39 54Thursday, August 27, 2009
2008/09/15 2009/09/15Compal Electronics, Inc.
Note: X7R type
Charge Detector
High 17.614
Low 17.201
AC Detector
High 13.277
Low 10.708
PC1010.1U_0603_25V7K
1 2
PR1280_0402_5%
1 2PR138
100K_0402_5%1 2
PR1301K_0402_5%
1 2
PR119200K_0402_1%
12
PC1161U_0603_6.3V6M
12
PC
11
34
.7U
_0
80
5_
25
V6
M
12
PC
10
8
0.1
U_
06
03
_5
0V
7K
12
PR10515K_0402_5%
12
PC
10
24
.7U
_0
80
5_
25
V6
M
12
PR122210K_0402_1%
12
PC1280.1U_0402_25V6
12
G
D
S PQ104SSM3K7002FU_SC70-3
2
13
PC1200.1U_0603_50V7K
12
PR11010_0805_5%
1 2
PR14539.2K_0402_1%
1 2
PR1120.01_1206_1%
1 2
PC
10
44
.7U
_0
80
5_
25
V6
M
12
PR139
1M_0402_5%1 2
PR
12
7
@7
6.8
K_
04
02
_1
%
12
PR1210_0402_5%
1 2
PQ105ADMN66D0LDW-7 2N SOT363-6
61
2
PC1250.1U_0402_25V6
12
PC1271U_0603_10V6K
12
PR132300K_0402_5%
12
PR111
150K_0402_5%
12
[email protected]_0603_25V7K
12
PR101200K_0402_5%
1 2
PC1170.1U_0402_10V7K
1 2
PQ101AO4433L_SO8
3 65
78
2
4
1
PR104
56K_0402_1%
1 2
PR
14
1
76
.8K
_0
40
2_
1%
12
PQ107AO4468L_SO8
365 7 8
2
4
1
PL101HCB2012KF-121T50_0805
1 2
PD1031SS355_SOD323-2
12
PC109
1U_0805_25V6K
1 2
G
D
S PQ109BSS138_SOT23-3
2
13
PR120
4.7K_0402_5%
12
PU103BLM393DG_SO8
+5
-6O 7
P8
G4
PR1020.01_2512_1%
1
3
4
2
PC1221U_0603_6.3V6M
12
PU10ALM393DG_SO8
+3
-2O 1
P8
G4
PR14311K_0402_5%
1 2
PC1051U_0603_6.3V6M
1 2
PQ106AON7408L_DFN8-5
35
2
4
1
PC
12
6@
4.7
U_
08
05
_2
5V
6M
12
PR131
10K_0603_0.1%
12
PR125604K_0402_1%
1 2
PR126470K_0402_5%1
2
PR12947K_0402_5%
1 2
PU103ALM393DG_SO8
+3
-2O 1
P8
G4
PD102LL4148 LL-34
12
PC
11
54
.7U
_0
80
5_
25
V6
M
12
PR133100K_0402_5%
12
PC1230.047U_0402_16V7K
12
PR135100K_0402_1%
1 2
[email protected]_0603_25V7K
12
BQ24740RHDR_QFN28_5X5PU101
AC
P3
LP
MD
4
CH
GE
N1
AC
N2
AC
DE
T5
AC
SE
T6
IADSLP8
SR
P19
BA
T17
IAD
AP
T15
PGND 22
SR
SE
T16
ISYNSET14
VADJ12
VDAC11
LP
RE
F7
VREF10
DP
MD
ET
21
LODRV 23
CE
LLS
20
SR
N18
AGND9
REGN 24
EXTPWR13
PH 25
HIDRV 26
BTST 27
PVCC 28
TP 29
PR144
49.9K_0402_1%
12
PR1151M_0402_1%
12
PR118
255K_0402_1%
1 2
PQ103P1403EVG_SO8
3 65
78
2
4
1
PC1240.1U_0402_10V7K
12
PR117
100K_0402_5%
12
PC1100.1U_0402_10V7K
1 2
PC
11
44
.7U
_0
80
5_
25
V6
M
12
PR113
453K_0402_1%
12
PC119100P_0402_50V8J
12
PR10347K_0402_5%
1 2
LMV321AS5X_G_SOT23-5
PU104
V-2
+IN1
-IN3OUT 4
V+ 5
PQ105BDMN66D0LDW-7 2N SOT363-6
34
5
PC
10
34
.7U
_0
80
5_
25
V6
M
12
PR1060_0402_5%
12
PR11622.6K_0402_5%
12
PC1070.01U_0402_16V7K
12
PQ102AO4433L_SO8
365
78
2
4
1
C
B
E
PQ108MMBT3906_SOT23-3
1
2
3
PR114422K_0402_1%
1 2
PC
11
24
.7U
_0
80
5_
25
V6
M
12
PC1111U_0603_6.3V6M
1 2
PR142
22K_0402_5%
12
PR134220K_0402_5%
12
PR124147K_0402_1%
12
PL10210U_LF919AS-100M-P3_4.5A_20%
1 2
PR136100K_0402_1%
1 2
PR109
0_0402_5%
1 2
PR12341.2K_0402_1%
12
PC1181U_0603_10V6K
12PR137
24K_0603_1%
1 2
PR
14
02
3.7
K_
04
02
_1
%
12
![Page 40: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/40.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFET_B
CFET_A
CFET_B
BATT_IN
BATT_IN
BATT_IN
BA
TT
_B
_P
BATT_IN
BATT_IN
BA
TT
_A
_P
LATCH<33>
BAT_ALARM <33>
FET_B<33>
FET_A<33>
CFET_A<46>
BATT
BATT
BATT_A
BATT_B
BATT_A
BATT_B
+3VL
BATT
2VREF_51125VL
51125_PWRVin
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P
Battery selector
Custom
40 54Thursday, August 27, 2009
2008/09/15 2009/09/15Compal Electronics, Inc.
PR31
4.7K_0402_5%
12
G
D
S PQ7SSM3K7002FU_SC70-3
2
13
PQ13P1403EVG_SO8
365
78
2
4
1
PQ8PMBT2222A_SOT23-3
1
2
3
G
D
S
PQ10SSM3K7002FU_SC70-3
2
13
G
D
S PQ21SSM3K7002FU_SC70-3
2
13
PD51SS355_SOD323-2
1 2
PR3010K_0402_5%
12
PR29
470K_0402_5%
12
PD91SS355_SOD323-2
1 2
PR181M_0402_5%
1 2
PQ14AO4433L_SO8
365
78
2
4
1
PR340_0402_5%
1 2
PD8RLZ27V
21
PR
39
47
0K
_0
40
2_
5%
12
PQ
17
PM
BT
2222
A_
SO
T2
3-3
1
2
3
G
D
S PQ9SSM3K7002FU_SC70-3
2
13
G
D
S PQ22SSM3K7002FU_SC70-3
2
13
PC150.1U_0603_50V4Z
12
PR93
10K_0402_5%
12
PQ12P1403EVG_SO8
3 65
78
2
4
1
PR19
93.1K_0603_1%
12
PQ15AO4433L_SO8
3 65
78
2
4
1
PR3210K_0402_5%
1 2
G
D
S PQ20SSM3K7002FU_SC70-3
2
13
PR4210K_0402_5%
12
PD2CH715FPT_SC70
2
31
PD7SX34H_SMA
21
PC300.1U_0603_50V4Z
12
G
D
S PQ19SSM3K7002FU_SC70-3
2
13
PR35
470K_0402_5%
12
G
DS
PQ3BSS84LT1G_SOT23-32
13
PD221SS355_SOD323-2
12
PR41
4.7K_0402_5%
12
PD6SX34H_SMA
21
PR20
100K_0402_5%
12
PR36470K_0402_5%
12
G
D
S
PQ11SSM3K7002FU_SC70-3
2
13
PR21
20K_0402_1%
12
PR4410K_0402_5%
1 2
PR28
470K_0402_5%
12
PR94
8.06K_0402_1%
12
G
D
S PQ31SSM3K7002FU_SC70-3
2
13
PR33
470K_0402_5%
12
PU10BLM393DG_SO8
+5
-6
O7
P8
G4
![Page 41: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/41.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DEBUG_KBCRST
UG1_3V
LG_5V
BST_5V
LX_5V
LG_3V
LX_3V
UG_3V
EN
TR
IP1
EN
TR
IP2
UG_5V
BST_3V
EN
TR
IP2
EN
TR
IP1
KBC_PWR_ON <33>
RPGOOD <42>
EN0 <38>
DEBUG_KBCRST <29>
VCC1_PWRGD <33,39>
51125_PWR
B+
B++
+5VALWP
+5VLP
+3VALWP
B++
51125_PWR
2VREF_51125
B+
+3VLP
2VREF_51125
VL
+5VALWP
+3VALW
+5VALW
+3VALWP
VL+5VLP
+3VL
B++
+3VALWP +5VALWP
+VREG3_51125+3VLP
+5VLP
P2
+3VL+3VEXTLP
+5VLP
+3VEXTLP
VL
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
3.3VALWP/5VALWPCustom
41 54Thursday, August 27, 2009
2008/09/15 2009/09/15Compal Electronics, Inc.
Enable +5VALWP when DC mode for S5 power consumption
(4.5A,180mils ,Via NO.= 9)
(3A,120mils ,Via NO.= 6)
PC3140.1U_0603_25V7K
12
PR320255K_0402_1%
12
PC
30
54
.7U
_0
80
5_
25
V6
-K
12
PR319
@0_0402_5%
1 2
PQ303AO4712L_SO8
365 7 8
2
4
1
PR329100K_0402_5%
12
PR327
680K_0402_5%
1 2
PQ302AON7408L_DFN8-5
35
2
4
1
PR30320K_0402_1%
1 2
LMV321AS5X_G_SOT23-5
PU302
V-2
+IN1
-IN3OUT 4
V+ 5
G
D
SPQ307
SSM3K7002FU_SC70-3
2
13
PC3080.1U_0402_10V7K
1 2
PD3051SS355_SOD323-2
12
PR318100K_0402_5%
12 PR328
0_0402_5%
1 2PJP305
PAD-OPEN 2x2m
2 1
G
D
S
PQ305SSM3K7002FU_SC70-3
2
13
PR30420K_0402_1%
1 2
PC30710U_0805_6.3V6M
12
PJP302
PAD-OPEN 2x2m
2 1
PD306
1SS355_SOD323-2
12
PR
32
1
11
.5K
_0
40
2_
1%
12
PR3100_0402_5%
1 2
PR313@1M_0402_1%
1 2
PJP301
PAD-OPEN 4x4m
1 2
+
PC310150U_B2_6.3VM
1
2
PR30113.7K_0402_1%
1 2
PC3220.1U_0402_25V6
12
PC
31
80
.1U
_0
60
3_
50
V7
K
12
PL3034.7UH_PCMC063T-4R7MN_5.5A_20%
1 2
PC320
10U_0805_6.3V6M
12
PC
30
13
90
0P
_0
40
2_
50
V7
K
12
PR32320K_0402_1%
12
PR32416.5K_0402_1%
12
+
PC311150U_B2_6.3VM
1
2
PD3041SS355_SOD323-2
12
PR3114.7_1206_5%
12
PR317330K_0402_5%
12
PR3124.7_1206_5%
12
PR30690.9K_0402_1%
1 2
PU301TPS51125RGER_QFN24_4X4
VR
EF
3
TO
NS
EL
4
EN
TR
IP1
1
VF
B1
2
VF
B2
5
EN
TR
IP2
6
VREG38
DRVL1 19
VR
EG
517
GN
D15
VBST1 22
VIN
16
SK
IPS
EL
14
DRVL212
LL211
VO27
DRVH210 DRVH1 21
PGOOD 23
LL1 20
VC
LK
18
VBST29
VO1 24
EN
013
P PAD25
PC3121000P_0603_50V7K
12
APL5317
PU303
GND2
VIN1
EN3FB 4
VOUT 5
PR326470K_0402_5%
12
PC
30
64
.7U
_0
80
5_
25
V6
-K
12
PQ304AON7406L_DFN8-5
4
5
1 2 3
PR
32
52
20
K_
04
02
_5
%
12
PQ301AON7408L_DFN8-5
35
2
4
1
G
D
S
PQ306SSM3K7002FU_SC70-3
2
13
PR316100K_0402_5%
1 2
PR314100K_0402_5%
12
PL3024.7UH_PCMC063T-4R7MN_5.5A_20%
12
PC31522U_0805_6.3V6M
12
PC3191U_0603_10V6K
12
PC3131000P_0603_50V7K
12
PR3080_0402_5%
1 2
PJP304
PAD-OPEN 2x2m
2 1
PR3090_0402_5%
1 2
PC
31
70
.1U
_0
60
3_
50
V7
K
12
PC3021U_0603_6.3V6M
12
PC3090.1U_0402_10V7K
1 2
G
D
SPQ308SSM3K7002FU_SC70-3
2
13
PC
30
34
.7U
_0
80
5_
25
V6
-K
12
PR30230.9K_0402_1%
1 2
PL301HCB2012KF-121T50_0805
1 2
PC
30
43
90
0P
_0
40
2_
50
V7
K
12
PR32264.9K_0402_1%
12
PR30595.3K_0402_1%
1 2
PJP303
PAD-OPEN 4x4m
1 2
PD3031SS355_SOD323-2
12PR330
60.4K_0402_5%
12
PR315620K_0402_5%
12
PR307
0_0402_5%
1 2
PC321
1U_0603_10V6K
12
PR331
100K_0402_5%
1 2
![Page 42: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/42.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+5VALW
LX_1.8V
LG_1.8V
UG_1.8V
+5VALW
BST_1.8V
UG1_1.8V
+5VALW
LX_1.2V
LG_1.2V
UG_1.2V
+5VALW
BST_1.2V
UG1_1.2V
PM_RSMRST# <21,33>
RPGOOD<41>
SLP_S5#<21,36>
+1.2VALW+1.2VALWP
+1.2VALWP
+1.2VALWP
B+
+1.2VALWP
+1.8VP
+1.8VP
B+
+1.8VP
1.8V_B+
+1.8VP +1.8V
+5VALW
1.2V_B+
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
1.2VALWP/1.8VP
42 54Thursday, August 27, 2009
2008/09/15 2009/09/15Compal Electronics, Inc.
(8A,320mils ,Via NO.= 16)
(8A,320mils ,Via NO.= 16)
PQ404FDS6690AS_G_SO8
365 7 8
2
4
1
PR405 0_0402_5%1 2
PC4061U_0603_10V6K
12
PC
43
70
.1U
_0
60
3_
50
V7
K
12
PL401
HCB1608KF-121T30_0603
1 2
PC
41
30
.1U
_0
60
3_
50
V7
K
12PC417
0.1U_0402_10V7K
1 2
PR403255K_0402_1%
1 2
PC
41
64
.7U
_0
80
5_
25
V6
M
12
PR4094.7_1206_5%
12
PR4150_0402_5%
1 2
[email protected]_0805_6.3V6K
12
PR417 11.5K_0402_1%1 2
PR41010K_0603_0.1%
12
PU402
TPS51117RGYR_QFN14_3.5x3.5
VOUT3
V5FILT4
EN
_P
SV
1
TON2
VFB5
PGOOD6 DRVL 9
DRVH 13
LL 12
GN
D7
PG
ND
8
TRIP 11
V5DRV 10
VB
ST
14
TP
15
PJP401
PAD-OPEN 3x3m
1 2
PC
40
44
.7U
_0
80
5_
25
V6
M
12
PC420@10P_0402_50V8J
1 2
PR411
0_0402_5%
12
PR4040_0402_5%
1 2
PR407 12.1K_0402_1%1 2
PR434@1K_0402_5%
12
PQ402FDS6690AS_G_SO8
365 7 8
2
4
1
PR4122.2_0402_5%
1 2
PR406316_0402_1%
1 2
PC4231000P_0603_50V7K
12
PL4022.2UH_PCMC063T-2R2MN_8A_20%
1 2
PQ401AO4466L_SO8S
1S
2S
3G
4
D8
D7
D6
D5
PR413255K_0402_1%
1 2
+
PC409220U_D2_4VY_R25M
1
2
PR418
14.3K_0402_1%
1 2
PR401
0_0402_5%
12
PC410@10P_0402_50V8J
1 2
PR4310_0402_5%
1 2
PL4042.2UH_PCMC063T-2R2MN_8A_20%
1 2
PR42010K_0603_0.1%
12
PC
41
40
.1U
_0
40
2_
25
V6
12
PC401@1000P_0402_50V7K
12
PC4181U_0603_10V6K
12
PC
40
20
.1U
_0
40
2_
25
V6
12
PC4111000P_0603_50V7K
12
PC4194.7U_0805_10V6K
12
PC4074.7U_0805_10V6K
12
PU401
TPS51117RGYR_QFN14_3.5x3.5
VOUT3
V5FILT4
EN
_P
SV
1
TON2
VFB5
PGOOD6 DRVL 9
DRVH 13
LL 12
GN
D7
PG
ND
8
TRIP 11
V5DRV 10
VB
ST
14
TP
15
[email protected]_0805_6.3V6K
12
+
PC422220U_D2_4VY_R25M
1
2
PQ403AO4466L_SO8S
1S
2S
3G
4
D8
D7
D6
D5
PR414 0_0402_5%1 2
PC
41
54
.7U
_0
80
5_
25
V6
M
12
PJP402
PAD-OPEN 4x4m
1 2
PC
40
34
.7U
_0
80
5_
25
V6
M
12PR402
2.2_0402_5%
1 2
PL403
HCB1608KF-121T30_0603
1 2PC412@1000P_0402_50V7K
12
PR416316_0402_1%
1 2
PR408
6.49K_0402_1%
1 2
PR4194.7_1206_5%
12
PC4050.1U_0402_10V7K
1 2
![Page 43: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/43.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LX_VDDC
LG_VDDC
UG_VDDC
+5VALW
BST_VDDC
UG1_VDDC
PWR_GD<35,36,44,45>
DYN_PWR_EN <11>
+NB_VDDCP
B+
+5VALW
+NB_VDDCP
VDDC_B+
+NB_VDDCP +NB_VDDC
+NB_VDDCP
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
NB_VDDC
43 54Thursday, August 27, 2009
2008/09/15 2009/09/15Compal Electronics, Inc.
(7A,280mils ,Via NO.= 14)
DYN_PWR_EN
0
1
NB_VDDC
1.1
1.0
PC4334.7U_0805_6.3V6K
12
PL405
HCB1608KF-121T30_0603
1 2
PR4294.7_1206_5%
12
PR43023.7K_0402_1%
12
PC
42
60
.1U
_0
40
2_
25
V6
12
PR425 0_0402_5%1 2
PC
42
74
.7U
_0
80
5_
25
V6
M
12
PC4351000P_0603_50V7K
12
PC4240.01U_0402_16V7K
12
PU403
TPS51117RGYR_QFN14_3.5x3.5
VOUT3
V5FILT4
EN
_P
SV
1
TON2
VFB5
PGOOD6 DRVL 9
DRVH 13
LL 12
GN
D7
PG
ND
8
TRIP 11
V5DRV 10
VB
ST
14
TP
15
PR427 12.4K_0402_1%1 2
PC432
4700P_0402_16V7K
12
PR4222.2_0402_5%
1 2
PR423255K_0402_1%
1 2
+
PC434220U_D2_4VY_R25M
1
2
PR421150K_0402_5%
1 2
PR42810K_0402_1%
1 2
PC4314.7U_0805_10V6K
12
PR4240_0402_5%
1 2
PR426316_0402_1%
1 2
PC
42
50
.1U
_0
60
3_
50
V7
K
12
PJP403
PAD-OPEN 4x4m
1 2
PR433191K_0402_1%
1 2
PC4290.1U_0402_10V7K
1 2
PR43216.2K_0402_1%
1 2
PQ406AO4712L_SO8
365 7 8
2
4
1
PC
42
84
.7U
_0
80
5_
25
V6
M
12
PC436
1500P_0402_50V7K
12
PC4301U_0603_10V6K
12
PQ405AO4466L_SO8S
1S
2S
3G
4
D8
D7
D6
D5
PL4062.2UH_PCMC063T-2R2MN_8A_20%
1 2
![Page 44: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/44.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.1VSP
PWR_GD
PWR_GD<35,36,43,45>
SYS_PWRGD <33,45>
+V_DDR_MCH_REF <8,9>
+0.9V+0.9VP
+1.5VSP
+5VALW
+5VALW
+1.8VP
+1.5VS+1.5VSP
+1.1VS+1.1VSP
+3VS +2.5VSP
+2.5VS+2.5VSP
+1.2V_HT+5VALW
+1.1VSP
+1.2VALW
+0.9VP
+1.8V
+5VALW
+5VALW
+1.8V
+1.2VALW
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
0.9V/1.5VS/1.1VS/2.5VS
44 54Thursday, August 27, 2009
2008/09/15 2009/09/15Compal Electronics, Inc.
(2A,80mils ,Via NO.= 4)
(3A,120mils ,Via NO.= 6)
(200mA,10mils ,Via NO.= 1)
(2A,80mils ,Via NO.= 4)
PR6120_0402_5%
1 2
PR603
200_0402_1%
12
PC60910U_0805_6.3V6M
12
RT9024GE_SOT23-6
PU603
GND2
EN1
FB3 PGOOD 4
DRI 5
VCC 6
PR6050_0402_5%
1 2
PJP604
PAD-OPEN 2x2m
2 1
PR606
10K_0402_5%
12
PC
61
10
.1U
_0
40
2_
10
V7
K
12
PQ
60
2B
DM
N6
6D
0L
DW
-7 2
N S
OT
36
3-6
34
5
PR61410K_0402_1%
12
PC61710U_0805_6.3V6M
12
PC6221000P_0402_50V7K
1 2
PC
61
31
0U
_0
80
5_
6.3
V6
M
12
PU602
G2992F1U_SO8
VOUT4
NC 5GND2
VREF3
VIN1 VCNTL 6
NC 7
NC 8
TP 9
PU604G916T1UF_SOT23-5
IN1
GND
2
OUT 5
SHDN#3 SET 4PR611
10K_0402_5%
1 2
PJP602
PAD-OPEN 3x3m
1 2
PC
60
31
0U
_0
80
5_
6.3
V6
M
12
PC
60
51
0U
_0
80
5_
6.3
V6
M
12
PC6021U_0603_10V6K
12
PC61210U_0805_6.3V6M
12
PR6100_0402_5%
1 2
PC62110U_0805_6.3V6M
12
PR6081K_0402_1%
12
PC
60
6@
10
U_
08
05
_1
0V
4Z
12
PR6131K_0402_1%
12
PC62010U_0805_6.3V6M
12
PC6191000P_0402_50V7K
12
PJP603
PAD-OPEN 3x3m
1 2
E
B
C
PQ604MMBT3904WH_SOT323-3
2
31
[email protected]_0402_16V7K
12
PQ603SI7230DN-T1-GE3_PAK1212-835
2
4
1
PR6093.92K_0402_1%
12
PC6071U_0603_10V6K
12
[email protected]_0402_16V7K
12
PR607
16K_0402_5%
12
PC6232.2U_0603_6.3V6K
12
PC61610U_0805_6.3V6M
12
PC6081U_0603_6.3V6M
12
PC
61
41
0U
_0
80
5_
6.3
V6
M
12
PC
60
4@
10
U_
08
05
_1
0V
4Z
12
PQ602ADMN66D0LDW-7 2N SOT363-6
61
2
PR618
2.2_0402_5%
1 2
PR6151K_0402_1%
12
PC6151U_0603_10V6K
12
PJP601
PAD-OPEN 3x3m
1 2
PU601
TPS51100DGQR_MSOP10
PGND4
VTTSNS5
VLDOIN2
VTT3
VDDQSNS1
VTTREF 6
S3 7
GND 8
S5 9
VIN 10
TP11
PR617@0_0402_5%
12
PR6161K_0402_5%1 2
![Page 45: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/45.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
UGATE1_1
UGATE0_1VS
EN
_N
B
RT
N0
RT
N1
BO
OT
_N
B1
ISP
0
+C
PU
_C
OR
E_
0
BO
OT
0
UGATE0
LGATE0
BOOT1
LGATE1
UGATE1
PHASE1
ISP 0PHASE0
ISP 1
+CPU_CORE_0
ISP 1
BO
OT
_N
B
RT
N_
NB
PH
AS
E_
NB
SVD
SVC
UG
AT
E_
NB
PH
AS
E_
NB
UG
AT
E_
NB
LG
AT
E_
NB
VS
EN
0
LG
AT
E_
NB
VDD_NB_FB_H<6>
SYS_PWRGD<33,44>
SB_PWRGD<6,21,33>
CPU_SVD<6>
CPU_SVC<6>
PWR_GD<35,36,43,44>
CPU_VDD0_FB_H<6>
CPU_VDD0_FB_L<6>
VDD_NB_FB_L<6>
+CPU_CORE_0
+5VALW
B+
CPU_B+
CPU_B+
+CPU_CORE_NB
CPU_B+
+5VALW
CPU_B+
+3VS+5VS
+CPU_CORE_0
+1.8V
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
CPU_CORE
Custom
45 54Thursday, August 27, 2009
2008/09/15 2009/09/15Compal Electronics, Inc.
PR2194.02k_0603_1%
1 2
PC2051000P_0402_50V7K
1 2
PR
23
04
.7_
12
06
_5
%
12
PC237
1200P_0402_50V7K
1 2
PQ201AON7406L_DFN8-5
4
5
123
PQ202AON7408L_DFN8-5
3 52
4
1
PC2100.1U_0603_25V7K
12
PC
20
91200
P_
04
02
_5
0V
7K
12
PC2060.1U_0402_16V7K
12
PR
23
11
6.5
K_
04
02
_1
%
12
PL2030.36UH_PCMC104T-R36MN1R17_30A_20%
12
PR224
95.3K_0402_1%
1 2
PC2240.22U_0603_10V7K
1 2
PC
21
44
.7U
_0
80
5_
25
V6
-K
12
PC
24
20
.1U
_0
60
3_
50
V7
K
12
PR
20
20
_0
40
2_
5%
12
PR2370_0402_5%
1 2
PC2401000P_0402_50V7K
1 2
PR2072_0402_5%
1 2
PR225
255_0402_1%
1 2
PC2260.1U_0603_25V7K
1 2
PR212@10K_0402_5%
1 2
PC
23
30
.1U
_0
60
3_
50
V7
K
12
PR222 0_0402_5%1 2
PQ207AO4474L_SO8
365 7 8
2
4
1
PC
22
23
90
0P
_0
40
2_
50
V7
K
12
PC2441000P_0402_50V7K
12
PR
21
81
6.5
K_
04
02
_1
%
12
PR2401K_0402_5%
1 2
PC
21
34
.7U
_0
80
5_
25
V6
-K
12
PL204
0.36UH_PCMC104T-R36MN1R17_30A_20%
12
PR2091_0603_5%
12
PC2212.2U_0603_6.3V6K
12
PR20422K_0402_1%
1 2
PR2010_0402_5%
12
PC
21
54
.7U
_0
80
5_
25
V6
-K
12
PC
22
51
00
0P
_0
60
3_
50
V7
K
12
PC
24
7@
100
0P
_0
40
2_
50
V7
K1
2
+
PC202220U_B_2.5VM_R35M
1
2
PR226
0_0603_5%1 2
PC2271000P_0603_50V7K
12
PR211@0_0402_5%
1 2
PC
20
11
0U
_0
80
5_
6.3
V6
M
12
PL2014.7UH_PCMC063T-4R7MN_5.5A_20%
12
PC2044.7U_0805_25V6-K
12
PR
20
84
4.2
K_
04
02
_1
%
12
PC
23
14
.7U
_0
80
5_
25
V6
-K 12
PC
20
83
3P
_0
40
2_
50
V8
J
12
PC2410.1U_0603_25V7K
1 2
PL202HCB2012KF-121T50_0805
12
PC
23
23900
P_
04
02
_5
0V
7K
12
PR221 0_0402_5%1 2
PR2340_0402_5%
1 2
PR2150_0603_5%1 2
PR
21
64
.7_
12
06
_5
%
12
PQ206TPCA8028-H_SOP-ADVANCE8-5
4
1235
PC
21
60
.1U
_0
60
3_
50
V7
K
12
PC
22
31
00
0P
_0
40
2_
50
V7
K
1 2
PC
24
5@
100
0P
_0
40
2_
50
V7
K1
2
PR227
1K_0402_1%
1 2
PC
20
33
90
0P
_0
40
2_
50
V7
K
12
PR
21
31
0K
_0
40
2_
1%
12
PR
20
30
_0
40
2_
5%
12
PR2282.2_0603_5%
1 2
PC
23
04
.7U
_0
80
5_
25
V6
-K 12
PC235
4700P_0402_25V7K
1 2
PC
21
24
.7U
_0
80
5_
25
V6
-K
12
PR232
6.81K_0402_1%
1 2
PC
22
84
.7U
_0
80
5_
25
V6
-K 12
PR2052_0402_5%
1 2
PC2360.22U_0603_10V7K
1 2
+
PC
22
0@
47
U_
25
V_
M
1
2
PR2142.2_0603_5%
1 2
PC2381000P_0603_50V7K
12
PL205HCB2012KF-121T50_0805
12
PQ204AO4474L_SO8
365 7 8
2
4
1
PC
22
94
.7U
_0
80
5_
25
V6
-K 12
PC2070.1U_0402_16V7K
12
PR229
54.9K_0402_1%
1 2
PR223
21.5K_0402_1%
1 2
PR2100_0402_5%
1 2
PQ205TPCA8028-H_SOP-ADVANCE8-5
4
1235
PR2174.7_1206_5%
12
PR2334.02k_0603_1%
1 2
PC239180P_0402_50V8J
1 2
PU201
ISL6265AIRZ-T_QFN48_6X6
PWROK3
SVD4
OFS/VFIXEN1
PGOOD2
SVC5
ENABLE6
OCSET8
VD
IFF
11
9
RT
N1
17
VS
EN
01
5
VW
12
2
RT
N0
16
ISN
01
4
VW012
COMP011
RBIAS7
FB010
CO
MP
12
1
ISP
12
3
FB
12
0
VS
EN
11
8
VDIFF09
ISN
12
4
ISP
01
3
BOOT125
UGATE126
PHASE127
PGND128
LGATE129
PVCC30
LGATE031
PGND032
PHASE033
UGATE034
BOOT035
BOOT_NB36
UG
AT
E_
NB
37
PH
AS
E_
NB
38
LG
AT
E_
NB
39
PG
ND
_N
B4
0
OC
SE
T_
NB
41
RT
N_
NB
42
VS
EN
_N
B4
3
FS
ET
_N
B4
4
CO
MP
_N
B4
5
FB
_N
B4
6
VC
C4
7
VIN
48
TP
49
PR
20
61
5K
_0
40
2_
1%
12
![Page 46: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/46.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
OCP_A_IN
ADP_ID_ADC <33>
ADP_DET# <33>
IADAPT<39>
H_PROCHOT# <4,6>
SRSET <39>
OCP<33>
ADP_PRES3,36,39>
CFET_A<40>
OCP_ADJ <38>
OCP_IN_ADC <33>
ADP_SIGNAL
+5VS
2VREF_51125
VIN
BQ24740VREF
+3VL
VL
+3VL
+3VL+3VL
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P
ADP_OCPCustom
46 54Thursday, August 27, 2009
2008/09/15 2009/09/15Compal Electronics, Inc.
PR7047K_0402_1%
12
PC
31
0.0
1U
_0
40
2_
16
V7
K
12
PR64
100_0402_5%
12
PC26
10U_0805_10V6K
12
PR68200K_0402_5%
1 2
PR794.7K_0402_1%
12
G
DS
PQ24NDS0610_G_SOT23-3
2
13
G
D S
PQ33BSS138_SOT23-3
2
1 3
PR63@0_0402_5%
1 2
PR618.66K_0402_1%
12
PR60100K_0402_5%
1 2
PR71100K_0402_5%
12
PR6745.3K_0402_1%
12
E
B
C
PQ26MMBT3904WH_SOT323-3
2
31
PC210.22U_0603_10V7K
1 2
PR8210K_0402_1%
12
PU14A
LM393DG_SO8
+3
-2O 1
P8
G4
PR65
27.4K_0402_1%
12
LMV321AS5X_G_SOT23-5
PU12
V-2
+IN1
-IN3OUT 4
V+ 5
PR7568K_0402_1%
12
G
D
S PQ34SSM3K7002FU_SC70-3
2
13
PR7410K_0402_5%
12
PR50165K_0402_1%
12
PC
23
39
00
P_
04
02
_5
0V
7K
1
2
C
B
EPQ35MMBT3906_SOT23-3
1
2
3
PR52
2K_0402_5%
12
PC32
0.01U_0402_16V7K
12
PU14B
LM393DG_SO8
+5
-6O 7
P8
G4
PR5110K_0402_1%
1 2
PR62
8.06K_0402_1%
12
PR570_0402_5%
1 2
PD231SS355_SOD323-2
12
PR58100_0402_5%
1 2
PD211SS355_SOD323-2
12
PR69130K_0402_1%
12
PD111SS355_SOD323-2
12
PR49100K_0402_1%
12
PR7233K_0402_1%
12
G
DS
PQ32BSS138_SOT23-3
2
13
PR95150K_0402_5%
1 2
PR8510K_0402_5%
1 2
PD24RLZ4.7B_LL34
12
G
D
SPQ25SSM3K7002FU_SC70-3
2
13P
R5
93
.9K
_0
40
2_
5%
12
PR66100K_0402_5%
12
PR841M_0402_5%
1 2
PR73
100K_0402_5%
12
![Page 47: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/47.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size D ocument Number R e v
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
Changed-List History
47 54Thursday, August 27, 2009
2008/09/15 2009/09/15Compal Electronics, Inc.
8 2009/02/10 DB2-->SI1 Additional +3VL for KBC ADC accuracy 41 Add external +3VL LDO
32 2009/06/26 SI2-->PV
(MEMO)
Change PR330 from 15K to 20KFor HP's request 41
12 2009/02/20 DB2-->SI1 For EMI request 41
45
3V/5V
PR311/PC312:4.7ohm/ 1000pF
PC317/PC301:0.1uF/ 3900pF
PR312/PC313:4.7ohm/ 1000pF
PC318/PC304:0.1uF/ 3900pF
CPU CORE
PR217/PC227:4.7ohm/ 1000pF
PC242/PC203:0.1uF/ 3900pF
PR216/PC225:4.7ohm/ 1000pF
PC216/PC222:0.1uF/ 3900pF
PR230/PC238:4.7ohm/ 1000pF
PC233/PC232:0.1uF/ 3900pF
11 2009/02/19 DB2-->SI1 Adjust NB_VDDC between 0.95V and 1.1V
(instead of 1.0V and 1.1V).
43 Change PR430 to 23.7K_0402_1% and PR433 to 191K_0402_1%
18 2009/04/24 SI1-->SI2 Fine tune NB_VDDC power on sequence 43 Change PR421 from 10K to 150K
Change PC424 from 1000P to 0.01u
19 2009/04/24 SI1-->SI2 Travel battery can not be detected issue 38 Change PR9 from 100K to 210K
20 2009/04/24 SI1-->SI2 For RF request 42
43
Add PC413,PC425 and PC437 as 0.1u
Add PR409,PR419 and PR429 as 4.7 ohm
Add PC411,PC423 and PC435 as 1000pF
3
27 2009/06/06 SI2-->PV For EMI request (had been implemented at SI2) 42
43
Change PR402,PR412 from 0 to 2.2
Add PR409,PR419 as 4.7
PC411,PC423 as 1000p
PC413,PC437 as 0.1u_0603
PC402,PC414 as 0.1u_0402
Change PR422 from 0 to 2.2
Add PR429 as 4.7
PC435 as 1000p
PC425 as 0.1u_0603
PC426 as 0.1u_0402
16 2009/04/14 SI1-->SI2 Enable +5VALWP when DC mode 41 Add PR318 as 100K which is the pull high of PQ305.3 to VL
Connect PQ305.3 to DEBUG_KBCRST
28 2009/06/06 SI2-->PV Fine tune power sequence for NB_VDDC
(had been impelemented at SI2)
43 Change PR421 from 10K to 150K
PC424 from 1000p to 0.01u
29 2009/06/06 SI2-->PV 38 Change PR9 from 100K to 210KEnsure the THM_MAIN# level lower enough
when main battery be inserted (had been impelemented at SI2)
2009/05/30 SI2-->PV
33 2009/06/26
Fine tune OCP setting 46 Change PR49 to 100K25
SI2-->PV
(MEMO)
For HP's request 44 Change PR616 from 10K to 1K
Version change list (P.I.R. List) Power section Page 1 of 1
Item Reason for change PG# Modify ListDate Phase
15 2009/04/09 SI1-->SI2 To improve the power efficiency when S5 under DC mode,
Re-connect the EN signal (ENTRIP1/2) to 2 singal N-MOSFET
41 Change PQ305 from 2N7002KDW-2N_SOT363 to SSM3K7002FU_SC70
Add PQ306 as SSM3K7002FU_SC70-3
31 2009/06/09 SI2-->PV Add PQ20, PQ25 and PQ26 as BAV99For ESD request 38
2009/01/16 DB2-->SI1 Improve DDR termination power rail efficiency 44 Change DDR termination solution from G2992 to TPS51100
2009/01/22 DB2-->SI1 Modify the charger funtion 39 Modify the watch-dog circuit
6
2009/05/25 SI2-->PV
9 2009/02/18 DB2-->SI1 44 Add +V_DDR_MCH_REF netAdd +V_DDR_MCH_REF net
2009/05/29 SI2-->PV23 For HP request 42 Add a serial resistor (0ohm install) between pin 6 of PU401
and signal PM_RSMRST#.
30 2009/06/09 SI2-->PV 44 Change PQ604 from 2N7002 to MMBT3904
Add PR616 as 10K
For HP request
1
2
2009/05/29 Change PR62 to 8.06K_1%
PR61 to 8.66K_1%
PR67 to 45.3K_1%
46Because table of AC adapters has been expanded.SI2-->PV24
5
35 2009/07/04 SI2-->PV
(MEMO)
Fine tune enable signal level to make sure the switch
can work normally
41 Change PR330 from 20K to 60.4K
PC322 from 0.01u to 0.1u
21 2009/05/25 SI2-->PV For S5 power consumption,
reserve additional circuit to enable +5VALWP at battery mode
41 Add PR319 as 0
PQ308 as SSM3K7220FU
PR329 as 100K
PR330 as 15K
PC322 as 0.01u
Resserve PR328
22 For AirLine adapter detection issue 39 Un-install PR127
Add PR141 as 78.6K between Vin and PU103.3
Change net name AC_AND_CHG to AC_ADP_PRES
4
Modify circuit for Debug board 40 Change PR34 from 100 ohm to 0 ohm2009/01/16 DB2-->SI1
37 2009/07/07 PV-->PV-R Add a pull down resistor to prevent the floating of PQ307 Add PR331 as 1K41
38 2009/07/07 Change PC302 from 0.22u to 1uPV-->PV-R TI request to prevent LDO issue 41
34 2009/06/26 SI2-->PV
(MEMO)
Fine tune Vsense feedback to prevnet feedback saturation issue 45 Change PR218 and PR231 from 3.65K to 16.5K
PR223 from 100K to 21.5K
PR224 from 17.4K to 95.3K
PR206 from 14K to 15K
Add PR219 and PR233 as 4.02K
2009/06/05 SI2-->PV26 Enable +5VALW at S5 when battery mode 41 Uninstall PR319
Add PR328 as 0
BATCON circuit is removed due to SMSc 1098 design. 40 Delete PD10, PR45 and PU9
10
2008/12/11 DB1-->DB2
2009/02/19 DB2-->SI1 39For EMI request Add PC125 and PC128 as 0.1u
7
36 2009/07/07 PV-->PV-R Reserve a dummy load to prevent the leakage issue in the
future. That issue has happened on PUMA platform
42 Reserve PR434 as 1K
17 2009/04/16 SI1-->SI2 For EMI request 41 Change PD18 and PD19 from BAV99 to PJSOT24CW
Delete PD20
14 2009/04/07 SI1-->SI2 For HP's request,
add a diode which connects the B++ and 51125_PWR
41 Add PD306 as 1SS355
2009/02/03 DB2-->SI1 Modify the Vin/Charge detector 39 Fine tune the trigger point
2009/02/03 DB2-->SI1 Modify the watch-dog sequence 39 Change PR133.1 and PQ108.3 to +3VL
2009/02/03 DB2-->SI1 Fine tune Power monitor setting 39 Change PR143 from 100 to 11K
Change PR145 from 33K to 39.2K
39 2009/07/15 PV-->PV-R TI request to prevent LDO issue
(Capacitance on VREG5 should be 33u at least)
Change PC315 from 10u to 22u
PC26 from 1u to 10u
41
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Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
HW Changed-List History-1
48 54Thursday, August 27, 2009
2007/08/02 2009/09/15Compal Electronics, Inc.
Version Change ListVersion Change ListVersion Change ListVersion Change List ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit
ItemItemItemItem Issue DIssue DIssue DIssue DescriptionescriptionescriptionescriptionDateDateDateDateReqReqReqRequestuestuestuest
OwnOwnOwnOwnerererer SoSoSoSolution Descriptionlution Descriptionlution Descriptionlution Description Rev.Rev.Rev.Rev.PaPaPaPage#ge#ge#ge# TTTTitleitleitleitle
1111 33333333 HP BIHP BIHP BIHP BIOSOSOSOSKBC 1KBC 1KBC 1KBC 1098098098098 11111111/28/28/28/28 HP BIOS team design chanHP BIOS team design chanHP BIOS team design chanHP BIOS team design changegegege remove ADremove ADremove ADremove ADP_DET# signal connection from pin 80 of KBCP_DET# signal connection from pin 80 of KBCP_DET# signal connection from pin 80 of KBCP_DET# signal connection from pin 80 of KBC
to to to to pin 87 (GPIO9) pin 87 (GPIO9) pin 87 (GPIO9) pin 87 (GPIO9)
0.20.20.20.2
22223333444455556666
77778888999910101010111111111212121213131313141414141515151516161616171717171818181819191919
20202020
29292929 LPCLPCLPCLPC Debug port Debug port Debug port Debug port 11111111/28/28/28/28 HP BIHP BIHP BIHP BIOSOSOSOS LPCLPCLPCLPC debug card can't work debug card can't work debug card can't work debug card can't work change JP21change JP21change JP21change JP21.16 conection from DEBUG_KBCRST to "51125_PWR".16 conection from DEBUG_KBCRST to "51125_PWR".16 conection from DEBUG_KBCRST to "51125_PWR".16 conection from DEBUG_KBCRST to "51125_PWR" 0.20.20.20.2
29292929 VGAVGAVGAVGA 11111111/28/28/28/28 HHHHP P P P DeDeDeDesign change for RS880M VGA I2C DDCsign change for RS880M VGA I2C DDCsign change for RS880M VGA I2C DDCsign change for RS880M VGA I2C DDC deldeldeldelete R101, R102, Q18,Q19ete R101, R102, Q18,Q19ete R101, R102, Q18,Q19ete R101, R102, Q18,Q19 0.20.20.20.2
30,30,30,30,31313131 USBUSBUSBUSB 12121212/1/1/1/1 CCCCompalompalompalompal all all all all USB board can't work USB board can't work USB board can't work USB board can't work change change change change USB PWR switch enable signal from SLP_S5# to SLP_S5USB PWR switch enable signal from SLP_S5# to SLP_S5USB PWR switch enable signal from SLP_S5# to SLP_S5USB PWR switch enable signal from SLP_S5# to SLP_S5 0.20.20.20.2
4444 TheTheTheThermal senseorrmal senseorrmal senseorrmal senseor 12121212/1/1/1/1 CCCCompalompalompalompal System cSystem cSystem cSystem can't power onan't power onan't power onan't power on thermal sensthermal sensthermal sensthermal sensor change from ADM1032 to EMC1402 or change from ADM1032 to EMC1402 or change from ADM1032 to EMC1402 or change from ADM1032 to EMC1402 0.20.20.20.2
29292929 LPCLPCLPCLPC Debug port Debug port Debug port Debug port 12121212/2/2/2/2 HP BIHP BIHP BIHP BIOSOSOSOS LPCLPCLPCLPC debug card can't work debug card can't work debug card can't work debug card can't work chanchanchanchange JP21.12 conection from "B+" to "51125_PWR" & change ge JP21.12 conection from "B+" to "51125_PWR" & change ge JP21.12 conection from "B+" to "51125_PWR" & change ge JP21.12 conection from "B+" to "51125_PWR" & change
JP21.16 conection from "DEBUG_KBCRST" to "VCC1_PWRGJP21.16 conection from "DEBUG_KBCRST" to "VCC1_PWRGJP21.16 conection from "DEBUG_KBCRST" to "VCC1_PWRGJP21.16 conection from "DEBUG_KBCRST" to "VCC1_PWRGD"D"D"D"0.20.20.20.2
27272727 USB (WLAN conn) USB (WLAN conn) USB (WLAN conn) USB (WLAN conn) 12121212/2/2/2/2 HPHPHPHP AMD platforAMD platforAMD platforAMD platform is not support WiMAXm is not support WiMAXm is not support WiMAXm is not support WiMAX remove USB20remove USB20remove USB20remove USB20_N9\P9 from WLAN connector (JP9)_N9\P9 from WLAN connector (JP9)_N9\P9 from WLAN connector (JP9)_N9\P9 from WLAN connector (JP9) 0.20.20.20.2
27272727 WWWWWANWANWANWAN 12121212/2/2/2/2 HPHPHPHP HPHPHPHP Comm team design change Comm team design change Comm team design change Comm team design change reserve R5reserve R5reserve R5reserve R513 for LAN_PCIE_WAKE# of JP10 pin113 for LAN_PCIE_WAKE# of JP10 pin113 for LAN_PCIE_WAKE# of JP10 pin113 for LAN_PCIE_WAKE# of JP10 pin1 0.20.20.20.2
32323232 VGAVGAVGAVGA 12121212/2/2/2/2 HPHPHPHP VGA caVGA caVGA caVGA can't work issuen't work issuen't work issuen't work issue change change change change DOCK_ID signal pullup power rail to +5VSDOCK_ID signal pullup power rail to +5VSDOCK_ID signal pullup power rail to +5VSDOCK_ID signal pullup power rail to +5VS 0.20.20.20.2
11111111 NBNBNBNB 12121212/2/2/2/2 HPHPHPHP HP dHP dHP dHP design changeesign changeesign changeesign change change R61 frochange R61 frochange R61 frochange R61 from 10Kohm to 0 ohmm 10Kohm to 0 ohmm 10Kohm to 0 ohmm 10Kohm to 0 ohm 0.20.20.20.2
32323232 DODODODOCKCKCKCK 12121212/2/2/2/2 HPHPHPHP HP dHP dHP dHP design changeesign changeesign changeesign change rerereremove Q23, Q5, Q6, R457~R460,R483,C682,C683move Q23, Q5, Q6, R457~R460,R483,C682,C683move Q23, Q5, Q6, R457~R460,R483,C682,C683move Q23, Q5, Q6, R457~R460,R483,C682,C683 0.20.20.20.2
18181818 DPDPDPDP 12121212/2/2/2/2 HPHPHPHP HP dHP dHP dHP design changeesign changeesign changeesign change remoremoremoremove C253, R467. add R514, Q98ve C253, R467. add R514, Q98ve C253, R467. add R514, Q98ve C253, R467. add R514, Q98 0.20.20.20.2
17171717 LCDLCDLCDLCD 12121212/3/3/3/3 CCCCompalompalompalompal CompaCompaCompaCompal ME design changel ME design changel ME design changel ME design change chanchanchanchange the LCD connector typege the LCD connector typege the LCD connector typege the LCD connector type 0.20.20.20.2
32323232 DODODODOCKCKCKCK 12121212/3/3/3/3 HPHPHPHP HP dHP dHP dHP design changeesign changeesign changeesign change remove SER_SHDremove SER_SHDremove SER_SHDremove SER_SHD signal & pin76 pullup 10k ohm to +5VS signal & pin76 pullup 10k ohm to +5VS signal & pin76 pullup 10k ohm to +5VS signal & pin76 pullup 10k ohm to +5VS 0.20.20.20.2
25252525 NNNNICICICIC 12121212/3/3/3/3 HPHPHPHP V1.2_V1.2_V1.2_V1.2_LAN leakage issueLAN leakage issueLAN leakage issueLAN leakage issue chchchchange power rail friom +1.2V_HT to +1.2VALWange power rail friom +1.2V_HT to +1.2VALWange power rail friom +1.2V_HT to +1.2VALWange power rail friom +1.2V_HT to +1.2VALW 0.20.20.20.2
32323232 DODODODOCKCKCKCK 12121212/3/3/3/3 HPHPHPHP all the FETs call the FETs call the FETs call the FETs c icuit will be located inside docking stationicuit will be located inside docking stationicuit will be located inside docking stationicuit will be located inside docking station All theAll theAll theAll the CEC and CAD pins (143,46,142 and 47) will left as NC CEC and CAD pins (143,46,142 and 47) will left as NC CEC and CAD pins (143,46,142 and 47) will left as NC CEC and CAD pins (143,46,142 and 47) will left as NC 0.20.20.20.2
34343434 Super IOSuper IOSuper IOSuper IO 12121212/4/4/4/4 CCCCompalompalompalompal CompalCompalCompalCompal design change design change design change design change Change SupChange SupChange SupChange Super IO IT8305E to LPC47N217er IO IT8305E to LPC47N217er IO IT8305E to LPC47N217er IO IT8305E to LPC47N217 0.20.20.20.2
15151515 CLCLCLCLK genK genK genK gen 12121212/4/4/4/4 CCCCompalompalompalompal CompalCompalCompalCompal design change design change design change design change add CLK_14M_SIO for Super IO & delete CLK_48M_SIOadd CLK_14M_SIO for Super IO & delete CLK_48M_SIOadd CLK_14M_SIO for Super IO & delete CLK_48M_SIOadd CLK_14M_SIO for Super IO & delete CLK_48M_SIO 0.20.20.20.2
9999 DDRDDRDDRDDRIIIIIIII 12121212/5/5/5/5 CCCCompalompalompalompal layout layout layout layout placement issueplacement issueplacement issueplacement issue cgange rsistocgange rsistocgange rsistocgange rsistor size from 8P4R to 0402r size from 8P4R to 0402r size from 8P4R to 0402r size from 8P4R to 0402 0.20.20.20.2
30303030 USBUSBUSBUSB 12121212/5/5/5/5 HPHPHPHP re-re-re-re-define the USB debug port (USB port 0)define the USB debug port (USB port 0)define the USB debug port (USB port 0)define the USB debug port (USB port 0) Swap JUSB1 Swap JUSB1 Swap JUSB1 Swap JUSB1 & JUSB2's USB signal & JUSB2's USB signal & JUSB2's USB signal & JUSB2's USB signal 0.20.20.20.2
21212121 25252525 NNNNICICICIC 12121212/5/5/5/5 V1.2_LAN lV1.2_LAN lV1.2_LAN lV1.2_LAN leakage issue & improve layouteakage issue & improve layouteakage issue & improve layouteakage issue & improve layout Swap pSwap pSwap pSwap power rail +1.2V_HT & V1.2_LANower rail +1.2V_HT & V1.2_LANower rail +1.2V_HT & V1.2_LANower rail +1.2V_HT & V1.2_LANHPHPHPHP 0.20.20.20.2
0.20.20.20.222222222 25252525 NNNNICICICIC 12121212/5/5/5/5 HPHPHPHP HP recomHP recomHP recomHP recommand that 8075 is not neededmand that 8075 is not neededmand that 8075 is not neededmand that 8075 is not needed remove R246,R240remove R246,R240remove R246,R240remove R246,R240,R241,R247,R244,R238,C421,U14 & USB signal,R241,R247,R244,R238,C421,U14 & USB signal,R241,R247,R244,R238,C421,U14 & USB signal,R241,R247,R244,R238,C421,U14 & USB signal
23232323 27272727 WWAMWWAMWWAMWWAM 12121212/5/5/5/5 HPHPHPHP HP dHP dHP dHP design changeesign changeesign changeesign change add Wadd Wadd Wadd WWAM wakeup circuitWAM wakeup circuitWAM wakeup circuitWAM wakeup circuit 0.20.20.20.2
24242424 15151515 CLCLCLCLK genK genK genK gen 12121212/8/8/8/8 HPHPHPHP Adding clk requAdding clk requAdding clk requAdding clk request signal for media/1394 daughter est signal for media/1394 daughter est signal for media/1394 daughter est signal for media/1394 daughter
board forboard forboard forboard for power saving benefit power saving benefit power saving benefit power saving benefit
cccchange CLK_PCIE_CARD#/CLK_PCIE_CARD from pin25,26hange CLK_PCIE_CARD#/CLK_PCIE_CARD from pin25,26hange CLK_PCIE_CARD#/CLK_PCIE_CARD from pin25,26hange CLK_PCIE_CARD#/CLK_PCIE_CARD from pin25,26
to pin 22 to pin 22 to pin 22 to pin 22,23 & rename pin24 to CRD_REQ# & connect to JP29 pin20,23 & rename pin24 to CRD_REQ# & connect to JP29 pin20,23 & rename pin24 to CRD_REQ# & connect to JP29 pin20,23 & rename pin24 to CRD_REQ# & connect to JP29 pin20
0.20.20.20.2
26262626 4444 CCCCPUPUPUPU 12121212/8/8/8/8 HPHPHPHP AMD AMD AMD AMD S1G3 request for +1.2V_HT power railS1G3 request for +1.2V_HT power railS1G3 request for +1.2V_HT power railS1G3 request for +1.2V_HT power rail C1C1C1C1,C2,C7 change from 4.7U to 10U ,C2,C7 change from 4.7U to 10U ,C2,C7 change from 4.7U to 10U ,C2,C7 change from 4.7U to 10U 0.20.20.20.2
27272727 26262626 WWAMWWAMWWAMWWAM 12121212/9/9/9/9 HPHPHPHP HP dHP dHP dHP design changeesign changeesign changeesign change changechangechangechange R279 pin1 power rail from +3VALW to +3VS R279 pin1 power rail from +3VALW to +3VS R279 pin1 power rail from +3VALW to +3VS R279 pin1 power rail from +3VALW to +3VS 0.20.20.20.2
add R5add R5add R5add R534343434 0.20.20.20.2HPHPHPHP design change for RF design change for RF design change for RF design change for RFHPHPHPHP12121212/10/10/10/1028282828 4444 FFFFANANANAN
29292929 33333333 KKKKBCBCBCBC 12121212/10/10/10/10 CCCCompalompalompalompal de de de design change to meet SMSC guidelinesign change to meet SMSC guidelinesign change to meet SMSC guidelinesign change to meet SMSC guideline add C7add C7add C7add C710101010 0.20.20.20.2
30303030 31313131 KKKKBCBCBCBC 12121212/12/12/12/12 HPHPHPHP HP dHP dHP dHP design changeesign changeesign changeesign change change BAchange BAchange BAchange BATCON to ADP_DET# and connection Pin87 & pin92TCON to ADP_DET# and connection Pin87 & pin92TCON to ADP_DET# and connection Pin87 & pin92TCON to ADP_DET# and connection Pin87 & pin92 0.20.20.20.2
31313131 18181818 Display Display Display Display PortPortPortPort 12121212/15/15/15/15 HPHPHPHP add leveadd leveadd leveadd leve l shit control for DPl shit control for DPl shit control for DPl shit control for DP add Q1add Q1add Q1add Q102, R53502, R53502, R53502, R535 0.20.20.20.2
32323232 6666 LeaLeaLeaLeakagekagekagekage 12121212/18/18/18/18 HPHPHPHP llll eakage fro +1.8VSeakage fro +1.8VSeakage fro +1.8VSeakage fro +1.8VS cccchange power rail from +1.8VS to +1.8Vhange power rail from +1.8VS to +1.8Vhange power rail from +1.8VS to +1.8Vhange power rail from +1.8VS to +1.8V 0.20.20.20.2
![Page 49: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/49.jpg)
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Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
HW Changed-List History-1
49 54Thursday, August 27, 2009
2007/08/02 2009/09/15Compal Electronics, Inc.
Version Change ListVersion Change ListVersion Change ListVersion Change List ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit
ItemItemItemItem Issue DIssue DIssue DIssue DescriptionescriptionescriptionescriptionDateDateDateDateReqReqReqRequestuestuestuest
OwnOwnOwnOwnerererer SoSoSoSolution Descriptionlution Descriptionlution Descriptionlution Description Rev.Rev.Rev.Rev.PaPaPaPage#ge#ge#ge# TTTTitleitleitleitle
1111 28282828 CCCCompalompalompalompalKBKBKBKB connector connector connector connector 12121212/24/24/24/24 0.30.30.30.3
2222333344445555
6666
7777
8888999910101010
11111111121212121313131314141414151515151616161617171717
18181818
19191919
20202020
2121212122222222
232323232424242426262626
Key Board matrix eKey Board matrix eKey Board matrix eKey Board matrix errorrrorrrorrror Correct the right Key Board MatrixCorrect the right Key Board MatrixCorrect the right Key Board MatrixCorrect the right Key Board Matrix26262626 LLLLANANANAN 12121212/31/31/31/31 CCCCompalompalompalompal LAN cable can'tLAN cable can'tLAN cable can'tLAN cable can't dectect dectect dectect dectect conconconconnection JRJ45 pin10 to GNDnection JRJ45 pin10 to GNDnection JRJ45 pin10 to GNDnection JRJ45 pin10 to GND 0.30.30.30.3
32323232 DoDoDoDockingckingckingcking 1/1/1/1/15151515 HPHPHPHP Docking connector pin ouDocking connector pin ouDocking connector pin ouDocking connector pin out errort errort errort error delete pdelete pdelete pdelete pin 180 (PLT_RST#) & let it NCin 180 (PLT_RST#) & let it NCin 180 (PLT_RST#) & let it NCin 180 (PLT_RST#) & let it NC 0.30.30.30.3
32323232 DoDoDoDockingckingckingcking 1/1/1/1/15151515 HPHPHPHP Docking connector pin ouDocking connector pin ouDocking connector pin ouDocking connector pin out errort errort errort error SwapSwapSwapSwap pin assignment of pin2,3 & pin183,184 pin assignment of pin2,3 & pin183,184 pin assignment of pin2,3 & pin183,184 pin assignment of pin2,3 & pin183,184 0.30.30.30.3
32323232 DoDoDoDockingckingckingcking 1/1/1/1/15151515 HPHPHPHP Docking connector pin ouDocking connector pin ouDocking connector pin ouDocking connector pin out errort errort errort error 0.30.30.30.3Add conAdd conAdd conAdd connection for pin 51 to signal DOCK_AUX- nection for pin 51 to signal DOCK_AUX- nection for pin 51 to signal DOCK_AUX- nection for pin 51 to signal DOCK_AUX-
pin 52 to signalpin 52 to signalpin 52 to signalpin 52 to signal DOCK_AUX+, pin 138 (HDMICLK_UMA) DOCK_AUX+, pin 138 (HDMICLK_UMA) DOCK_AUX+, pin 138 (HDMICLK_UMA) DOCK_AUX+, pin 138 (HDMICLK_UMA)
,pin 137 ( H,pin 137 ( H,pin 137 ( H,pin 137 ( HDMIDAT_UMA)DMIDAT_UMA)DMIDAT_UMA)DMIDAT_UMA)
32323232 DoDoDoDockingckingckingcking 1/1/1/1/15151515 HPHPHPHP Docking connector pin ouDocking connector pin ouDocking connector pin ouDocking connector pin out errort errort errort error let pin77let pin77let pin77let pin77 & pin 78 NC pin because of the dock side is GND & pin 78 NC pin because of the dock side is GND & pin 78 NC pin because of the dock side is GND & pin 78 NC pin because of the dock side is GND 0.30.30.30.3
32323232 DoDoDoDockingckingckingcking 1/1/1/1/15151515 HPHPHPHP can't programing serial pocan't programing serial pocan't programing serial pocan't programing serial port by BIOSrt by BIOSrt by BIOSrt by BIOS SER_SHD signal (after Q96) connect to pin 10 of JP35SER_SHD signal (after Q96) connect to pin 10 of JP35SER_SHD signal (after Q96) connect to pin 10 of JP35SER_SHD signal (after Q96) connect to pin 10 of JP35
& & & & let pin76 NClet pin76 NClet pin76 NClet pin76 NC
0.30.30.30.3
25252525 NNNNICICICIC 1/1/1/1/15151515 HPHPHPHP can't boot in DC modecan't boot in DC modecan't boot in DC modecan't boot in DC mode aaaadd Q2 to isolated when DC modedd Q2 to isolated when DC modedd Q2 to isolated when DC modedd Q2 to isolated when DC mode 0.30.30.30.3
31313131 WLAN_LEDWLAN_LEDWLAN_LEDWLAN_LED 1/1/1/1/15151515 CCCCompalompalompalompal WLAN_LED issWLAN_LED issWLAN_LED issWLAN_LED issue ue ue ue correct the net name to WL/BT_LED#correct the net name to WL/BT_LED#correct the net name to WL/BT_LED#correct the net name to WL/BT_LED# 0.30.30.30.3
28282828 MMMMDCDCDCDC 1/1/1/1/22222222 HPHPHPHP Modem disable GPIO is no neededModem disable GPIO is no neededModem disable GPIO is no neededModem disable GPIO is no needed delete U17 RR173, connect HAD_RST#_MDC to pin 11delete U17 RR173, connect HAD_RST#_MDC to pin 11delete U17 RR173, connect HAD_RST#_MDC to pin 11delete U17 RR173, connect HAD_RST#_MDC to pin 11
of MDC v of MDC v of MDC v of MDC via a serial resistor (4.7K)ia a serial resistor (4.7K)ia a serial resistor (4.7K)ia a serial resistor (4.7K)
0.30.30.30.3
21212121 PWR on CKTPWR on CKTPWR on CKTPWR on CKT 2/32/32/32/3 CCCCompalompalompalompal system auto power on after un-system auto power on after un-system auto power on after un-system auto power on after un-plug ACplug ACplug ACplug AC change R179 power rail from +3VALW to +3change R179 power rail from +3VALW to +3change R179 power rail from +3VALW to +3change R179 power rail from +3VALW to +3VLVLVLVL 0.30.30.30.3
29,29,29,29,33333333 KKKKBCBCBCBC 2/32/32/32/3 HPHPHPHP for SPI lock feature & only apply to AMD pfor SPI lock feature & only apply to AMD pfor SPI lock feature & only apply to AMD pfor SPI lock feature & only apply to AMD platformlatformlatformlatform change R375 to 0ohm & connect to U19 pichange R375 to 0ohm & connect to U19 pichange R375 to 0ohm & connect to U19 pichange R375 to 0ohm & connect to U19 pin3n3n3n3 0.30.30.30.3
32323232 DoDoDoDockingckingckingcking 2/32/32/32/3 HPHPHPHP DisplayDisplayDisplayDisplay port working not right port working not right port working not right port working not right Swap pin 146 and pin 145 con Swap pin 146 and pin 145 con Swap pin 146 and pin 145 con Swap pin 146 and pin 145 connectionnectionnectionnection 0.30.30.30.3
32323232 DoDoDoDockingckingckingcking 2/32/32/32/3 HPHPHPHP DisplayDisplayDisplayDisplay port working not right port working not right port working not right port working not right swap pin 52 and pin 51 connec swap pin 52 and pin 51 connec swap pin 52 and pin 51 connec swap pin 52 and pin 51 connectiontiontiontion 0.30.30.30.3
31313131 card reacard reacard reacard readerderderder 2/32/32/32/3 HPHPHPHP to beefup with enough decouplingto beefup with enough decouplingto beefup with enough decouplingto beefup with enough decoupling cap on MB cap on MB cap on MB cap on MB chanchanchanchange C684 from 0.1U to 4.7Uge C684 from 0.1U to 4.7Uge C684 from 0.1U to 4.7Uge C684 from 0.1U to 4.7U 0.30.30.30.3
32323232 DoDoDoDockingckingckingcking 2/42/42/42/4 HPHPHPHP ddddocking station design changeocking station design changeocking station design changeocking station design change chanchanchanchange pin11, pin178, oin179 from NC to +5VSge pin11, pin178, oin179 from NC to +5VSge pin11, pin178, oin179 from NC to +5VSge pin11, pin178, oin179 from NC to +5VS 0.30.30.30.3
32323232 DoDoDoDockingckingckingcking 2/42/42/42/4 HPHPHPHP docking station power LED abnordocking station power LED abnordocking station power LED abnordocking station power LED abnormalmalmalmal aaaadd Q3 for invert STB_LED# signal behaviordd Q3 for invert STB_LED# signal behaviordd Q3 for invert STB_LED# signal behaviordd Q3 for invert STB_LED# signal behavior 0.30.30.30.3
23232323 SBSBSBSB710710710710 2/52/52/52/5 HPHPHPHP forforforfor improve battery life improve battery life improve battery life improve battery life remove IDE PATA controller and flash controremove IDE PATA controller and flash controremove IDE PATA controller and flash controremove IDE PATA controller and flash controller power rail ller power rail ller power rail ller power rail
++++3VS) & connect pin 1 of R170 to pin M5 of SB7103VS) & connect pin 1 of R170 to pin M5 of SB7103VS) & connect pin 1 of R170 to pin M5 of SB7103VS) & connect pin 1 of R170 to pin M5 of SB710
0.30.30.30.320202020
17171717 LCD PaneLCD PaneLCD PaneLCD Panel l l l 2/62/62/62/6 HPHPHPHP LLLLCD Panel flashing issueCD Panel flashing issueCD Panel flashing issueCD Panel flashing issue rrrremove R106, D41 & add R540emove R106, D41 & add R540emove R106, D41 & add R540emove R106, D41 & add R540 0.30.30.30.3
17171717 card reacard reacard reacard reader der der der 2/62/62/62/6 HPHPHPHP for power-down of 1394/cardreadfor power-down of 1394/cardreadfor power-down of 1394/cardreadfor power-down of 1394/cardreader chip er chip er chip er chip
when no card/1394 when no card/1394 when no card/1394 when no card/1394 insertedinsertedinsertedinserted
aaaadd Q104~Q107, R541~R543dd Q104~Q107, R541~R543dd Q104~Q107, R541~R543dd Q104~Q107, R541~R543 0.30.30.30.3
11111111 18181818 DPDPDPDP 2/62/62/62/6 HPHPHPHP design chadesign chadesign chadesign changengengenge changchangchangchange R60 & R125 from 20k to 100K ohme R60 & R125 from 20k to 100K ohme R60 & R125 from 20k to 100K ohme R60 & R125 from 20k to 100K ohm32323232 DoDoDoDockingckingckingcking 2/92/92/92/9 CCCCompalompalompalompal RJ45 green LED doesn't light with cable wRJ45 green LED doesn't light with cable wRJ45 green LED doesn't light with cable wRJ45 green LED doesn't light with cable whilehilehilehile
system po system po system po system power off with AC inwer off with AC inwer off with AC inwer off with AC in
0.30.30.30.3
0.30.30.30.3change the R340 power rail from +5VS to +5change the R340 power rail from +5VS to +5change the R340 power rail from +5VS to +5change the R340 power rail from +5VS to +5VALWVALWVALWVALW
30303030 USBUSBUSBUSB 2/2/2/2/10101010 HPHPHPHP correct the USB debug port 0correct the USB debug port 0correct the USB debug port 0correct the USB debug port 0 location location location location swap JUSB2 & JUSB3 siswap JUSB2 & JUSB3 siswap JUSB2 & JUSB3 siswap JUSB2 & JUSB3 signalgnalgnalgnal 0.30.30.30.3
19191919 RRRRTCTCTCTC 2/2/2/2/11111111 HPHPHPHP forforforfor RTC battery life issue RTC battery life issue RTC battery life issue RTC battery life issue chachachachange D43 pin2 power rail from +3VL to +VREG3_51125nge D43 pin2 power rail from +3VL to +VREG3_51125nge D43 pin2 power rail from +3VL to +VREG3_51125nge D43 pin2 power rail from +3VL to +VREG3_51125 0.30.30.30.3
19191919 SBSBSBSB710710710710 2/2/2/2/12121212 HPHPHPHP port 9,10,11 are un-used and BIOport 9,10,11 are un-used and BIOport 9,10,11 are un-used and BIOport 9,10,11 are un-used and BIOS can disable theS can disable theS can disable theS can disable the
one OHCI one OHCI one OHCI one OHCI controller controller controller controller
chachachachange the USB port from port 11 to port 12nge the USB port from port 11 to port 12nge the USB port from port 11 to port 12nge the USB port from port 11 to port 12 0.30.30.30.3
![Page 50: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/50.jpg)
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Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
HW Changed-List History-1
50 54Thursday, August 27, 2009
2007/08/02 2009/09/15Compal Electronics, Inc.
Version Change ListVersion Change ListVersion Change ListVersion Change List ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit
ItemItemItemItem Issue DIssue DIssue DIssue DescriptionescriptionescriptionescriptionDateDateDateDateReqReqReqRequestuestuestuest
OwnOwnOwnOwnerererer SoSoSoSolution Descriptionlution Descriptionlution Descriptionlution Description Rev.Rev.Rev.Rev.PaPaPaPage#ge#ge#ge# TTTTitleitleitleitle
25252525 HPHPHPHPNNNNICICICIC 2/2/2/2/14141414 0.30.30.30.3design change for 8059 (co-ldesign change for 8059 (co-ldesign change for 8059 (co-ldesign change for 8059 (co-lay)ay)ay)ay) aaaadd R544~R548dd R544~R548dd R544~R548dd R544~R54827272727
28282828 31313131 AuAuAuAudio Express dio Express dio Express dio Express 2/2/2/2/17171717 HPHPHPHP to ito ito ito improve battery lifemprove battery lifemprove battery lifemprove battery life change both pin 21 of JP34 and pin 1 of C646 connection change both pin 21 of JP34 and pin 1 of C646 connection change both pin 21 of JP34 and pin 1 of C646 connection change both pin 21 of JP34 and pin 1 of C646 connection
to +VREG3to +VREG3to +VREG3to +VREG3_51125 (from +3VL_51125 (from +3VL_51125 (from +3VL_51125 (from +3VL
0.30.30.30.3
29292929 20202020 VRAM VRAM VRAM VRAM IDIDIDID 2/2/2/2/17171717 CCCCompalompalompalompal add VRAM ID for side poert memory 2nd sourceadd VRAM ID for side poert memory 2nd sourceadd VRAM ID for side poert memory 2nd sourceadd VRAM ID for side poert memory 2nd source adadadadd R549, R550,R551,R176d R549, R550,R551,R176d R549, R550,R551,R176d R549, R550,R551,R176 0.30.30.30.3
30303030 32323232 DoDoDoDockingckingckingcking 2/2/2/2/18181818 HPHPHPHP DP's 1DP's 1DP's 1DP's 16 AC coupling remove to docking station6 AC coupling remove to docking station6 AC coupling remove to docking station6 AC coupling remove to docking station deletet C659~C666, C512~C519deletet C659~C666, C512~C519deletet C659~C666, C512~C519deletet C659~C666, C512~C519 0.30.30.30.3
31313131 32323232 DoDoDoDockingckingckingcking 2/2/2/2/18181818 HPHPHPHP SATA'sSATA'sSATA'sSATA's 4 AC coupling remove to docking station 4 AC coupling remove to docking station 4 AC coupling remove to docking station 4 AC coupling remove to docking station deletet R342~R3deletet R342~R3deletet R342~R3deletet R342~R345454545 0.30.30.30.3
32323232 32323232 DoDoDoDockingckingckingcking 2/2/2/2/19191919 CCCCompalompalompalompal duedueduedue to DP current is 500mA to DP current is 500mA to DP current is 500mA to DP current is 500mA changechangechangechange F2 from 3A to 0.5A F2 from 3A to 0.5A F2 from 3A to 0.5A F2 from 3A to 0.5A 0.30.30.30.3
![Page 51: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/51.jpg)
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Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 1.0
HW Changed-List History-1
51 54Thursday, August 27, 2009
2007/08/02 2009/09/15Compal Electronics, Inc.
Version Change ListVersion Change ListVersion Change ListVersion Change List ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit
ItemItemItemItem Issue DIssue DIssue DIssue DescriptionescriptionescriptionescriptionDateDateDateDateReqReqReqRequestuestuestuest
OwnOwnOwnOwnerererer SoSoSoSolution Descriptionlution Descriptionlution Descriptionlution Description Rev.Rev.Rev.Rev.PaPaPaPage#ge#ge#ge# TTTTitleitleitleitle
25252525 HPHPHPHPNNNNICICICIC 3/3/3/3/23232323 0.40.40.40.41111 power-down NIC instead of low-powerpower-down NIC instead of low-powerpower-down NIC instead of low-powerpower-down NIC instead of low-power mode mode mode mode aaaadd Q34, R554, C712, R555, Q107 & delete R186, R239dd Q34, R554, C712, R555, Q107 & delete R186, R239dd Q34, R554, C712, R555, Q107 & delete R186, R239dd Q34, R554, C712, R555, Q107 & delete R186, R2392222 4444 FFFFanananan 3/3/3/3/23232323 CCCCompalompalompalompal Fan shake when temperaturFan shake when temperaturFan shake when temperaturFan shake when temperature in 70 degreee in 70 degreee in 70 degreee in 70 degree addaddaddadd Q108, C556 & C557 Q108, C556 & C557 Q108, C556 & C557 Q108, C556 & C557 0.40.40.40.4
3333 31313131 card reacard reacard reacard readerderderder 3/3/3/3/24242424 HPHPHPHP 1394 detection circuit design chan1394 detection circuit design chan1394 detection circuit design chan1394 detection circuit design changegegege delete R533, R552,R543 & add R559, R558, Q1delete R533, R552,R543 & add R559, R558, Q1delete R533, R552,R543 & add R559, R558, Q1delete R533, R552,R543 & add R559, R558, Q108080808 0.40.40.40.4
4444 29292929 SSSSPIPIPIPI 3/3/3/3/25252525 HPHPHPHP SMsC recommand to add 100k ohm fro select pinSMsC recommand to add 100k ohm fro select pinSMsC recommand to add 100k ohm fro select pinSMsC recommand to add 100k ohm fro select pin aaaadd R560dd R560dd R560dd R560 0.40.40.40.4
5555 27,27,27,27, WLAN,WLAN,WLAN,WLAN, 3/3/3/3/25252525 HPHPHPHP power MOSFET can not be fully shutoff wpower MOSFET can not be fully shutoff wpower MOSFET can not be fully shutoff wpower MOSFET can not be fully shutoff with ith ith ith
+3V/+5+3V/+5+3V/+5+3V/+5V levelV levelV levelV level
change R277 power rail from +3VS to +5Vchange R277 power rail from +3VS to +5Vchange R277 power rail from +3VS to +5Vchange R277 power rail from +3VS to +5VS & change R277S & change R277S & change R277S & change R277
from 680 from 680 from 680 from 680 to 47k & R272 from 220K to 100K, R234 changeto 47k & R272 from 220K to 100K, R234 changeto 47k & R272 from 220K to 100K, R234 changeto 47k & R272 from 220K to 100K, R234 change
power rail to +5VALW & change to 10Kpower rail to +5VALW & change to 10Kpower rail to +5VALW & change to 10Kpower rail to +5VALW & change to 10K
0.40.40.40.425252525 NNNNICICICIC
6666 27272727 WLWLWLWLANANANAN 3/3/3/3/25252525 HPHPHPHP delete CLK_PCIdelete CLK_PCIdelete CLK_PCIdelete CLK_PCIE_WLAN_REQ# from JP9 pin 7 E_WLAN_REQ# from JP9 pin 7 E_WLAN_REQ# from JP9 pin 7 E_WLAN_REQ# from JP9 pin 7
& connect CLK_P& connect CLK_P& connect CLK_P& connect CLK_PCIE_WLAN_REQ# to WLAN_OFFCIE_WLAN_REQ# to WLAN_OFFCIE_WLAN_REQ# to WLAN_OFFCIE_WLAN_REQ# to WLAN_OFF
0.40.40.40.4HP design chanHP design chanHP design chanHP design changegegege
7777 27272727 SBSBSBSB710710710710 3/3/3/3/25252525 HPHPHPHP HHHHP design change for GPIO56P design change for GPIO56P design change for GPIO56P design change for GPIO56 cccconnection CRD_REQ#_R to GPIO56onnection CRD_REQ#_R to GPIO56onnection CRD_REQ#_R to GPIO56onnection CRD_REQ#_R to GPIO56 0.40.40.40.4
8888 4,4,4,4, 6666 CCCCPUPUPUPU 3/3/3/3/30303030 HPHPHPHP HP design change for CPU ThermHP design change for CPU ThermHP design change for CPU ThermHP design change for CPU Thermalalalal change Q10 pin2 power rail from +1.8VS to +1.2V_change Q10 pin2 power rail from +1.8VS to +1.2V_change Q10 pin2 power rail from +1.8VS to +1.2V_change Q10 pin2 power rail from +1.8VS to +1.2V_HT HT HT HT
& connection thermal sensor pin4 (thermal#) to CPU dir& connection thermal sensor pin4 (thermal#) to CPU dir& connection thermal sensor pin4 (thermal#) to CPU dir& connection thermal sensor pin4 (thermal#) to CPU dirtertly.tertly.tertly.tertly.
0.40.40.40.4
9999 27272727 WWWWWANWANWANWAN 3/3/3/3/31313131 HPHPHPHP HP HP HP HP design change for WWAN dection pindesign change for WWAN dection pindesign change for WWAN dection pindesign change for WWAN dection pin ccccontion JP10 pin26 to Super IO GPIO23ontion JP10 pin26 to Super IO GPIO23ontion JP10 pin26 to Super IO GPIO23ontion JP10 pin26 to Super IO GPIO23 0.40.40.40.4
10101010 28282828 Point sPoint sPoint sPoint sticktickticktick 4/14/14/14/1 CCCCompalompalompalompal PoinPoinPoinPoint Stick pin out errort Stick pin out errort Stick pin out errort Stick pin out error SwapSwapSwapSwap from pin1 to pin8 from pin1 to pin8 from pin1 to pin8 from pin1 to pin8 0.40.40.40.4
11111111 33333333 KKKKBCBCBCBC 4/64/64/64/6 HPHPHPHP BOM chBOM chBOM chBOM changeangeangeange changchangchangchange pull down resistor on FET_A R443 from 1.2K toe pull down resistor on FET_A R443 from 1.2K toe pull down resistor on FET_A R443 from 1.2K toe pull down resistor on FET_A R443 from 1.2K to
10K; Change pulldown resistor on SB_PWRGD R367 10K; Change pulldown resistor on SB_PWRGD R367 10K; Change pulldown resistor on SB_PWRGD R367 10K; Change pulldown resistor on SB_PWRGD R367 fromfromfromfrom
1.2K to 1.2K to 1.2K to 1.2K to 4.7K 4.7K 4.7K 4.7K
0.40.40.40.4
12121212 35353535 PWR OKPWR OKPWR OKPWR OK 4/64/64/64/6 HPHPHPHP BOM chBOM chBOM chBOM changeangeangeange c c c change PWR_GD resistor values - change R399 to 31.6K_1%,hange PWR_GD resistor values - change R399 to 31.6K_1%,hange PWR_GD resistor values - change R399 to 31.6K_1%,hange PWR_GD resistor values - change R399 to 31.6K_1%,
change R400 to 88.7K_1%, cha change R400 to 88.7K_1%, cha change R400 to 88.7K_1%, cha change R400 to 88.7K_1%, changengengenge
R407 t R407 t R407 t R407 to 16.9K_1%, change R401 to 10K_5%o 16.9K_1%, change R401 to 10K_5%o 16.9K_1%, change R401 to 10K_5%o 16.9K_1%, change R401 to 10K_5%
0.40.40.40.4
13131313 6666 CCCCPUPUPUPU 4/64/64/64/6 HPHPHPHP BOM chBOM chBOM chBOM changeangeangeange change R35 value to 560 ohm (instead of 300 ohm)change R35 value to 560 ohm (instead of 300 ohm)change R35 value to 560 ohm (instead of 300 ohm)change R35 value to 560 ohm (instead of 300 ohm) 0.40.40.40.4
14141414 28282828 LLLLID SWITCHID SWITCHID SWITCHID SWITCH 4/64/64/64/6 HPHPHPHP LID_LID_LID_LID_SW# is triggering very intermittently andSW# is triggering very intermittently andSW# is triggering very intermittently andSW# is triggering very intermittently and
cause lockup in POST cause lockup in POST cause lockup in POST cause lockup in POST B173 B173 B173 B173
adadadadd Q110 & C713d Q110 & C713d Q110 & C713d Q110 & C713 0.40.40.40.4
15151515 21212121 power butpower butpower butpower buttontontonton 4/74/74/74/7 HPHPHPHP PrPrPrPress twice power to power on in DC modeess twice power to power on in DC modeess twice power to power on in DC modeess twice power to power on in DC mode cccchange R179 to 4.7Khange R179 to 4.7Khange R179 to 4.7Khange R179 to 4.7K 0.40.40.40.4
16161616 31,31,31,31, 33333333 KKKKBCBCBCBC 4/74/74/74/7 HPHPHPHP design change for detect 14" & 15.6" design change for detect 14" & 15.6" design change for detect 14" & 15.6" design change for detect 14" & 15.6" panel panel panel panel add GPIO03 (14vsadd GPIO03 (14vsadd GPIO03 (14vsadd GPIO03 (14vs15_FF_DETECT) on KBC15_FF_DETECT) on KBC15_FF_DETECT) on KBC15_FF_DETECT) on KBC 0.40.40.40.4
17171717 26262626 NNNNICICICIC 4/84/84/84/8 HPHPHPHP HHHHP design change for LED, NIC is locate on theP design change for LED, NIC is locate on theP design change for LED, NIC is locate on theP design change for LED, NIC is locate on the
r r r rear, not side of system. So, after docking, even ear, not side of system. So, after docking, even ear, not side of system. So, after docking, even ear, not side of system. So, after docking, even
NICNICNICNIC leds on NB side is blinking, users will not see it, leds on NB side is blinking, users will not see it, leds on NB side is blinking, users will not see it, leds on NB side is blinking, users will not see it,
delete Q37 & delete Q37 & delete Q37 & delete Q37 & Q38Q38Q38Q38 0.40.40.40.4
18181818 17,17,17,17, 29292929 LCLCLCLCD & FPD & FPD & FPD & FP 4/84/84/84/8 HPHPHPHP to make sure can turn off theto make sure can turn off theto make sure can turn off theto make sure can turn off the power MOS power MOS power MOS power MOS change the G gate of MOS to +5VS & +5VAchange the G gate of MOS to +5VS & +5VAchange the G gate of MOS to +5VS & +5VAchange the G gate of MOS to +5VS & +5VALWLWLWLW 0.40.40.40.4
19191919
20202020
21212121
NNNNICICICIC
SBSBSBSB710710710710
WebCWebCWebCWebCanananan
4/94/94/94/94/94/94/94/94/4/4/4/11111111
HPHPHPHP HP desigHP desigHP desigHP design change to simplified circuitn change to simplified circuitn change to simplified circuitn change to simplified circuit delete Q1B, Rdelete Q1B, Rdelete Q1B, Rdelete Q1B, R553553553553 0.40.40.40.426262626
20202020 HPHPHPHP HP dHP dHP dHP design CPPE_NC# connectionesign CPPE_NC# connectionesign CPPE_NC# connectionesign CPPE_NC# connection CPPE_N CPPE_N CPPE_N CPPE_NC# connect to U10.C4 (GPIO55)C# connect to U10.C4 (GPIO55)C# connect to U10.C4 (GPIO55)C# connect to U10.C4 (GPIO55) 0.40.40.40.4
17171717 HPHPHPHP in order to support nein order to support nein order to support nein order to support new Webcan w Webcan w Webcan w Webcan delete Q24, C248, R113 & R446, R174.then cdelete Q24, C248, R113 & R446, R174.then cdelete Q24, C248, R113 & R446, R174.then cdelete Q24, C248, R113 & R446, R174.then connect onnect onnect onnect
CARMERA_OCARMERA_OCARMERA_OCARMERA_OFF to MOS G gate.FF to MOS G gate.FF to MOS G gate.FF to MOS G gate.0.40.40.40.4
![Page 52: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/52.jpg)
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Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 0.7
HW Changed-List History-1
52 54Thursday, August 27, 2009
2007/08/02 2009/09/15Compal Electronics, Inc.
Version Change ListVersion Change ListVersion Change ListVersion Change List ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit
ItemItemItemItem Issue DIssue DIssue DIssue DescriptionescriptionescriptionescriptionDateDateDateDateReqReqReqRequestuestuestuest
OwnOwnOwnOwnerererer SoSoSoSolution Descriptionlution Descriptionlution Descriptionlution Description Rev.Rev.Rev.Rev.PaPaPaPage#ge#ge#ge# TTTTitleitleitleitle
21212121 HPHPHPHPSBSBSBSB710710710710 4/4/4/4/13131313 0.40.40.40.4add a 10K pull-down resistor to signal "SLP_S5add a 10K pull-down resistor to signal "SLP_S5add a 10K pull-down resistor to signal "SLP_S5add a 10K pull-down resistor to signal "SLP_S5#"#"#"#" aaaadd R563dd R563dd R563dd R56322222222
23232323 20202020 NNNNICICICIC 4/4/4/4/13131313 HPHPHPHP BOM chaBOM chaBOM chaBOM change nge nge nge chachachachange C712 to 0.022uF (from 0.1uF)nge C712 to 0.022uF (from 0.1uF)nge C712 to 0.022uF (from 0.1uF)nge C712 to 0.022uF (from 0.1uF) 0.40.40.40.4
24242424 33333333 KKKKBCBCBCBC 4/4/4/4/14141414 HPHPHPHP add pull-down resistor to signal "SLP_S5add pull-down resistor to signal "SLP_S5add pull-down resistor to signal "SLP_S5add pull-down resistor to signal "SLP_S5#"#"#"#" change R464 connection from +3VLto change R464 connection from +3VLto change R464 connection from +3VLto change R464 connection from +3VLto GNDGNDGNDGND 0.40.40.40.4
25252525 32323232 4/4/4/4/17171717 HPHPHPHP design changdesign changdesign changdesign change e e e connecconnecconnecconnect pin 2 of Q3A to signal PREP#, dock pin 111t pin 2 of Q3A to signal PREP#, dock pin 111t pin 2 of Q3A to signal PREP#, dock pin 111t pin 2 of Q3A to signal PREP#, dock pin 111 0.40.40.40.4
26262626 36363636
dodododockingckingckingcking
DCDCDCDC-DC-DC-DC-DC 4/4/4/4/19191919 HPHPHPHP to fine turn power to fine turn power to fine turn power to fine turn power on sequenceon sequenceon sequenceon sequence changchangchangchange C553 from 0.01U to 0.047Ue C553 from 0.01U to 0.047Ue C553 from 0.01U to 0.047Ue C553 from 0.01U to 0.047U 0.40.40.40.4
![Page 53: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/53.jpg)
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Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 0.7
HW Changed-List History-1
53 54Thursday, August 27, 2009
2007/08/02 2009/09/15Compal Electronics, Inc.
Version Change ListVersion Change ListVersion Change ListVersion Change List ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit
ItemItemItemItem Issue DIssue DIssue DIssue DescriptionescriptionescriptionescriptionDateDateDateDateReqReqReqRequestuestuestuest
OwnOwnOwnOwnerererer SoSoSoSolution Descriptionlution Descriptionlution Descriptionlution Description Rev.Rev.Rev.Rev.PaPaPaPage#ge#ge#ge# TTTTitleitleitleitle
25252525 HPHPHPHPNNNNICICICIC 5/95/95/95/9 0.50.50.50.5can't power on in AC mode due to PWR_GD can't power on in AC mode due to PWR_GD can't power on in AC mode due to PWR_GD can't power on in AC mode due to PWR_GD bebebebe
dr dr dr drive to lowive to lowive to lowive to low
delete R555, R512. change R499 pin2 from runon delete R555, R512. change R499 pin2 from runon delete R555, R512. change R499 pin2 from runon delete R555, R512. change R499 pin2 from runon to B+. to B+. to B+. to B+.
chchchchange Q79 power source from V1.2_LAN to +1.2VALWange Q79 power source from V1.2_LAN to +1.2VALWange Q79 power source from V1.2_LAN to +1.2VALWange Q79 power source from V1.2_LAN to +1.2VALW
1111
2222 27272727 WWWWWANWANWANWAN 5/5/5/5/29292929 HPHPHPHP ChChChChange WWAN circuit to follow what HP commange WWAN circuit to follow what HP commange WWAN circuit to follow what HP commange WWAN circuit to follow what HP comm
team, & power down WWAN team, & power down WWAN team, & power down WWAN team, & power down WWAN cardcardcardcard
0.50.50.50.5delete R279, R528, Q99 & change Q100 pidelete R279, R528, Q99 & change Q100 pidelete R279, R528, Q99 & change Q100 pidelete R279, R528, Q99 & change Q100 pin5 powern5 powern5 powern5 power
rai rai rai rail from +3VALW to +3VSl from +3VALW to +3VSl from +3VALW to +3VSl from +3VALW to +3VS3333 25252525 NNNNICICICIC 5/5/5/5/29292929 HPHPHPHP to support to support to support to support LAN/WLAN switchLAN/WLAN switchLAN/WLAN switchLAN/WLAN switch add FEadd FEadd FEadd FET Q111T Q111T Q111T Q111 0.50.50.50.5
4444 33333333 KKKKBCBCBCBC 5/5/5/5/29292929 HPHPHPHP add fiadd fiadd fiadd filtering circuit for AD inputltering circuit for AD inputltering circuit for AD inputltering circuit for AD input add add add add C714, C715, C716,R564C714, C715, C716,R564C714, C715, C716,R564C714, C715, C716,R564 0.50.50.50.5
5555 20202020 SBSBSBSB710710710710 5/5/5/5/29292929 HPHPHPHP delete the SATA decoupling cap, Bedelete the SATA decoupling cap, Bedelete the SATA decoupling cap, Bedelete the SATA decoupling cap, Because the capscause the capscause the capscause the caps
are located in docking station side a are located in docking station side a are located in docking station side a are located in docking station side alreadylreadylreadylready
delete C289~C2delete C289~C2delete C289~C2delete C289~C292929292 0.50.50.50.5
6666 36363636 DCDCDCDC-DC-DC-DC-DC 5/5/5/5/29292929 HPHPHPHP DC mode can't power on iDC mode can't power on iDC mode can't power on iDC mode can't power on issuessuessuessue conn conn conn connect R442.1 pin to +3VALW (instead of VL)ect R442.1 pin to +3VALW (instead of VL)ect R442.1 pin to +3VALW (instead of VL)ect R442.1 pin to +3VALW (instead of VL) 0.50.50.50.5
7777 20202020 SBSBSBSB710710710710 5/5/5/5/29292929 HPHPHPHP for for for for AMD vidoe driver requesAMD vidoe driver requesAMD vidoe driver requesAMD vidoe driver reques 0.50.50.50.5connconnconnconnect R175.2 to signal DOCK_ID (instead of GND)ect R175.2 to signal DOCK_ID (instead of GND)ect R175.2 to signal DOCK_ID (instead of GND)ect R175.2 to signal DOCK_ID (instead of GND)
, , , , and make R175 to 100Kand make R175 to 100Kand make R175 to 100Kand make R175 to 100K8888 31313131 card reacard reacard reacard readerderderder 6/46/46/46/4 HPHPHPHP reserve 0 ohm for CRD)REQ#reserve 0 ohm for CRD)REQ#reserve 0 ohm for CRD)REQ#reserve 0 ohm for CRD)REQ# aaaadd R565dd R565dd R565dd R565 0.50.50.50.5
9999 13131313 sideport sideport sideport sideport memorymemorymemorymemory 6/56/56/56/5 AAAAMDMDMDMD AMD SCL suggection:Connected a 100AMD SCL suggection:Connected a 100AMD SCL suggection:Connected a 100AMD SCL suggection:Connected a 100-? 1%-? 1%-? 1%-? 1%
resist resist resist resistor between MEM_CKP and MEM_CKNor between MEM_CKP and MEM_CKNor between MEM_CKP and MEM_CKNor between MEM_CKP and MEM_CKN
(not installed by def (not installed by def (not installed by def (not installed by default).ault).ault).ault).
un-installun-installun-installun-install R68 R68 R68 R68 0.50.50.50.5
10101010 31313131 card reacard reacard reacard readerderderder 6/86/86/86/8 HPHPHPHP sosososome 1394 not detectedme 1394 not detectedme 1394 not detectedme 1394 not detected adadadadd Q23, R566d Q23, R566d Q23, R566d Q23, R566 0.50.50.50.5
11111111 25252525 NNNNICICICIC 6/86/86/86/8 CCCCompalompalompalompal combine Q111 & Q97 as dual FET Q19 combine Q111 & Q97 as dual FET Q19 combine Q111 & Q97 as dual FET Q19 combine Q111 & Q97 as dual FET Q19 0.50.50.50.5
12121212 31313131 card reacard reacard reacard readerderderder 6/96/96/96/9 HPHPHPHP the power down feature for BIOS (The idthe power down feature for BIOS (The idthe power down feature for BIOS (The idthe power down feature for BIOS (The idea is ea is ea is ea is
to have BIOS SIO GPIO control, if that GPIO is to have BIOS SIO GPIO control, if that GPIO is to have BIOS SIO GPIO control, if that GPIO is to have BIOS SIO GPIO control, if that GPIO is
high, thhigh, thhigh, thhigh, the circuit is enabled. If the GPIO is GPI ore circuit is enabled. If the GPIO is GPI ore circuit is enabled. If the GPIO is GPI ore circuit is enabled. If the GPIO is GPI or
low, the power-down circuit then disa low, the power-down circuit then disa low, the power-down circuit then disa low, the power-down circuit then disabled.)bled.)bled.)bled.)
add add add add R565, R567, C717,C718R565, R567, C717,C718R565, R567, C717,C718R565, R567, C717,C718 0.50.50.50.5
13131313 18181818 DPDPDPDP 6/6/6/6/11111111 AAAAMDMDMDMD AMD require a blank time on HPD signaAMD require a blank time on HPD signaAMD require a blank time on HPD signaAMD require a blank time on HPD signal when l when l when l when
docking station and NB both have DP. The change docking station and NB both have DP. The change docking station and NB both have DP. The change docking station and NB both have DP. The change
basically will block DPB HPD for a 10basically will block DPB HPD for a 10basically will block DPB HPD for a 10basically will block DPB HPD for a 100ms becuase0ms becuase0ms becuase0ms becuase
p p p pass throughass throughass throughass through
0.50.50.50.5delete R124, R514 add Q113,R568,R569,C7delete R124, R514 add Q113,R568,R569,C7delete R124, R514 add Q113,R568,R569,C7delete R124, R514 add Q113,R568,R569,C719191919
14141414 27272727 WWWWWANWANWANWAN 6/6/6/6/11111111 CCCCompalompalompalompal
in order to improve the placemein order to improve the placemein order to improve the placemein order to improve the placementntntnt
MC1_DISABL is open drain seeting need pull high, MC1_DISABL is open drain seeting need pull high, MC1_DISABL is open drain seeting need pull high, MC1_DISABL is open drain seeting need pull high,
and +3V_WWAN need discharge circuand +3V_WWAN need discharge circuand +3V_WWAN need discharge circuand +3V_WWAN need discharge circuitititit
adadadaddR570, R571, Q114dR570, R571, Q114dR570, R571, Q114dR570, R571, Q114 0.50.50.50.5
15151515 8888 DDDDDRDRDRDR 6/6/6/6/11111111 CCCCompalompalompalompal EEEEMI request 0.1UF cap for +1.8VMI request 0.1UF cap for +1.8VMI request 0.1UF cap for +1.8VMI request 0.1UF cap for +1.8V addaddaddadd C720, C721 C720, C721 C720, C721 C720, C72116161616 6666 CCCCPUPUPUPU 6/6/6/6/12121212 HPHPHPHP HP request add 1k resistor between Q10.2 and LDT_RHP request add 1k resistor between Q10.2 and LDT_RHP request add 1k resistor between Q10.2 and LDT_RHP request add 1k resistor between Q10.2 and LDT_RST#.ST#.ST#.ST#. aaaadd R572dd R572dd R572dd R572
0.50.50.50.5
0.50.50.50.5
17171717 17171717 webwebwebwebcamcamcamcam 6/6/6/6/13131313 CCCCompalompalompalompal EMI request add com-choke forEMI request add com-choke forEMI request add com-choke forEMI request add com-choke for webcam webcam webcam webcam addaddaddadd L49 L49 L49 L49 0.50.50.50.5
0.50.50.50.518181818 31313131 WWWWWANWANWANWAN 6/6/6/6/13131313 HPHPHPHP WWAN LED abnormal when poWWAN LED abnormal when poWWAN LED abnormal when poWWAN LED abnormal when power downwer downwer downwer down chajnge Q53 pin2 power rail from +3VS to +3V_WWchajnge Q53 pin2 power rail from +3VS to +3V_WWchajnge Q53 pin2 power rail from +3VS to +3V_WWchajnge Q53 pin2 power rail from +3VS to +3V_WWANANANAN
![Page 54: LA-4961P TAG UMA Rev: 1 - ldasystem.com 1.0 Block Diagram Custom Thursday, August 27, ... 2MB Docking CONN. (1) ... 10K_0402_5% 1 2 C4 0.22U_0603_16V4Z 1 2 U2](https://reader035.vdocument.in/reader035/viewer/2022062908/5ac6e2937f8b9a5d718b4dfc/html5/thumbnails/54.jpg)
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Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4961P 0.7
HW Changed-List History-1
54 54Thursday, August 27, 2009
2007/08/02 2009/09/15Compal Electronics, Inc.
Version Change ListVersion Change ListVersion Change ListVersion Change List ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit ( P. I. R. List ) for HW Circuit
ItemItemItemItem Issue DIssue DIssue DIssue DescriptionescriptionescriptionescriptionDateDateDateDateReqReqReqRequestuestuestuest
OwnOwnOwnOwnerererer SoSoSoSolution Descriptionlution Descriptionlution Descriptionlution Description Rev.Rev.Rev.Rev.PaPaPaPage#ge#ge#ge# TTTTitleitleitleitle
30303030 CCCCompalompalompalompalUSBUSBUSBUSB 6/6/6/6/20202020 0.60.60.60.6change C485, C491,C690 footprint for 2nd souchange C485, C491,C690 footprint for 2nd souchange C485, C491,C690 footprint for 2nd souchange C485, C491,C690 footprint for 2nd sourcercercerce1111 change foochange foochange foochange footprint from C_D to C_D2Etprint from C_D to C_D2Etprint from C_D to C_D2Etprint from C_D to C_D2E2222 21, 2821, 2821, 2821, 28 SMSMSMSMSC CBBSC CBBSC CBBSC CBB 7/47/47/47/4 HPHPHPHP for SMfor SMfor SMfor SMsC CBB utilized the Lid#.sC CBB utilized the Lid#.sC CBB utilized the Lid#.sC CBB utilized the Lid#. move Q110 close to SB710 and pull high LIDmove Q110 close to SB710 and pull high LIDmove Q110 close to SB710 and pull high LIDmove Q110 close to SB710 and pull high LID_SW#_SW#_SW#_SW# 0.60.60.60.6
1111 31313131 card reacard reacard reacard reader der der der 8/8/8/8/13131313 HPHPHPHP card reader can't detect & rcard reader can't detect & rcard reader can't detect & rcard reader can't detect & reduce power consumptioneduce power consumptioneduce power consumptioneduce power consumption remove C718 and change R558 to 47K oremove C718 and change R558 to 47K oremove C718 and change R558 to 47K oremove C718 and change R558 to 47K ohmhmhmhm 1.01.01.01.0
2222 HPHPHPHP8/8/8/8/24242424AudAudAudAud ioioioio33333333 1.01.01.01.0adadadadd Q115, R575,Q116d Q115, R575,Q116d Q115, R575,Q116d Q115, R575,Q116there is the po-po sound when warm bothere is the po-po sound when warm bothere is the po-po sound when warm bothere is the po-po sound when warm bootototot