lab 4: digital ic design flow - université...

GIF-4201/GEL-7016 (Micro-électronique)

Lab 4: Digital IC Design Flow

Synthesis, Verification, Layout

Mehdi Noormohammadi Khiarak, Gabriel Gagnon-Turcotte, and

Benoit Gosselin

Department of Electrical & Computer Engineering

Laval University, Quebec City, Canada

March 2018

2

Version history

Version Description Authors Date

1 Original revision

M. Noormohammadi

Khiarak ,G. Gagnon-

Turcotte, and Benoit

Gosselin

March. 20

2018

3

1. Introduction 4

2. Design Synthesis and Verification 4

2.1. Functional Verification of HDL code 4

2.2. Synthesising your HDL Code 4

2.3. Functional verification on Gate-Level Netlist 6

3. Placement, Routing, and Optimization 8

3.1. Importing the Design 10

3.2. Preparing the Floorplan 12

3.3. Inserting Core Power Ring and Stripes 13

3.4. Initial Placement and Trial Route for Timing Verification 15

3.5. Clock Tree Insertion 16

3.6. Routing the Power Nets 18

3.7. Filler Cells 20

3.8. Routing and Timing Verifications 21

4. EXPORT GDS file (this step is optional) 22

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1. Introduction This lab was written to guide you through a CMOS digital design flow process. The main

purpose of this lab is to start from your VHDL source files that has been written in Lab 3

(i.e., it can be your own project files) and generate a gate level file and a complete chip

layout. In this lab, the following tools and technologies will be required:

- Synopsys

- Modelsim

- Encounter

- TSMC: CMOSP18 Artisan library

In this lab, you will use design files and scripts that were created by CMC microsystem

group for a digital design flow in 0.18µm CMOS process. You will have to copy these

design files, including the VHDL code and its testbench, in your personal account, so

they can be accessed by the tools throughout the lab.

Please note that this tutorial is based on CMC tutorial for digital flow design in tsmc

180nm process [1].

2. Design Synthesis and Verification In this section, you will build your gate level design using a hardware description

language (HDL) code, and then verify its functionality before and after each important

steps of the synthesis process to ensure the functionality has not altered.

2.1. Functional Verification of HDL code

It is assumed that you are familiar with VHDL code compiling and verification which

steps were covered in Lab 3. In Lab 3, you familiarized with ISim and Modelsim tools

and verified your VHDL code. Don’t hesitate to test your HDL code again before starting

this new lab in order to make sure it has not been altered.

** Note that in the gate level simulation, it is necessary to add an enable signal “en” to

your VHDL code, as follow. This signal is mandatory for every process in your VHDL

design.

“If rising_edge(clk) and en=’1’ then”

This is because the synthesized flip-flops in these CMOS library has such an enable

signal. Hence, without “en” your gate level netlist will not work correctly.

Since you will need Modelsim in the following section, it is suggested that you start by

compiling and verifying your code using this software in order to familiarize yourself

with it.

2.2. Synthesising your HDL Code

In this step, you will create the gate-level netlist of your design using the Synopsys

synthesizer. To perform the synthesis, a script has already been prepared to expedite the

process. You can copy the file in your account with the following commands:

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Log on cmc-node-1, and type:

cd

cp /CMC/kits/artisan/tut_artisan.zip

unzip tut_artisan.zip

Before starting the synthesis, you should perform the following task to modify the script

in the provided file.

a) Navigate to the directory” …\tut_artisan\synopsys_analyzer\cmds”

b) Open the script “ALU_build.script” and replace it with your own HDL design

architecture and entity names all over the script.

c) Make sure “.synopsys_dc.setup” script is located in

“…\tut_artisan\synopsys_vision”.

d) Save and exit.

Design Analyzer from Synopsys is used to generate the synthesis gate level code. The

gate level netlist can be built by executing the above-mentioned script. Hence, open a

terminal window and navigate to the directory “…\tut_artisan\synopsys_analyzer” and

then execute the following commands:

tcsh

source /CMC/scripts/cadence.edi10.13.003.csh

source /CMC/scripts/cadence.incisiv12.10.001.csh

source /CMC/scripts/kit.tsmc180nm.5.2.csh

source /CMC/scripts/mentor.calibre.2016.4_27.18.csh

source /CMC/scripts/synopsys.syn.2016.03-SP4-1.csh

design_vision &

The Design Analyzer window is displayed as shown in Figure 1. Perform the following

steps (the following procedure was copied from [1]):

a) Select Setup->Command Window... from the Design Analyzer window. The

Command window is displayed. The results of the script will be displayed in this

window. You are encouraged to open the script in the next task to understand a

little better the commands being executed.

b) Select Setup->Execute Script... from the Design Analyzer window.

The Execute File window is displayed.

c) Navigate to the cmds directory and select ALU_build.script (i.e., in this case it

would be your file name) in the File Name field.

d) Click OK in the Execute File window. The script takes a while to execute. At the

end of this script, the files alu_gate.v and alu_gate.vhd are created. These are the

gate-level netlists we are looking for.

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e) Exit Design Analyzer

Fig.1. Design Analyzer Window [1].

2.3. Functional verification on Gate-Level Netlist

In this section, you will check the gate-level netlist to figure out whether it meets the

functional verification of your design. For this task, Modelsim will be used. Open the

gate level netlist (i.e the VHDL file generated by Synopsis and located in

“…\tut_artisan\synopsys_analyzer”) and change the first lines of the commands in

VHDL accordingly as follows:

(please just make sure that you have replaced ALU_build with your design name)

library IEEE;

use IEEE.std_logic_1164.all;

package CONV_PACK_ ALU_build is

attribute ENUM_ENCODING : STRING;

end CONV_PACK_ ALU_build;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_ ALU_build.all;

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entity ALU_build is

Run Modelsim using the following command in the terminal or opening directly from

your computer if it has already been installed on your machine.

source /CMC/scripts/mentor.modelsim.10.3.csh

vsim

In the library tap as shown in the following figure, right click and add “tsmc18vhd” to the

library from “/CMC/kits/artisan/FE/aci/sc/vhdl/tsmc18vhd”.

Add three Verilog files namely, tsmc18, tsmc18_clean, tsmc18_neg to the project by

navigating to the directory

“…\Artisan_dev_INCISIV12.10.001\artisan18.3.0\FE\aci\sc\verilog”

The files are displayed in Fig. 2 for an arbitrary project (LIA_FSM). Then compile those

files to add the required libraries to the work directory. To compile the files go to

“Compile compile all”

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Fig.2. Verilog files added in Modelsim.

To run the simulation, go to “simulate start simulation …” the following window will

pop up. Make sure that enable optimization is deselected. Set the resolution to ps and

select your entity from the library work as shown in the following figure.

3. Placement, Routing, and Optimization This section relates to the physical portion of the design flow. The Cadence tool,

Encounter, will be used to create the floorplan and perform the physical layout of the

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design. Encounter will be executed from the SOC directory. Three files are provided in

the SOC/inputs directory (…\tut_artisan\SOC) as follows:

a) alu_clk.ctstch: File to used during the clock tree insertion. It provides the

necessary specifications to build the clock tree for your circuit;

b) alu.conf: Contains the necessary links to import the design (libraries, placement,

etc); and

c) alu_placement.io: Placement file for the tutorial. It has all the inputs placed in

their proper location: put name of the input output pins that is created after

synthesis. In the following example, north, west, east, and west refer to location of

the pins in the layout. In this example, the entity of your design has 5 signal pads

including rst, en, clk, A, and B. A and B are two bit signal bus.

# North

######################################################

Pin: rst N

######################################################

# East

#######################################################

Pin: en E

Pin: clk E

######################################################

# South

Pin: A[0] S

Pin: A[1] S

######################################################

# West

Pin: B[0] W

Pin: B[1] W

#####################################################

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In those files which are located in “…\tut_artisan\SOC\Inputs”, you must replace the

design names with your design names. Then execute the following commands in the

terminal window:

tcsh

source /CMC/scripts/cadence.edi10.13.003.csh

encounter

* Do not put “&” in front of Encounter command.

3.1. Importing the Design

In this section, the synthesized VHDL file generated by Synopsys will be taken and

imported into Encounter. The design import form comprises many features.

a) LEF Files: In the Technology Information/Physical Libraries section, the user points

the import tool to the technology library. For this tutorial, we only use the LEF files from

the Artisan technology from TSMC. In the script, the names should be modified to match

with your design names. The files from the Artisan kit are:

i. /CMC/kits/artisan/FE/aci/sc/lef/tsmc18_6lm.lef (standard cell definitions),

ii. /CMC/kits/artisan/FE/aci/sc/lef/tsmc18_6lm_antenna.lef (standard cell antenna

definitions),

iii.

/CMC/kits/artisan/FE/fe_TSMCHOME_tpz973g_240c/digital/Back_End/lef/tpz9

73g_240a/6lm/lef/tpz973g_6lm.lef (I/O PAD definitions), and

iv.

/CMC/kits/artisan/FE/fe_TSMCHOME_tpz973g_240c/digital/Back_End/lef/tpz9

73g_240a/6lm/lef/antenna_6.lef (I/O PAD antenna definitions).

b) Timing Libraries: In the Timing Information section, the user points the import tool

to the timing information for the technology. The files from the CMOSP18 kit are:

i.

/CMC/kits/artisan/FE/fe_TSMCHOME_tpz973g_240c/digital/Front_End/timing_

power/tpz973g_240c/tpz973gwc.tlf

(PAD worst case timings), and

ii. /CMC/kits/artisan/FE/aci/sc/tlf/slow.tlf (standard cells worst case timings);

c) Timing Constraint File: Under the timing tab, in the timing Information section, the

user points the import tool to the timing information for the design. The constraint file for

the tutorial design is:

i. ../synopsys/alu.sdc;

d) Component Name or Footprint: In the Timing Information section, the user needs

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to identify certain components for delay, buffering and inverting. For this tutorial, these

inputs are:

i. Buffer name/Footprint: BUFX2,

ii. Delay name/Footprint: BUFX1, and

iii. Inverter name/Footprint: INVX2; and

e) IO Assignment File: In the IO Information section, the user points the tool to a file

that contains the required details for the placement of the I/Os around the core. You

should change the file according to your input/output pins, as stated in Section 3.c.

i. Inputs/alu_placement.io

To instantiate the import form, execute the following steps (the following procedure was

copied from [1]):

Form: Select Design -> Design Import... in the Encounter Main Window.

The Design Import form is displayed.

Form: Click on the Load... button in the Design Import window.

The Load Import Configuration window is displayed.

Form: Navigate to the Inputs directory.

Form: Click on the file alu.conf to select it.

It should now be highlighted.

Form: Click on the Open button in the Load Import Configuration window.

The Design Import window should now be loaded with the required information

to import your design.

Form: Click on the OK button in the Design Import window. Depending on the

design size, it may take a few minutes to load the design. You should now see the

design loaded in the Display Area like as shown in Fig.3.

There are three distinct area in the imported design:

- Core: This is the black area with white (or gray) line in the middle. This is

where the standard cells will be placed;

- IO Ring: Area where your design I/Os have been placed based on the placement

file provided; and

- Cell listing: At the beginning, the list of standard cells is place in the area to the

left of the chip (shown in pink on your screen).

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Fig.3. Imported Tutorial Design [1].

3.2. Preparing the Floorplan

At this time, you will initialize your design floorplan by determining the shape and size

of the core area where the logic cells will be placed. You should leave enough room for

the power and ring around the core if you using those items. Use the following command

to initialize the floorplan (the following procedure was copied from [1]):

Form: Select Floorplan -> Specify Floorplan... in the Encounter Main Window.

The Specify Floorplan window is displayed (shown in Fig.4).

Form: In the Specify Floorplan window, set the following fields:

Ratio (H/W): 0.4 (indicating the ratio of the length to width of the layout, it could

be square and rectangle depends on the ratio)

Core Utilization: 1 (number of core in the design)

Core to Left: 70 (the space between the core and the left of the layout edge in µm)

Core to Right: 70 (the space between the core and the right part of the layout edge

in µm)

Core to Top: 150 (the space between the core and the top of the layout edge in

µm)

Core to Bottom: 150 (the space between the core and the bottom of the layout

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edge in µm)

Leave the remaining field as is.

Form: Click the OK button in the Specify Floorplan Window.

The core area can be reshaped to fit on the design size for instance, it can be a rectangle

with a long side on the top and bottom. This step can be done with trial and error to target

the best possible result. If the initialization of the floorplan is successful, save the design

again as “initialized.enc”.

Fig.4. Specify Floorplan Form [1].

3.3. Inserting Core Power Ring and Stripes

In this step, we will prepare the power distribution to the core area. This is carried out by

building a power ring around the core area and adding stripes through the core extending

the ring. The ring will be connected to the power core pads which is supplied by an

external power supply.

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Core Power Ring

The core power ring is composed of actually two rings: VDD and VSS rings. In order to

add a core power ring to the tutorial design, perform the following tasks (the following

procedure was copied from [1]):

Form: Select Power->Power Planning->Add Rings... in the Encounter Main

Window

The Add rings form is displayed. If the other forms were filled out properly, the

defaults values here should be fine except for sizes. The width and spacing will be

adjusted higher for better power distribution.

Form: Change the following inputs:

Ensure the Top and Bottom Layers are: Metal5 H

Ensure Left and Right Layers are: Metal6 V

Change the Top, Bottom, Left and Right Widths: 0.88

Change the Top, Bottom, Left and Right Spacings: 1.38

Change the Top, Bottom, Left and Right Offset: 1.32

Leave all other fields as default

Form: Click Ok.

You should now see the VSS and VDD power rings around the core area.

Core Power Stripes

When the design is big, only one metal for the power distribution would not be enough

and there would be a significant voltage drop across the path. Hence, stripes can be used

to increase the power distribution all over the chip layout. Stripes are metal lines that will

connect the power ring from the top metal wires to the bottom metal wires vertically with

equal spacing between the lines. We started with adding a pair of stripes (VDD and VSS)

for every 100 µm of core (in width). We will add one pair of power stripes in the middle

of the core. To add the stripes to the core, perform the following tasks (the following

procedure was copied from [1]):

Form: Select Power->Power Planning->Add Stripes... in the Encounter Main

Window.

The Add Stripes window is displayed.


Ensure Layer is: Metal 6

Width: 0.88

Spacing: 1.38

Click on Number of Sets and enter 3

Click on Relative from core or area

X from left: 36

Y from left: 36

Leave all other fields as default

Form: Click Ok

You should now see the VSS and VDD power stripes added over the core area.

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Your core area should now look like the one shown in Fig.5.

Form: If adding the power rings and stripes is successful, save the design again as

“powered.enc”.

Fig.5 Core Area with Power Rings and Stripes [1].

3.4. Initial Placement and Trial Route for Timing Verification

At this time, we will place the cells into the core area that already existed by the floor

planning. In this step, each cell in the netlist will be mapped in the core area. The timing

requirement will be considered to meet the system clock specs.

Initial Placement

To perform the initial placement, execute the following tasks (the following procedure

was copied from [1]):

Form: Select Timing->Report->Clock Waveform... in the Encounter Main Window.

The Clock Summary Info window should be displayed.

Form: Click Ok in the Clock Summary Info window

This task will identify if you have a clock present in your design. Inspect the terminal

window where the Encounter tool was started from and look for a clock report. It will

contain the period and clock source identification.

Form: Select Place-> Standard Cells and Blocks... in the Encounter Main Window

The Place window should be displayed.

Deselect Reorder Scan Connection.

Form: Click Ok in the Place window

This task may take a few minutes when designs are large.

Form: Select Place-> Check Placement... in the Encounter Main Window

The Check Placement window should be displayed.

Form: Click Ok in the Check Placement window

The placed cells are now shown in the core area as shown in Fig. 6 (placement may

differ for each user).

Form: If the placement is successful, save the design again as “placed.enc”.

After cells placement run the following command in the console:

globalNetConnect VDD -pin VDD -inst * -type pgpin -all -override

globalNetConnect VSS -pin VSS -inst * -type pgpin -all –override

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Optimization: After the placement run the following command in the console:

optDesign –preCTS

Fig.6. Placed Design [1].

Trial Route for Timing Verification

Now it is the time to make an initial timing verification before further proceeding to

figure out if your timing constraints are met. Otherwise, you should come back and do

some modification in synthesis, floor planning, etc to fix the issue. To perform the trial

route and timing verifications, perform the following tasks (the following procedure was

copied from [1]):

Form: Select Route->Trial Route... in the Encounter Main Window

The Trial Route window is displayed. The defaults values are OK for trial route.

Form: Click Ok in the Trial Route Window Zoom in to observe the routing nets.

Form: Select Timing->Extract RC... in the Encounter Main Window

The Extract RC window is displayed. Deselect Save Cap to and leave the other

fields as default.

Form: Click OK in the Extract RC window.

Form: Click Timing->Timing Analysis in the Encounter Main Window

The Timing Analysis window is displayed. Leave the defaults values in the form.

Form: Click OK in the Timing Analysis window

Timing reports are stored in directory SOC/timingReports. In particular, you can

browse the directory for “.slk” file. These files contain the slack timings. For this

analysis, look for the alu_chip_preCTS.slk. Any negative slack indicates that the

design does not meet the specifications.

3.5. Clock Tree Insertion

Clock tree is a method of providing a clock distribution all over the chip so as to reduce

the clock skew and avoiding the synchronisation issues. These tools will insert a balance

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tree in your design in order to get a perfectly synchronized clock throughout your circuit.

Building the clock tree requires a library including the buffers and drivers. To insert the

clock tree, perform the following tasks (the following procedure was copied from [1]):

Form: From the Encounter prompt, enter specifyClockTree -template

This will create a template file, template.ctstch in the directory tut_artisan/SOC, for your

clock tree insertion. The user needs to modify this file to meet its needs. The clock tree

specifications have been provided for this tutorial in file “Inputs/alu_clk.ctstch“. The

user is encouraged to compared the template file against this file to familiarize himself

with the clock tree specifications. The following procedure was copied from [1].

Form: Select Clock->Specify Clock Tree... in the Encounter Main Window

The Specify Clock Tree window is displayed. Click the folder navigation button

and navigate to the file “Inputs/alu_clk.ctstch“.

Form: Click Open in the Clock Tree File window

Form: Click OK in the Specify Clock Tree window

The clock tree specifications are loaded in Encounter.

Form: Select Clock->Synthesize Clock Tree... in the Encounter Main Window

The Synthesize Clock Tree window is displayed.


Click on Set Added Clock Buffers as Fixed

Leave all other fields as defaults

Form: Click OK in the Synthesize Clock Tree window

The previous trial route information is cleared.

Form: Select Clock->Display->Display Clock Tree... from the Encounter

window.

The Display Clock Tree window is displayed.



Form: Click OK in the Display Clock Tree window.

Form: Again, select Clock->Display->Display Clock Tree... from the Encounter

window.

The Display Clock Tree window is displayed.


Click on Display Clock Tree

Click on All Level


Form: Click OK in the Display Clock Tree window.

The clock tree is displayed using colors for the added buffers for the clock tree

components. Each color indicate a different level for the tree distribution. In

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addition to the color, a visual connection line (yellow) is displayed to show how

the clock is distributed. The user can browse the clock tree using the Clock-

>Clock Tree Browser... command. It is left to the user to explore this feature.

Form: If the clock tree insertion is successful, save the design again as

“clocked.enc”.

3.6. Routing the Power Nets

The power core pads including VSS and VDD are connected to the power ring by routing

the power nets (in this lab you will not deal with the pad, will have only pins in your

design). To route the power nets, perform the following tasks (the following procedure


Form: Select Route->Special Route... in the Encounter Main Window

The SRoute window is displayed. Leave the fields of the form as defaults.

Form: Click OK in the SRoute window

The power nets to the pads should now be visible. In addition, the cell row VDD’s

and VSS’s have been extended to their respective rings. There are connected

using via arrays. Fig.7 shows the power routing completed.

Form: If the power routing is successful, save the design again as “srouted.enc”.

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Fig.7. Power Routing Completed [1].

Timing Driven Routing

One of the last task is to route the remaining nets using the NanoRoute tool. To

route the design, execute the following tasks (the following procedure was copied from

[1]):

Form: Select Route->NanoRoute->Route... in the

Encounter Main Window

The NanoRoute window is displayed.


In Concurrent Routing Features Area, select Timing Driven,


Form: Click OK in the NanoRoute window

If you got an error you can see it in the console. The successful routing, reflect no

violations in the console. To see the routing, you can zoom in the core area as shown in

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Fig.8 as an example. Form: Once the time driven routing is completed, save the design

again as “nrouted.enc”.

Fig.8. Small Routed View [1].

3.7. Filler Cells

As seen from Fig.8, between the two cells there is a gap. This gap can be filled with filler

cells. Fillers cells are used to fill the gaps between the std cells and to make the metal

density uniform from the fab point of view. Execute the following tasks to insert filler

cells (the following procedure was copied from [1]):

Form: Select Place->Filler->Add... in the

Encounter Main Window.

The Add Filler window is displayed.

Form: Click on the Select button.

The Select Filler Cells window is displayed.

Form: Select all cells in the Cells List area (use the ctl or shift keys for multiple

selects)

and click the Add button in the Select Filler Cells window.

Form: Click Close in the Select Filler Cells window.

You should be back in the Add Filler window is displayed. You should see the list of

filler cells in the Cell Name(s) field.

Form: Enter FILLER in the Prefix field of the Add Filler window and ensure that

Fill Boundary is selected.

Form: Click OK in the Add Filler window.

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To see the added filler cells, you need to zoom in the core area.

Form: Once the add filler task is completed, save the design again as “filled.enc”. The sample

completed layout is shown in Fig.9.

3.8.Routing and Timing Verifications

The final step is the verifications to make sure the design can be fabricated. you need to

perform a couple of verifications on the design:

a. Routing: verification that ensures the design is properly

connected (as designed); and

b. Timing: verification to verify the design layout is meeting the

timing constraints set for this design.

Routing Verifications

you need to carry out a high level verification to find out the connectivity that has been

completed, and make sure there are no error. This task can be done with two commands:

Verify Connectivity and Verify Geometry.

Verify Connectivity

in this step, you will check the final connectivity test to see the routing is completed. To

perform this test, carry out the following tasks (the following procedure was copied from

[1]):

Form: Select Verify->Connectivity... in the Encounter Main Window

The Verify Connectivity window is displayed. Leave all the fields as default.

Form: Click OK in the Verify Connectivity window.

In the Encounter terminal window, a message indicating that no violations were

detected should be displayed.

Verify Geometry

This verification looks like a DRC in cadence. The goal is to check the final geometry

test to determine your routing meets the layout rules. To perform this test, perform the

following tasks (the following procedure was copied from [1]):

Form: Select Verify->Geometry... in the Encounter Main Window

The Verify Geometry window is displayed.


In Check Area, select Geometry Antenna,


Form: Click OK in the Verify Geometry window.

In the Encounter terminal window, a message indicating that no violations were detected

should be displayed.

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Verify Process Antenna

Antenna errors happen in the design when the area of a metal in a path exceed a certain

value. To verify that the routing meets the antenna rules perform the following tasks (the

following procedure was copied from [1]):

Form: Select Verify->Process Antenna... in the Encounter Main Window

The Verify Process Antenna window is displayed.


Leave all fields as defaults

Form: Click OK in the Verify Process Antenna window.

In the Encounter terminal window, a message indicating that no violations were detected

should be displayed.

Fig.9. Completed layout.

4. EXPORT GDS file (this step is optional)

Gds file is the file containing the layout information and normally used by the fabrication

manufactures to implement your layout based on the file. In this design, you can export

the gds file and then import it in the cadence spectre to integrate within your analog

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design. To export your GDS file, perform the following tasks (the following procedure


Go to Design->Save->GDS...

Fill out the form as follow which is show in Fig.10:

Output Stream File: Lab4.gds

The name of the GDS file you wish to save.

Map File: vtvt_SoCE2df2.map

This map file is used to map layer from SOC Encounter into df2.

Fig.10. GDS export.

References:

[1] Tutorial on CMC’s Digital IC Design Flow, Canadian Microelectronics Corporation,

A Tutorial on RMC’s Digital Design Flow (based on CMOSP18 Artisan), 2007.

lab 4: digital ic design flow - université...

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