Islamic University

EE-261Digital Logic Design

Functional Block: Half-Adder

• A 2-input, 1-bit width binary adder that performs the following

computations:

• The sum is expressed as a sum

bit , S and a carry bit, C

• The half adder can be specified as a

truth table for S and C

X 0 0 1 1

+ Y + 0 + 1 + 0 + 1

C S 0 0 0 1 0 1 1 0

X Y C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

Logic Diagram-Half adder

Full adder

• A full adder is combinational circuit that forms the

arithmetic sum of three input bits. It consists of three

inputs and two outputs.

• Two of the input variable represented by x and y. The third

input Z represent s the carry from previous lower

significant position.

Full adder

Logic Diagram-Full adder

Half Subtractor

Subtracting a single-bit binary value Y from anther X (I.e. X -Y ) produces a

difference bit D and a borrow out bit B-out.

X Y B D

• 0 0 0 0

• 0 1 1 1

• 1 0 0 1

• 1 1 0 0

o D(X,Y) = S (1,2)

o D = X’Y + XY’

o D = X Å Y

o B= S (1)

o B = X’Y

Logic Diagram-Half Subtractor

• The circuit has three inputs and two outputs. The three

inputs X, Y, Z denote the minuend, subtrahend, and

previous borrow respectively. The two outputs D and B

represent the difference and output borrow, respectively.

• Easy way to write the truth table

B=1 if (X<Y+Z)

D=X-Y-Z (Don’t bother about sign),If B=0

D=(2+X)-Y-Z, If B=1

Full Subtractor

X00001111

Y00110011

D01101001

B 0 1 1 1 0 0 0 1

Z 0 1 0 1 0 1 0 1

Inputs Outputs

D = X’Y’Z + X’YZ’ + XY’Z’ + XYZ

B = X’Z + X’Y + YZ