lab: initial setupweng/courses/ic_2007/... · 2020. 4. 23. · c. m. huang / cic-cbdc / 01.2004 lab...

C. M. Huang / CIC-CBDC / 01.2004 Lab 0-1

Lab: Initial Setup 1. Create the symbolic link to the lab source directory:

cd ~ ln –s /cad2/lab/CBDC/0401 CBDC

2. Create the lab working directory: mkdir CBDC_LAB

3. Copy the lab initial file into your home directory: cp ~/CBDC/BIN/.cshrc ~

4. Source the new initial file to make it effectively: source ~/.cshrc


Lab: Using the 0.18um Standard Cell Library

Accessing the Databooks

1. Open the first cell library databook: acroread ~/CBDC/LIB/CIC/doc/umc18.pdf & What is the title of this databook? What is the target process for the cells described in this databook? How many Layers of Metal are used in this cell library? What is the Layout Grid for this cell library? What is the Vertical Pin Grid for this cell library? What is the Horizontal Pin Grid for this cell library? What are the Cell Power and Ground Rail Width for this cell library? What are the maximum and minimum DC Supply Voltage values for this cell library? What is the definition of Propagation Delay used for this cell library? What are the Height and Width of INVX1 and INVX8? What are the Pin Capacitance for input pin A of INVX1 and INVX8? What are the Intrinsic Delay for output pin Y rising of INVX1 and INVX8? What are the Load Multiplier (Kload) for output pin Y rising of INVX1 and INVX8?


2. Open the second cell library databook:

acroread ~/CBDC/LIB/CIC/doc/umc18io3v5v.pdf & What is the title of this databook? What are the maximum and minimum Core DC Supply Voltage values for this cell library? What are the maximum and minimum Ring DC Supply Voltage values for this cell library? What is the cell PCORNER used for? What is the cell PFILL used for?

3. Open the third cell library databook: acroread ~/CBDC/LIB/CIC/doc/ra1sh_1.pdf & What is the title of this databook? What types of output view can be generated by this memory generator?


Accessing the Synthesis Models

4. Change into the source file directory of the synthesis models: cd ~/CBDC/LIB/orig_lib/aci/sc-x/synopsys How many source files (*.lib) there? Please record the file name and size below. ls -alF How many source binary (*.db) there? Please record the file name and size below. Take a look at the file: typical.lib What are the operation conditions (process, temperature, and voltage) for this model? What is the area cost of INVX1? What is the capacitance for pin A of INVX1? What is the function for pin Y of INVX1? Take a look at the power and delay calculation table for INVX1.

Accessing the Simulation Models

5. Take a look at the Verilog simulation model file for core cells: ~/CBDC/LIB/CIC/Verilog/umc18.v Find the simulation model for INVX1 and record it here:


Accessing the Physical Design Models

6. Take a look at the LEF physical design model file for core cells: ~/CBDC/LIB/orig_lib/aci/sc-x/lef/umc18_5lm.lef Find the definitions for INVX1. What is the Class of INVX1? What is the Size (Area) of INVX1?

Accessing the Memory Generator

7. Follow the directions in the High-Speed Single-Port SRAM Generator User Manual to generate some memory models (e.g. PostScript Datasheet, ASCII Datatable, Verilog Model, Synopsys Model, VCLEF Footprint). cd ~/CBDC_LAB mkdir 01 cd 01 ra1sh &


Lab: Using the nLint HDL Design Rule Checker 1. Create the lab directory:

mkdir ~/CBDC_LAB/02

2. Change the working directory to the lab directory: cd ~/CBDC_LAB/02

3. Copy the example Verilog design files to your lab directory: cp ~/CBDC/LAB/02/* .

4. Take a look at those two source file: rgb2ycrcb.v testbench.v

5. Invoke the nLint by using the following command: nLint –gui & The main frame will be shown on the screen:


6. Specify the design files. Select the File > Import Design… menu item in the main frame,

after the Import Design dialog box pops up, click on the From File tab, add rgb2ycrcb.v and testbench.v to the Design Files field and click on the OK button. These two files will be listed in the project window, notice that the first file in automatically shown in the integrated editor window.

7. Edit more then one file at the same time. When you double-click on a file, the file contents will be shown in the editor window. Click the right mouse button on a file displays a shortcut menu with an Open command and a Check button. Select the Open command and the selected file will be shown in another editor window.

8. Invoke the Rule Organizer. Select the Tools > Rule Organizer… menu item in the main frame, the Rule Organizer window will be shown on the screen:

There are total nine build in groups of rule, by default, the Coding Style, Naming Convention, and VITAL Compliant groups are disabled. Click the right mouse button on any Rule Group to enable or disable it. You can get help on a rule by selecting that rule in Rule Organizer and pressing the F1 key.


9. Start checking. In the main frame, select Run > Lint to start the checking process. While

running the process, a progress window will appear.

10. Viewing and editing violations. After the checking process is down, the result will be reported in the Report Viewer window, which consists of two sub-windows: Tree and Detail Windows.

You can click on the plus (+) icon to expend the rule, thus showing more details, or click on the minus (-) icon to collapse, thus hiding the details. When left-clicking on a rule message, the detailed information will be shown in the detail window.


11. Link to the nTrace/nSchema. Double click on a rule message, you will see the nSchema

window is invoked, and the schematic related to the violation will be shown as below.

You may also use the nTrace to trace the source codes.

12. Try to fix some violations and re-invoke the lint process to check the results.


Lab: Using the Verilog Simulator 1. Create the lab directory:

mkdir ~/CBDC_LAB/03


3. Edit and save the 16-bit three-stage pipelined multiplier as mult16p3.v

module mult16p3(a, b, clk, p); input [15:0] a; input [15:0] b; input clk; output [31:0] p; reg [15:0] a_reg0, a_reg1, a_reg2, b_reg0; reg [ 7:0] b_reg1; reg [ 3:0] b_reg2; reg [23:0] p_reg1; reg [27:0] p_reg2; wire [19:0] t1, t2; assign t1 = a_reg1 * b_reg1[3:0]; assign t2 = a_reg2 * b_reg2; assign #1 p = {t2, 12'b0} + p_reg2; always @(posedge clk) begin a_reg0 <= a; b_reg0 <= b; a_reg1 <= a_reg0; b_reg1 <= b_reg0[15:8]; p_reg1 <= a_reg0 * b_reg0[7:0]; a_reg2 <= a_reg1; b_reg2 <= b_reg1[7:4]; p_reg2 <= {t1, 8'b0} + p_reg1; end endmodule

4. Check the syntax correctness of mult16p3.v:

verilog –c mult16p3.v


5. Edit and save the random pattern generator as pattern.v

module pattern;

parameter TOTAL = 3000; reg [15:0] a, b; reg [31:0] p; integer i, sf; initial begin sf = $fopen("mult16p3.dat"); for (i=0; i<TOTAL; i=i+1) begin a = $random; b = $random; p = a * b; $fdisplay(sf, "%b_%b_%b", a, b, p); end $fclose(sf); end endmodule

6. Generate test patterns:

verilog pattern.v

7. Take a look at the generated pattern file mult16p3.dat.


8. Edit and save the testbench as mult16p3.vt

`timescale 1ns/10ps

module test; reg [15:0] a; reg [15:0] b; reg clk; wire [31:0] p; integer i, error; reg [31:0] prod0, prod1, prod2, prod3; reg [63:0] pattern [2999:0]; reg [63:0] t; mult16p3 U0 (.a(a), .b(b), .clk(clk), .p(p)); initial begin clk = 1'b0; forever #2.5 clk = ~clk; end initial begin $readmemb("mult16p3.dat", pattern); error = 0; for (i=1; i<=3000; i=i+1) begin t = pattern[i]; @(negedge clk); a = t[63:48]; b = t[47:32]; prod3 = prod2; prod2 = prod1; prod1 = prod0; prod0 = t[31:0]; @(posedge clk) if (p != prod3) begin $write("ERROR: %d != %d\n", p, prod3); error = error + 1; end end $write("Error Count: %d / %d\n", error, i-1); @(posedge clk); $finish; end initial begin $dumpfile("mult16p3.vcd"); $dumpvars(0, test); end endmodule


9. Simulate the design:

verilog mult16p3.vt mult16p3.v

10. Take a look at the Value Change Dump (VCD) file mult16p3.vcd.

11. Invoke the waveform browser: simvision –waves &

12. In the SimVison:Waveform window, select File>Open Database..., when the Open Database window pops up, change the Files of type to VCD Files (*.vcd), select mult16p3.vcd and click Open, when the File Translation window appears, click OK.

13. In the SimVison:Waveform window, select Windows>New Design Browser, when the SimVision:Design Browser window appears, click test and select all signals under it. Click the waveform icon and all signals will be added to the waveform window.

14. Try to set the display format of a[15:0], b[15:0], p[31:0]and prod3[31:0] to Decimal.

15. Try to zoom out the wavrform to make it easier for observation.

16. Check some values shown on the waveform and make sure the results are correct.


Lab: Using the VN-Cover Code Coverage Analyzer 1. Create the lab directory:

mkdir ~/CBDC_LAB/04


3. Copy the example Verilog design files to your lab directory: cp ~/CBDC/LAB/04/* . Take a look at those source files.

5. Invoke the VN-Cover by using the following command: vnavigator &

6. Click the Design Entry icon in the main window to display the Design Entry window. Click the Load button in the Design Entry window, select the monitor.f and click OK. There are 9 files added to the Verilog Source window.

7. Click the Dynamic Verification VN-Property VN-Cover icon in the main window to display the Dynamic Verification Flow window.

8. Click on Set Simulator icon in the Flow Manager window, the Select Simulator window will be opened, click on Cadence Verilog-XL 3.4-4.1 and click OK.

9. Click the Define Coverage Criteria icon to display the Instrument window, clicking on the Instrument button in the Instrument window, when the Select A Verilog Command File window pops up, click OK. After the Verilog command file is generated, click OK on the Instrumentation Completed window.

10. Click on Simulate icon in the Flow Manager window, the Simulate window will be opened, click on Add button and select Command File, then click OK. Click the Options button, when the Simulate Options window appears, de-select the Perform Property Checking button and click OK. Click the Simulate button to start the simulation. When the simulation finished, click OK on the Note window.

11. Click on Results icon in the Flow Manager window, the Results Summary window will be opened, click the Load Results Files button, when the Select results File(s) window pops up, click on vnavigator_results/vnavigator.index and click OK to load the results.

12. Click the Detail buttons under the Code Results Summary and under the FSM Results Summary field to observe the detailed code coverage analysis results.


Lab: Using the HDL and Design Compiler 1. Create the lab directory:

mkdir ~/CBDC_LAB/05


3. Create the synthesis working directory: mkdir work

4. Invoke the Synopsys Design Compiler Command-Line interface: dc_shell

5. Set the tool search paths: search_path = { ~/CBDC/LIB/CIC/SynopsysDC } + search_path

6. Map the default working library to work: define_design_lib WORK –path ./work

7. Define the target technology mapping library: target_library = { typical.db }

8. Define the symbol libraries (optional): symbol_library = { umc18.sdb generic.sdb class.sdb }

9. Define the synthetic libraries: synthetic_library = { dw_foundation.sldb }

10. Define the link libraries: link_library = { typical.db dw_foundation.sldb }

11. Read and analyze the 16-bit three-stage pipelined multiplier Verilog design file: analyze –format verilog –library WORK { ../03/mult16p3.v }

12. Elaborate the design: elaborate mult16p3 –arch verilog –library WORK


13. Set the current design to mult16p3:

current_design mult16p3

14. Perform logic-level and gate-level synthesis and optimization on the current design and do not preserve any design hierarchy: compile –ungroup_all

15. Check the resulted design area: report_area Number of ports

=

Number of nets

=

Number of cells

=

Number of references

=

Combinational area

=

Noncombinational area

=

Net Interconnect area

=

Total cell area

=

Total area

=

16. Check the resulted design timing:

report_timing –path full –delay max –max_path 1 –nworst 1

Startpoint

=

Endpoint

=

data arrival time

=


17. Check the standard cells used in this design:

report_reference

Total references

=

18. Define the properties for clock net:

create_clock –name clk –period 5 –waveform { 0 2.5 } { clk } set_clock_uncertainty -setup 0.5 clk set_clock_uncertainty -hold 0.5 clk set_dont_touch_network find(clock, clk) set_drive 0 { clk } set_fix_hold find(clock, clk)

19. Check the resulted clock net properities: report_clock

20. Define some design constraints: set_load 0.075 all_outputs() set_max_transition 0.5 find(design, mult16p3) set_fix_multiple_port_nets -feedthroughs

21. Re-synthesis and optimize the design with high mapping effort: compile –map_effort high

22. Check the area for the re-optimized design: report_area Number of ports

=

Number of nets

=

Number of cells

=


=


Combinational area

=


=


=

Total cell area

=

Total area

=

23. Check the timing for the re-optimized design:

report_timing –path full –delay max –max_path 1 –nworst 1

Startpoint

=

Endpoint

=

data arrival time

=

24. Check the standard cells used in the re-optimized design:

report_reference

Total references

=

25. Change the naming rule to Verilog:

change_names –rule verilog –verbose -hierarchy

26. Define some attributes for Verilog netlist exporting: verilogout_no_tri = TRUE verilogout_single_bit = FALSE verilogout_show_unconnected_pins = TRUE

27. Export the resulted Verilog netlist: write –format verilog –hierarchy –output mult16p3_gate.v

28. Exit the Design Compiler Command-Line Interface: quit

29. Take a look at the saved Verilog netlist file mult16p3_gate.v.


Lab: Gate-level Design Analysis

Delay Calculation

1. Create and change the working directory to the lab directory: mkdir ~/CBDC_LAB/06; cd ~/CBDC_LAB/06

2. Invoke the Synopsys PrimeTime Command-Line interface: pt_shell

3. Set the search paths: set search_path {. ~/CBDC/LIB/CIC/SynopsysDC}

4. Set the link paths: set link_path {* typical.db}

5. Read the Verilog netlist: read_verilog ../05/mult16p3_gate.v

6. Link the design: link_design mult16p3

7. Specify the driving cell at the design input ports: set_driving_cell –lib_cell INVX1 [all_inputs]

8. Specify the capacitive load at the design output ports: set_load –pin_load 0.075 [all_outputs]

9. Specify the capacitive load at the design output ports: set_wire_load_model –name UMC18_Conservative

10. Export the SDF file: write_sdf -no_edge mult16p3.sdf

11. Exit the pc_shell: quit

12. Take a look at the saved SDF file mult16p3.sdf.


Gate-level Simulation

1. Edit and save the Verilog gate-level testbench file as mult16p3_gate.vt

`timescale 1ns/10ps module test; reg [15:0] a; reg [15:0] b; reg clk; wire [31:0] p; integer i, error; reg [31:0] prod0, prod1, prod2, prod3; reg [63:0] pattern [2999:0]; reg [63:0] t; mult16p3 U0 (.a(a), .b(b), .clk(clk), .p(p)); initial $sdf_annotate("mult16p3.sdf", U0, , "mult16p3_sdf.log"); initial begin clk = 1'b0; forever #2.5 clk = ~clk; end initial begin $readmemb("../03/mult16p3.dat", pattern); error = 0; for (i=1; i<=3000; i=i+1) begin t = pattern[i]; @(negedge clk); a = t[63:48]; b = t[47:32]; prod3 = prod2; prod2 = prod1; prod1 = prod0; prod0 = t[31:0]; @(posedge clk) if (p != prod3) begin $write("ERROR: %d != %d\n", p, prod3); error = error + 1; end end $write("Error Count: %d / %d\n", error, i-1); @(posedge clk); $finish; end initial begin $dumpfile("mult16p3_gate.vcd"); $dumpvars(0, test); end endmodule


2. Create the simulation control file run.f

mult16p3_gate.vt ../05/mult16p3_gate.v -v ../../CBDC/LIB/CIC/Verilog/umc18.v +sdf_error_info +sdf_verbose _neg_tchk +nowarnTFNPC

3. Perform the gate-level simulation:

verilog –f run.f

4. Take a look at the SDF annotation log and VCD files.

5. Check the simulation waveform.


Power Analysis

1. Invoke the Synopsys PrimePower Command-Line interface: pp_shell

2. Set the search paths: set search_path {. ~/CBDC/LIB/CIC/SynopsysDC}

3. Set the link libraries: set link_library {* typical.db}

4. Read the Verilog netlist: read_verilog ../05/mult16p3_gate.v

5. Define the current design: current_design mult16p3

6. Read the VCD file: read_vcd -strip_path test/U0 mult16p3_gate.vcd

7. Calculate power: calculate_power

8. Report power information: report_power

Total Power

=

Dynamic Power

=

Leakage Power

=

Switching Power

=

Internal Power

=

X-tran Power

=

Glitch Power

=

9. Exit the PrimePower Command-Line interface.


Lab: Using the DFT Compiler

Scan Insertion

1. Create the lab directory: mkdir ~/CBDC_LAB/07


3. Invoke the Design Compiler Command-Line Interface: dc_shell

4. In the dc_shell, set the target library: target_library = { ~/CBDC/LIB/CIC/SynopsysDC/typical.db }

5. Set the link library: link_library = { ~/CBDC/LIB/CIC/SynopsysDC/typical.db }

6. Read in the Verilog netlist: read –format verilog ../05/mult16p3_gate.v

7. Explicit link the design: link

Write out the pre-scan area and timing information: report_area > area.rpt report_timing > timing.rpt

8. Select the scan style as multiplexed Flip-Flop: test_default_scan_style = multiplexed_flip_flop

9. Check the test design rules: check_scan How many valid scan cells are reported?


10. Build the scan chain:

insert_scan

11. Recheck the test design rules: check_scan

12. Report the details of test ports: report_test –port What is the port name for “test_scan_out”? What is the port name for “test_scan_enable”? What is the port name for “test_scan_in”?

13. Report the details of cells on the scan-path report_test –scan_path What is the start point of the scan path? What is the end point of the scan path?

14. Write out the post-scan area and timing information: report_area > area_scan.rpt report_timing > timing_scan.rpt

15. Write out the scan-inserted Verilog netlist: write –format verilog –hierarchy –out mult16p3_gate_scan.v

16. Exist the dc_shell: exit


17. Check the area and timing reports (area.rpt, area_scan.rpt, timing.rpt,

timing_scan.rpt):

Pre-Scan Post-Scan Overhead (%)

Number of ports

Number of nets

Number of cells


Combinational area



Total cell area

Total area

Pre-Scan Post-Scan

Startpoint

Endpoint

data arrival time

18. Check the Verilog netlist without scan insertion to see how many FFs includes:

grep DFF ../05/mult16p3_gate.v then apply the same command on the scan inserted Verilog netlist: grep DFF mult16p3_gate_scan.v Any thing different between these two netlists?


Lab: Using the Conformal LEC 1. Create the lab directory:

mkdir ~/CBDC_LAB/08


3. Invoke the Conformal LEC: lec &

4. Read in the cell library, in the CONFORMAL-LEC window LEC> prompt, type: read library –Both –sensitive –Verilog ~/CBDC/LIB/CIC/Verilog/umc18.v

5. Read in the golden (pre-scan) design, type: read design ../05/mult16p3_gate.v –Verilog –Golden –sensitive

6. Read in the revised (scan inserted) design, type: read design ../07/mult16p3_gate_scan.v –Verilog –Revised –sensitive

7. Change to the LEC System mode, type: set system mode lec

8. Viewing unmapped and mapped points. Select Tools > Mapping Manager, when the Mapping Manager window opens, you will see some Unmapped Points there.

9. Performing comparison, with the Mapping Manger window, add all the mapped points as compared points for the comparison process, left-click the add all compared points icon

. To perform comparison, left-click the compare icon . Left-click the class icon

in the Compared Points section and de-select the Equivalent toggle switch on the pop-up menu.

10. Performing diagnosis, left-click to select any non-equivalent compared points, right-click and select Diagnose from the pop-up menu to open the Diagnosis Manager window. With the Diagnosis Manager window, left-click the Schematic button and select Open from the pop-up menu, take a look at the two schematics and think about what makes them non-equivalent. Close the schematic and Mapping Manager windows.


11. Change to the Setup System mode, in the CONFORMAL-LEC Window, type:

set system mode setup

12. Add some pin constraint to make designs equivalent. add pin constraints 0 test_se –revised

13. Repeat step 7-9 to compare the two designs again, make sure these two designs are equivalent now.

Apollo Laboratory Exercise

Apollo version 2003.06

Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Cell Based IC Physical Design (Apollo)

1

Lab 1

Start Using Apollo 1. Change to the working directory of lab1. Unix% cd ~/lab1

2. Invoke Apollo. The result is as shown in Fig. 1. Unix% Apollo &

Fig. 1

3. Choose “Library > Open” from the menu banner. 4. Complete the form based on the settings listed below and click OK. (Use the left mouse button to

select commands or objects) “Open library successfully” will be shown on the Input/Message area.

Library Name c4msram32x4s_frLibrary Path

5. Choose “Cell > Open”. The “Open Cell” form will pop up. 6. Click Browse in “Open Cell” form to select the cell we want to open. The “Browse Cell“ form

will pop up. 7. Click c4msram32x4s in the left column of “Browse Cell” form. Note that it will be displayed in

“Cell Name” field of “Open Cell” form. 8. Click OK. The cell window will pop up. 9. Move the cursor on the cell window to see if the current coordinate shown around the upper-left

corner changes when you move the cursor. 10. Place the cursor right above the view command short-cut buttons to display a tag that tells you

what the button does. 11. Find “zoom out 2X” button and click it. 12. Find “previous view” button and click it. 13. Find “next view“ button and click it. 14. Find “zoom in 2X” button and click it.


2

15. Find “zoom to area” button and click it. 16. Define the zoomed area by drawing a rectangle. 17. Find “fit cell” button and click it. 18. Find “fit with margin” and click it. (You can also type the hotkey “f” to fit with margin) 19. Key in load “zo1.lab1＂ in the Input/Message area. 20. Click “Select-point” button and then click the text VDD in the window. Is the text VDD

highlighted? 21. Click “Query-object” button. Check what is shown in the Input/Message area. 22. Click “Deselect-all” button. 23. Click “Ruler” button. Measure the length of the text VDD? 24. Choose “Cell > Create” and click the Help button in “Create Cell” form. The online document

pops up. 25. Close Documentation Browser and cancel Create Cell form. 26. Key in help “geCreateCell＂ in Input/Message area. The same online document as above pops

up. 27. Choose “Tools > Quit” to quit from Apollo. 28. Invoke Apollo. Unix% Apollo &

29. Choose “Library > Open”. 30. Complete the form based on the settings listed below and click OK.

Library Name stdcellLibrary Path

31. Choose “Cell > Open”. 32. Complete the form based on the settings listed below and click OK. The cell window pops up.

What view is opened now? Check the upper left corner of the window to find the answer. Cell Name ad01d0

33. Using “Query-object” button to find the answers of the following questions: A. What is the layer name and number of the rectangle with red border? B. What is the layer name and number of the light blue polygon? C. What is the layer name and number of the dark blue rectangle? D. What is the layer name and number of the rectangle with yellow dashed border?

34. Choose “Cell > Close”. 35. Click “Discard All” button and OK to close the cell window without save. 36. Choose “Cell > Open”, Complete the form based on the settings listed below and click OK. The

cell window pops up. What view is opened now? Check the upper left corner of the window to find the answer.

Cell Name ad01d0.FRAM37. Click the “Layer panel” button and “Layer Panel” window appears. The PRBoundary layer is

covered completely by boundary layer. Show PRBoundary layer in the cell window by disabling the visibility of boundary layer.


3

38. Use Ruler to measure the width and height of this cell. Write down the cell width and height. 39. Choose “Cell > Close”. Click “Discard All” button and click OK to close the cell window without

save. 40. Choose “Cell > Open” from menu banner, and fill the fields in Open Cell form as shown below

Click OK. Cell Name unitTile

41. Use Ruler to measure the width and height of this cell. 42. Click “Window Options” button. Select wire track in Visible Objects group and then click Apply

and Redraw. The METAL1, METAL2, METAL3, METAL4 tracks all appear. 43. Select “Tools > Quit” to quit from Apollo.


4

Lab 2

Physical Design of a 2x2 Multiplier In this laboratory exercise, the gate-level netlist (including IO pads) of a 2x2 multiplier is given.

Follow the instructions in the proceeding paragraphs to complete the physical design. The IO pads used are listed in Table I and the desired floor plan is shown on Fig. 1.

Table I Type Master Name Instance Name(s)

ipad_CLK,ipad_RESET,ipad_IN1_0 INPUT P2A

ipad_IN1_1,ipad_IN2_0,ipad_IN2_1

opad_OUT_0,opad_OUT_1 OUTPUT P8A

opad_OUT_2,opad_OUT_3

CORE POWER PVDDC core_vdd1

CORE GROUND PVSSC core_vss1

IO POWER PVDDR io_vdd1

IO GROUND PVSSR io_vss1

Corner PCORNER cornerLL,cornerLR,cornerUR,cornerUL

Fig. 1


5

1. Change to the working directory of lab2. Unix% cd ~/lab2

2. Invoke Apollo. Unix% Apollo &

3. Translate Netlist A. Choose “Tools > Data Prep”. B. Choose “Netlist In > Verilog In”. C. Complete the form based on the settings listed below and click OK.

Verilog File Name CHIP_for_pr.vg

Verilog List File Name

Library Name mul

Tech File Name umc18_CIC.tf

HDL To GDSII Map File

Bus Naming Style [%d]

Verilog Model Directory

Model File Extension

Net Name for 1’b0 GND

Net Name for 1’b1 VDD

Hierarchy Separator .

Bus Name Append

Multiple PG Nets Disable

Set Case Sensitive Enable

No Backslash Insertion to avoid Hier Name Collisions Enable Remove First Backslash Of All Escaped Identifiers Disable

Create Bus For Undefined Cells From Connection

D. A library named “mul” is created. Now the library contains only NET view. Under UNIX command prompt, type ls mul, you should see the sub-directory “NETL”.

4. Add Reference Library A. Choose “Library > Add Ref”. B. Complete the form based on the settings listed below and click Apply.

Library Name mul

Ref Library Name umc18_framC. Complete the form based on the settings listed below and click OK.

Library Name mul

Ref Library Name umc18io3v5v_5lm5. Expand Netlist

A. Choose “Netlist In > Expand”. B. Complete the form based on the settings listed below and click “Global Net Options”.


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Library Name mul

Unexpanded Cell Name CHIP.NETL

Expanded Cell Name CHIP.EXP

Precede hierarchical names with “/” Disable

Expand netlist cell with no instance Enable

Stop at FRAM view cells only Disable

Print out net has a pin but no connections Disable C. Complete the form based on the settings listed below and click Apply.

Mode Add

Net Name VDD

Port Pattern VDDD. Complete the form based on the settings listed below and click Apply. Then click Hide.

Mode Add

Net Name GND

Port Pattern GNDE. Click OK. The EXP view will be created.

6. Open Library A. Choose “Tools > ApolloII”. B. Choose “Library > Open”. C. Complete the form based on the settings listed below and click OK.

Library Name mulLibrary Path

7. Create an Empty Cell A. Choose “Cell > Create”. B. Complete the form based on the settings listed below and click OK. A cell window will pop

up. Cell Name CHIP

8. Bind Netlist and Layout A. Choose “Design Setup > Bind Netlist”. B. Complete the form based on the settings listed below and click OK.

Net Name CHIP.EXPC. Click the cell window and press “f”. A number of standard and IO cells should be seen

inside the cell window. 9. Specify Global Net Connections

A. Choose “PreRoute > Connect Ports to P/G”. B. Complete the form based on the settings listed below and click Apply. Do you know what’s

done in this step?


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Net Name VDD

Port Pattern VDD

Cell Master Pattern .*

Cell Instance Pattern .*

Net Type Power

Net SubType Core Pad

Cell Types Std / Module Cell

Pad

Update Tie Up/Down Disable Mode Connect

C. Click OK on the dialog box that pops up. D. Complete the form based on the settings listed below and click OK. Do you know what’s

done in this step? Net Name GND

Port Pattern GND

Cell Master Pattern .*

Cell Instance Pattern .*

Net Type Ground

Net SubType Core Pad

Cell Types Std / Module Cell

Pad

Update Tie Up/Down Enable Mode Connect

E. Click OK on the dialog box that pops up. F. You should see the following messages on the Input/Message area.

G. Choose “Cell > Save”. H. Choose “Cell > Save As”. I. Complete the form based on the settings listed below and click OK.

Cell Name CHIP_connpgoverwrite Enable

10. Load the TDF File (IO Constraints) A. Choose “Design Setup > Load TDF”. B. Complete the form based on the settings listed below and click OK.


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Cell Name

TDF File Name io.tdf11. Setup the Floor Plan

A. Choose “Design Setup > Set Up Floorplan”. B. Complete the form based on the settings listed below and click OK.

Control Param aspect ratio

Core Utilization 0.7

Row/Core Ratio 1

Core Aspect Ratio(H/W) 1 Horizontal Row Enable

Double Back Enable

Start First Row Disable

Flip First Row Enable

Core To Left 60

Core To Right 60

Core To Bottom 60

Core To Top 60

Keep Macro Place Disable

Keep Std Cell Place Disable

Min Pad Height Disable

Pad Limit Disable

C. Choose “Cell > Save” 12. Create P/G Rings

A. Choose “PreRoute > Rectangular Rings”. B. Complete the form based on the settings listed below and click OK. Check the cell window

to see if the P/G ring is created successfully. Around Core

Net Name(s) VDD, GND

Skip Side(s)

L-Width / L-Layer 25 / 48 R-Width / R-Layer 25 / 48 B-Width / B-Layer 25 / 50 T-Width / T-Layer 25 / 50

Offsets Are Absolute

Offsets Left 5

Offsets Right 5

Offsets Bottom 5

Offsets Top 5

All other options Default value


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13. Create P/G Straps A. Choose “PreRoute > Straps”. B. Complete the form based on the settings listed below and click OK. Check the cell window

to see if the P/G strap is created successfully. Direction Vertical

Start Y 315

Start X 315

Net Name(s) VDD, GND

Width 10

Layer 48

Low Ends At First Targets

High Ends At First Targets

All other options Default value 14. Pre-route Macros & Pads

A. Choose “PreRoute > Macros/Pads”. B. Complete the form based on the settings listed below and click OK.

Instance Type(s) Pad

Select Pins Automatically and Route Only Those on Pin Layer 48 All other options Default value

C. Check if “core_vdd1” is connected to the power ring and “core_vss1” is connected to the ground ring.

D. Choose “Cell > Save”. E. Choose “Cell > Save As”. F. Complete the form based on the settings listed below and click OK.

Cell Name CHIP_prerouteoverwrite Enable

15. Automatic Placement A. Choose “Place > Design Placement”. B. Click OK and check if the standard cells are placed. C. The following message should be shown in the Input/Message area.

D. Check the 1D congestion map. Zoom in until you can see the numbers on it. Do you know

what the numbers mean? E. Choose “Cell > Save”. F. Choose “Cell > Save As”. G. Complete the form based on the settings listed below and click OK.

Cell Name CHIP_placeoverwrite Enable

16. Clock Tree Synthesis


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A. Choose “Clock > Specify Clock Net”. B. Complete the form based on the settings listed below and click OK.

Net Name(s) From Window

Net Name(s) i_clk

File Name

Net Type Clock

C. Choose “Timing > Timing Setup > Timing Model > Delay Model”. D. Set “Cell Delay Model” to “Table Look Up” and “Net Delay Model” to “AWE”. E. Click Apply and then click Hide. F. Choose “Timing Spec > Load TDF”. G. Set “TDF File Name” to “clk.tdf” and click OK. H. Choose “Clock > Auto. (Gated) Clock Tree”. I. Complete the form based on the settings listed below and click OK.

Net Name(s) i_clk

Buffer(s) CLKBUFXL, CLKBUFX1, CLKBUFX2, CLKBUFX3,

CLKBUFX4, CLKBUFX8, CLKBUFX12, CLKBUFX16,

CLKBUFX20

Delay Cell(s) DLY1X1, DLY2X1, DLY3X1, DLY4X1

Name Separator _ All other options Default value

J. View the file “CTS.clockTree”, how many clock buffers are added? K. Choose “Cell > Save”. L. Choose “Cell > Save As”. M. Complete the form based on the settings listed below and click OK.

Cell Name CHIP_ctsoverwrite Enable

17. Add Core Fillers A. Choose “PostPlace > Add Core Fillers”. B. Complete the form based on the settings listed below and click OK.

Master Cell Name(s) FILL64, FILL32, FILL16, FILL8,

FILL4, FILL2, FILL1

respect placement blockage Enable

between std cells only Enable

Connect to Power Net (optional) VDD

Connect to Ground Net (optional) GND All other options Default value

18. Add IO Fillers A. Choose “PostPlace > Add Pad Fillers”. B. Complete the form based on the settings listed below and click OK.


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Filler PFILL, PFILL_9, PFILL_1, PFILL_01

Overlap Filler PFILL_01

All other options Default value 19. Route Standard Cell P/G

A. Choose “PreRoute > Standard Cells”. B. Click OK and check if the power and ground nets of the standard cells are connected.

20. Since there are no buffers added in CTS stage, it’s not necessary to route clock nets here. 21. Auto Route

A. Choose “Route > Auto Route”. B. Click OK. C. The Total Violations are shown in the Input/Message window now. Are there any violations?

22. Optimize Routing A. Choose “Query > List PR Summary” to find the P&R statistics.

B. Write down the Total Wire Length & Total Number of Contacts. C. Choose “Route > Optimize Routing”. D. Click OK. E. Choose “Query > List PR Summary” again.

F. Compare the Total Wire Length & Total Number of Contacts to the previous values. Is there

any improvement? G. Choose “Cell > Save”. H. Choose “Cell > Save As”. I. Complete the form based on the settings listed below and click OK.

Cell Name CHIP_routeoverwrite Enable

23. Write SDF Timing Information


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A. Choose “Timing > SDF Write” and click OK. B. “CHIP.SDF” will be generated.

24. Create Hierarchical Netlist A. Choose “Tools > Data Prep”. B. Choose “Output > Create HNET”. C. Complete the form based on the settings listed below and click OK.

Library Name mul

Cell Name CHIP.CEL

Reference Netlist Cell Name CHIP.NETL Output Cell Name CHIP.HNET


D. Choose “Output > Hierarchical Verilog Out”. E. Complete the form based on the settings listed below and click OK.

Library Name mul

Cell Name CHIP.HNET

Verilog Out Data File CHIP_pr_sim.vg

Output Wire Declaration Enable

Output 1’b1 for Power(VDD, vdd, …) and1’b0 for Ground(VSS, gnd, …)

Enable

Output Bus As Individual Bits Disable

Reference Top NETL Cell to Output Bus CHIP.NETL


F. Compare “CHIP_pr_sim.vg” with “CHIP_for_pr.vg”, they should be almost the same. G. Choose “Library > Close” and click OK. H. Select “Save All” and click OK. I. Choose “Library > Open” to open the library “mul”. J. Choose “Cell > Open” to open the cell “CHIP”.

25. Fill Notches and Gaps / DRC / LVS A. Choose “Tools > ApolloII”. B. Choose “Route Utility > Fill Gap/Notch”. C. Click OK. D. Choose “Verify > DRC”. E. Select “List Error Summary Immediately” and click OK. F. Check the error summary. Are there any violations? G. Choose “Verify > LVS”. H. Select “List Error Summary Immediately” “Include existing Notch/Gap Fill Cell” and click

OK. I. Check the error summary. Are there any violations? J. Use “Verify > Show First Error” and “Verify > Next Error” to find the violations. What

are the violated nets?


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26. Export Physical Data A. Choose “Tools > Data Prep” & “Output > Stream Out”. B. Complete the form based on the settings listed below and click OK.

Stream File Name CHIP.gds

Library Name mul

Layer File stout.map

Child Extraction Depth 20

Convert Specified Cell

Cell Name CHIP

Convert Reference Lib Child Cells Enable

Text Conversion Factor 1.000

Text Width 0.000

Flatten Devices & Device Arrays

Fill FILL

Force output outdated Fill Cell Disable

Merge Additional Views Disable

Generate Instance Name As Prop Disable

Generate Geometry Property Disable

Strip Backslash from Instance/Net Names Disable Pin/Net Options > Output Net As Text

C. Check if fill data is transferred. D. Check if “CHIP.gds” is generated. E. Choose “Tools > Quit” to quit from Apollo.


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lab: initial setupweng/courses/ic_2007/... · 2020. 4. 23. · c. m. huang / cic-cbdc / 01.2004 lab...

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