labactivity2gggggggggawdsaaaveusall

7/25/2019 LabActivity2GGGGGGGGGAWDSAAAVEUSALL

1/28

ECE 126

Introduction to Analog Integrated Circuits Design

Lab 2: Common Source Amplifer with

Resistor Load and Source Degeneration

Submitted by:

Ceferino Kevin A. Tan

BSECE 4

Submitted to:

rof. Allenn dela Cerna !o"aton


2/28

Ceferino Kevin A. Tan BSECE 4 Se#tember $%& $'()

Step 1:

*ollo"ing t+e circuit of ,gure 4.(& simulate t+e -in-outDC transfer curve as it "as obtained in ,gure 4.$ and

t+e fre/uency res#onse as in ,gure 4.0.

Relation o !inand !out

C"DE

ste#(a1tan

.lib 2C:3syno#sys3rf'(.l2

TT

m( vout g gnd gnd nc+

l5'.(u "5'.6u

vdd vdd gnd (.v

vin g gnd '.%v

r( vout vdd ('7cload vout gnd ('#

.o#

.o#tion #ost #robe

.dc vin ' $ '.'(

.#robe v8vout9

.end

#"$ "utput

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id 00.'$'u

ibs .6(e$(

ibd 0.$44'n

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%igure 1T+e -in-outgra#+ s+o"s +o" t+e out#ut voltage8ya


3/28



4/28


%re&uenc' Response

C"DE

ste#(b1tan

.lib 2C:3syno#sys3rf'(.l2 TT

m( vout vin gnd gnd nc+ l5'.(u

"5'.6u

vdd vdd gnd (.v

vin vin vg ac (

vg vg gnd '.%

r( vout vdd ('7

cload vout gnd ('#

.o#

.#robe v8vout9

.o#tion #ost #robe

.#lot ac vdb8vout9

.ac dec ('' (' ('g.meas ac >B "+en vdb8vout9 5 '

.alter

vg vg gnd '.4

.alter

vg vg gnd (

.alter

vg vg gnd (.)

.end

%igure 2T+e gainfre/uency res#onse gra#+. At t+e bias #oint -inDC5'.%-& t+e DC

gain of t+e circuit is 0.$$(6 dB. *rom to# to bottom& t+e >ainBand"idt+s are:4.066(?@=&0.)(66?@=& A& A.


5/28


Step 2:

C+ange t+e value of in ,gure 4.( and simulate t+e resulting "aveforms of ,gure

4.4& t+en list t+e results as in table 4.( and com#are t+em "it+ +and calculation

results.

C"DESte#$1tan


TT

m( vout vin gnd gnd

nc+ l5'.(u "5'.6u

vdd vdd gnd (.v

vin vin vg ac (

vg vg gnd '.%

r( vout vdd $'7

cload vout gnd ('#

.o#

.#robe v8vout9

.o#tion #ost #robe

.#lot ac vdb8vout9

.ac dec ('' (' ('g

.meas ac >B "+en

vdb8vout9 5 '

.alter

vg vg gnd .4r( vout vdd (7

.alter

vg vg gnd (

r( vout vdd ($7

.alter

vg vg gnd (.)

r( vout vdd 0'7

.end

#"$ "utput

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6/28


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7/28


%igure (AC analysis "it+ di;erent values of (. otice t+at t+e curve for "+en

-g5'.%v and 5$'7 no" +as t+e +ig+est gain& but #ractically still +as a smaller >.B.

t+an for -g5(v and 5($7.

(879 out879 -g8-9A 8>ain in

dB90dB 8@=9 >.B. 8@=9

$'70.40$(6

4('.% ($.) (7 0.66$%?

(7 A '.4 (4. A A

($7$.64%4

40( %.$ (.4? 4.$'?

0'7 A (.) $%. A A

)able 1S+o"s t+e c+ange in gain and >B for "+en t+e resistance (and t+e in#ut

voltage -gis varied.


8/28


*and Calculations or step 2


9/28


Step (:

*ollo"ing t+e circuit of ,gure 4.)& simulate t+e -in

-outDC transfer curve as in ,gure 4.6 and t+e

fre/uency res#onse as in ,gure 4.%.

Relation o !inand !out

C"DE

ste#0a1tan


TT

m( vout g vs vs nc+

l5'.(u "5'.6u

vdd vdd gnd (.v

vin g gnd '.6v

r( vout vdd ('7

r$ vs gnd ('7

cload vout gnd ('#

.o#

.o#tion #ost #robe

.dc vin ' $ '.'(

.#robe v8vout9

.end

#"$ Result

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vdsat %$.(04(m

vod (.$'0m

beta (.040m

gam e; 6.460m

gm '.440(u

gds (.%4$)u

gmb $).(6)u

%igure +-in-outDC c+aracteristic curve for CS "it+ source degeneration. ote t+at

"e +ave a muc+ smaller slo#e magnitude at t+e saturation region.


10/28


%re&uenc' Response

C"DE

ste#0b1tan


TT

m( vout vg vs vs nc+

l5'.(u

"5'.6u

vdd vdd gnd (.v

vin vin gnd ac (

vg vg vin '.%

r( vout vdd ('7

r$ vs gnd (7

cload vout gnd ('#

.o#

.#robe v8vout9

.o#tion #ost #robe

.#lot ac vdb8vout9

.ac dec ('' (' ('g

.meas ac >B "+en

vdb8vout9 5 '

.end

#"$ Result

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%igure ,AC analysis of CS am#li,er "it+ source degeneration. lacing a source

resistance of (7 +as resulted in a ne" DC gain of 4.(dB. Fur >.B. value8+ig+lig+ted

above9 is given by $.4'4'?@=.


11/28


Step +:

C+ange t+e value of sin ,gure 4.) and simulate t+e resulting "aveforms of ,gure

4.G list t+e results as in table 4.$. T+en& com#are t+em "it+ +and calculation

results.

C"DE

Ste#41tan


TT


l5'.(u

"5'.6u

vdd vdd gnd (.vvin vin gnd ac (

vg vg vin '.%

r( vout vdd ('7

r$ vs gnd )''

cload vout gnd ('#

.o#

.#robe v8vout9

.o#tion #ost #robe

.#lot ac vdb8vout9

.ac dec ('' (' ('g

.meas ac >B "+en

vdb8vout9 5 '

.alter

vg vg vin '.

r$ vs gnd (.)7

.alter

vg vg vin '.6

r$ vs gnd $7

.end

#"$ Results

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12/28


cbtot (.4)60f cgs )%.'0%)a cgd $(6.'(a

%igure 6AC analysis of a CS am#li,er "it+ source degeneration: -arying source

resistance s. 8To# to bottom9 H 8-g&s9: 8'.%&)'' 9&8'.&()'' 9&8'.6&$'''9.

$879 -g8-9 out879A 8>ain in

dB90dB 8@=9 >.B. 8@=9

'.) '.%).0'$60$

6.'( (.6%? $.((?

(.) '.%.$(60')$

).'$ (.6%? $.466%?

$ '.6 ($.'$)(0$$ '.$)4 (.6$? '.0?

)able 2s+o"s t+e variation of t+e gain& cuto; fre/uency& and >.B. "+en value of s

is c+anged. T+e value of outis not c+anged even "it+ t+e addition of a source

resistance s8+tt#:"+ites.sdsmt.educlassesee0$'notes0$'!ecture0$.#df9. See

t+at t+e cuto; fre/uency does not c+ange even "+en t+e gain does.

ou can see t+at +aving a source resistance "ill result in a very little di;erence in

cuto; fre/uencies for all curves.

Addition of a source resistance "ill result in a lo"ering of -gs"it+ res#ect to -i. Also&

t+is "ill result in a lo"ering of t+e smallsignal voltage gain as can be seen in t+e ;:

Av=gmRD

1+gmRs


13/28


Des#ite t+ese dra"bac7s& t+e source

resistanceJs maor bene,t is t+at t+e small

signal voltage gain "ill be made muc+ less

de#endent on t+e ?FS*ET transconductance.

ote t+at for CS "it+ S.D.& t+e out#utim#edance is given by t+e e/uations to t+e

rig+t:


14/28


*and Calculations or step +


15/28


Step ,:

C+ange t+e value of sin ,gure 4.)& and simulate t+e "aveforms of ,gure 4.(' to

observe t+e relations+i# bet"een Idsand -in.

C"DE

ste#)1tan


TT


l5'.(u "5'.6u

vdd vdd gnd (.v

vin vin gnd ac (

vg vg vin '.%

r( vout vdd ('7

r$ vs gnd )''

cload vout gnd ('#

.o#

.o#tion #ost #robe

.dc vg ' (. '.'(

.#robe i(8m(9

.alter

r$ vs gnd (7

.alter

r$ vs gnd (.)7

.alter

r$ vs gnd '7

.end

#"$ Results

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16/28


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%igure -*rom to# to bottom are t+e curves for "+en t+e source resistance8in

F+ms9 is '& )''& ('''& ()''.


17/28


-ital e/uation >m5

1

( 1gm )+Rs for a CS am#li,er "it+ source degeneration. T+us&"+en "e increase s& "e decrease t+e slo#e of our Ids-gsgra#+& "+ic+ im#lies t+at

"e "ill #roduce a muc+ smaller out#ut current for a given in#ut DC voltage "+enour source resistance is increased. Since Av5>mD& Avis no" given by Av5

RD

( 1gm )+Rs .


18/28


Step 6:

*ollo"ing t+e am#li,er con,guration of ,gure

4.((& t+e in#ut signal is an ideal sinusoidal "ave

"it+ '.')v am#litude& and t+e fre/uency is

(''7@=. erform t+e **T analysis to - into get t+efre/uency s#ectrum li7e ,gure 4.($

C"DE

ste#61tan

.lib

2C:3syno#sys3rf'

(.l2 TT

m( vout vg vs

vs nc+ l5'.(u

"5'.6u

vdd vdd gnd (.

vin vin gnd

sin8' '.') (''7

' ' '9

vg vg vin '.%

r( vout vdd ('7

r$ vs gnd )''

cload vout gnd

('#

.o#

.o#tion #ost

#robe

.tran 6$)n

('.$4m

.;t v8vg9

start5'

sto#5('.$4m

n#5(604

.end

#"$ Results

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19/28


%igure .*ast*ourier Transform of t+e -in. T+e result s+ould s+o" no +armonic

com#onent e


20/28


Step -:

erform t+e **T Analysis to -outin t+e circuit of ,gure 4.(( "+ile c+anging t+e value

of sto get t+e fre/uency s#ectrum li7e in ,gure 4.(0(6. !ist t+e results of ,gure

4.(0(6 li7e in table 4.0.

C"DE

Ste#%1tan

.lib

2C:3syno#sys3rf'

(.l2 TT

m( vout vg vs

vs nc+ l5'.(u

"5'.6u

vdd vdd gnd (.

vin vin gnd

sin8' '.') (''7

' ' '9

vg vg vin '.%

r( vout vdd ('7

r$ vs gnd '

cload vout gnd

('#

.o#

.o#tion #ost

#robe

.tran 6$)n

('.$4m

.;t v8vout9

start5'

sto#5('.$4m

n#5(604

.alter

r$ vs gnd )''

.alter

r$ vs gnd (7

.alter

r$ vs gnd (.)7

.end

#"$ Results

subc7t Rs/0

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21/28


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22/28


%igure L+en s5'& t+e gain for t+e (st& $nd& and 0rd@armonics are $$.$'dB&

)0.('dB& %).'dB.

%%) Anal'sis o !outwith Rs/0#,

%igure 10 L+en s5)''& t+e gain for t+e (st& $nd& and 0rd@armonics are $0.6'dB&

)).('dB& '.'dB.

%%) Anal'sis o !outwith Rs/1


23/28


%igure 11L+en s5('''& t+e gain for t+e (st& $nd& and 0rd@armonics are $4.'dB&

)6.%'dB& (.('dB.

%%) Anal'sis o !outwith Rs/1#,


24/28


%igure 12L+en s5()''& t+e gain for t+e (st& $nd& and 0rd@armonics are H$6.''dB&

).('dB& (.)'dB.

s879 -inDC8-9 -inAC8-9 A8dB9 -out8dB9

$nd

@armonic

8dB9

0rd

@armonic

8dB9

'

'.% '.')

%.$ $$.$' )0.(' %).'

'.)'' 6.'( $0.6' )).(' '.'

( 4.' $4.' )6.%' (.('

(.) 0.4 $6.'' ).(' (.)'

)able (S+o"s +o" t+e gains for t+e (st& $nd& and 0rd+armonics c+ange "+en t+e

value of sis c+anged. >enerally& increasing t+e svalue "ill result in t+e gains for

t+e $nd

and 0rd

+armonics to a##roac+ some common value.

34ES)5"S

(. @o" to increase t+e gain of CS am#li,er "it+ resistive loadM E


25/28


ote t+at increasing t+e L! ratio increases t+e slo#e of t+e Ids-dsgra#+ of

our n?FS 8as observed in t+e #revious lab activity9. T+erefore& "e increase

gmalong "it+ it& conse/uently& "e get a muc+ +ig+er gain magnitude.


26/28


$. e#lace sin ,gure 4.(( "it+ a diodeconnected n?FS. Nsing t+e ste#s "e

follo"ed before& "+at is t+e DC gain of t+is circuitM

%igure 1(T+e DC gain for t+e net"or7 "it+ a diodeconnected n?FS8of t+e

same as#ect ratio as main n?FS9 is no" 0.%'dB.


27/28


0. Nsing t+e con,guration of /uestion $& #erform t+e **T Analysis of -inand -out

to get t+e fre/uency s#ectrum of t+ese "aves. L+at +a##ens to t+e circuit

linearityM Is t+ere any di;erence "it+ ,gure 4.((M

%%) o !in

%igure 1+ote t+at for t+e **T of t+e in#ut voltage& "e see no signi,cant

di;erence com#ared to t+e net"or7 "it+ source resistance instead of t+e

diodeconnected n?FS in t+e source.


28/28


%%) o !out

%igure 1, ote t+at for t+e **T of t+e out#ut voltage -out& "e "e see no

signi,cant di;erence com#ared to t+e net"or7 "it+ source resistance instead

of t+e diodeconnected n?FS in t+e source.

labactivity2gggggggggawdsaaaveusall

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