labs practicing in design of combinational networks and fsm with concurrent error detection tatjana...

Labs Practicing in Design of Labs Practicing in Design of Combinational Networks and FSM Combinational Networks and FSM

with Concurrent Error Detectionwith Concurrent Error Detection

Tatjana Stanković, Goran Djordjević, Mile Stojčev

20752075Microprocessor systemsMicroprocessor systems

Outline of the talkOutline of the talk

I.I. IntroductionIntroductionII.II. Review of the ExercisesReview of the ExercisesIII.III. Tutorial ContentTutorial ContentIV.IV. Description of Overall Design ProcedureDescription of Overall Design ProcedureV.V. Examples of VHDL synthesisExamples of VHDL synthesisVI.VI. Concurrent error detectionConcurrent error detectionVII.VII. ConclusionConclusion


Directions: Directions:

- Electronics, Electronics, - Communications, Communications, - MicroelectronicsMicroelectronics VII semester 2+2+1 VII semester 2+2+1 VIII semester 2+2+1VIII semester 2+2+1

Structure of Lab ExercisesStructure of Lab Exercises

Lab exercisesLab exercises

Programming orientedProgramming oriented Logic design orientedLogic design oriented

DOS (4 exercises)DOS (4 exercises)

Intel 80x86 (15 exercises)Intel 80x86 (15 exercises)

MIPS (5 exercises)MIPS (5 exercises)

VHDL description of three VHDL description of three stage pipelined systemstage pipelined system

Four more exercises about Four more exercises about VHDL design of logic VHDL design of logic

structure with concurrent structure with concurrent error detectionerror detection


What we propose?What we propose?

• CAD tools for logic design


Involving four additional exercises in logic design to cover the following topics:

• Design of combinational networks with concurrent error detection with examples

• Design of sequentional networks with concurrent error detection with examples

What kind of literature use students?What kind of literature use students?


• Tutorial for VHDL design

• Textbook for Digital Logic Design


Tutorial ContentTutorial Content1. General Introduction

2. VHDL for Synthesis

3. CAD tools and Design Flow

After passing this step students become familiar with writing and simulating VHDL code, modeling combinational and sequential circuits, using design hierarchy.

During this step students learn how to use CAD tool for designing logic structures with PLD circuits.


Description of the Overall Design Description of the Overall Design ProcedureProcedure

• Design entryDesign entry

• Design synthesisDesign synthesis

• Functional simulationFunctional simulation

• Design implementationDesign implementation

CAD systemCAD system

Xilinx Integrated Software Environment - ISE 5 for design entry, synthesis and physical

implementation for FPGA circuits

ModelSim XE II/Starter 5.7 for functional and timing VHDL simulation.

Design flow

ISEModelSim

Design entry Design entry - writing source code in VHDL -- writing source code in VHDL -

x1x2

x3

f

behavioral description

Design synthesis Design synthesis

Synthesis is process of generating a logic circuit from a formal circuit description, automatically.

This process translate, or compile, VHDL code into a network of logic gates.

Synthesis Report

Functional simulationFunctional simulation

Test bench

Simulation output

Design implementationDesign implementation

Post-Place & Route Static Timing Report

Floor Planner

VHDL synthesis of combinational circuitsVHDL synthesis of combinational circuitsFour ways to describe a MUX – behavioral description

select statement

conditional assignment

If-then-else statement

case statement

Arithmetic circuitsArithmetic circuitsRipple-carry adder – structural description

FA

x1 y1

s1

c2FA

x0 y0

s0

c1 c inFA

x3 y3

s3

FA

x2 y2

s2

c3cout

The correct model is one in which

the sequential current state logic has been separate from

the combinational next state and output logic.

combinational next state and

output logic

sequential current state

logic

VHDL synthesis of sequential circuitsVHDL synthesis of sequential circuitsFSM code template - layoutFSM code template - layout

St0

Y=001

St1

Y=010

St2

Y=011

St3

Y=100

Con

trol

=1

VHDL synthesis of sequential circuitsVHDL synthesis of sequential circuitsFSM state encodingFSM state encoding

Coding schemes (sequential, Gray, Johnson, and one-hot) are defined in separate package:

Source code using sequential state encoding:

Concurrent error detectionConcurrent error detectionWhy it is important?

Technological advances have increased drastically the complexity of integrated circuits that can be realized on a single chip.

The move towards VLSI technologies with higher frequencies, lower voltage levels, and smaller noise margins is increasing the susceptibility of systems to transient and intermittent faults.

Early detection of errors is crucial for preserving the state of the system and maintaining data integrity.

Techniques for concurrent error detection (CED) permit early detection and containment of errors before they can propagate to other parts of the system and corrupt data.

General structure of CED General structure of CED

One general approach for CED is to encode the outputs of a circuit with an error detecting code.

function logic

check symbolgenerator

checkern n

k

p

input data

check part

data part

outputs

indicationerror

The insertion of CED circuitry

This methodology has several advantages:

We use a methodology for insertion of CED in synthesizable VHDL description of the original circuit, at the front-end of the synthesis process.

• It allows the error detection circuitry to be optimized along with the functional circuitry.

• The CED circuitry is taken into account when satisfying timing constraints.

• The approach of inserting the CED circuitry can be easily and seamlessly incorporated into the standard design flow.

Techniques for CED

All mentioned techniques can be applied on the outputs of the combinational circuits or on the states of sequential circuit.

The techniques for CED depend on the way in which the output of functional logic is encoded. We use:

• duplication function

• parity codes

• Berger codes

• Bose-Lin codes

Duplication of function as a technique for CED

The design implements two copies of the same circuit. The second copy produces output values complementing the value of the first copy, and a tree of two-rail code (TRC) checkers makes a bitwise comparison of the outputs.

TRC

checker circuit

primary outputs

primary

primary

signal

outputs

inputs

error

TRC

TRC

functionlogic

copy 2

functionlogic

copy 1

(complement)

Parity codes as a technique for CEDZ1Z2Z3Z4C1

Z5Z6Z7Z8C2

Z9Z10Z11Z12C3

Z13Z14Z15Z16C4

outputs

inputsn

TSC4parity

TSC3parity

TSC2parity

TSC1parity

Functionalblock

TSC

two-

rail

chec

ker

with

fou

r in

put p

airsf2

g2

g3

g4

g1

f4

f3

f1

f

g

indi

cati

oner

ror

Combinati-onal logic

withn-inputs

(x1,…, xn)and

16-outputs(z1,…, z16)

&4-centralcheck bits(c1,…, c4)

The parity bit is equal to the sum modulo 2 of the information bits or their complements. A parity check code is a code in which each check bit is a parity check for a group of output bits.

Berger and Bose-Lin codes as a technique for CED

The Berger check symbol of the information can adopt either the binary representation of the number of zeros in the information (B0) or the ones complement of the number of ones in the information (B1).

Bose-Lin codes - similar to Berger codes, but the number of bits is performed modulo 2, 4, 8 etc.

check bitsgenerator

TSC double-rail checker

. . .

XP

XP

Px (check bits) Ix (information bits)

codeword input

g f

Layout of Lab Exercise for Combinational Layout of Lab Exercise for Combinational Networks with CEDNetworks with CED

Check symbol generator is described as a separate process which include: - VHDL code of the original circuit - Code that transforms circuit outputs into check symbol bits

Original circuit Check symbol generator

Layout of Lab Exercise for Combinational Layout of Lab Exercise for Combinational Networks with CEDNetworks with CED

Structural description of circuit with CED

hardware

Checker

FSM with CEDFSM with CED

The simplest technique for inserting CED in FSM is to append a parity bit to each state-codeword.

Parity bits technique

ConclusionConclusion

Extension of Lab exercises for course Microprocessor Systems is considered with goal to include VHDL synthesis of combinational and sequential networks with concurrent error detection using contemporary CAD tools.

labs practicing in design of combinational networks and fsm with concurrent error detection tatjana...

Documents

vhdl design textbook

design flowafter

design hierarchy

vhdl design of logic

examples of vhdl synthesisvi

concurrent error detectionvii

tutorial contentiv

timing vhdl simulation