layout of capacitor

8/12/2019 Layout of Capacitor

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http://webpages.eng.wayne.edu/cadence/ECE6570/cap/Layout_of_Capacitor.htm

Layout of Capacitor

Theory

In principle, capacitor is nothing but two adjacent conductor plates with certain type of dielectric in-between. The

capacitance is calculated based on the following formula:

If d and are constants and the area is a rectangle, this formula can be modified as:

Therefore, to layout a capacitor, we have to figure out the geometric parameters of the rectangle based on C and c, then

draw it!

Practice

In the process (C5N_SUBME, =0.30m) we are using, the two polysilicon (poly and elec, also known as poly2) are a

proper pair to form a capacitor. The thin silicon dioxide between these adjacent layers yields good capacitance valueper unit area. This type of capacitor is called poly-poly2 capacitor.

A sample of how to construct a 100fF (100E-15) poly-poly2 capacitor with a width of 9m (30) is given to illustrate the

layout process.

i) Calculation

c(poly-poly2) = 0.800fF/m2

s = C/c = 100f / 0.800f = 125

l = s/w = 125 / 9 = 13.89

round l to the nearest multiple of remember, we can only draw geometric of multiple !!

So if w is given as 10m, you have to convert it to 10.05m before

you get started.

l = 13.95 = 46.5

ii) Draw poly and elec layers


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Draw a 9m x 13.95m rectangle with elec (yellow). Then cover it with a poly (red) rectangle, which exceed every

side of elec rectangle by 3m. (You will see why we need the extra 3m soon.)

Figure 1

iii) Cover the elec rectangle with M1_ELEC contacts and a metal1 rectangle

Use as many M1_ELEC contact as possible, without violating DRC, to cover the whole effective capacitance

area (elec). Then cover the elec with a metal rectangle. The purpose of these contacts and metal1 is to minimize

parasitic resistance.


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Figure 2

iv) Cover the 3m extended poly edge with M1_POLY contacts and metal1

Use as many M1_POLY contacts as possible, without violating DRC, to cover the extended poly edge. (Now you

understand where this 3m comes from. Each M1_POLY is 1.2m wide and DRC requires 1.8m between the

contact and elec.) Then cover the M1_POLY contacts with metal1 as shown in figure 3. The purpose of these

contacts is also to minimize parasitic resistance.

Figure 3


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v) Draw a n-well to cover the whole capacitor

Draw a n-well to cover the poly rectangle with 0.6m extension to fulfill DRC requirement. The purpose of this n-

well is to minimize field leakage.

Figure 4

vi) Place Pins

Place a metal2 POS pin and a M2_M1 contact on top of a M1_POLY contact. Place a metal2 NEG pin and a

M2_M1 contact on top of a M1_ELEC contact. Of course you can move the pins outside and use metal2 to

connect them to the respective contacts.


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Figure 5

vii) DRC check

Check DRC and correct all errors.

viii)Extraction

Do an Extraction without any switch and open the extracted view. A capacitor symbol should be placed at the

upper-left corner of the inner rectangle. Choose the symbol and check its value to ensure your layout is correct.

You are not going to get an exact match since the adjustment we made to fulfill the requirement but a

reasonable error is allowed.


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Figure 6

Thus we complete a 100fF capacitor layout.

layout of capacitor

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