July 25, 2004 GRETINA Workshop at ANL 1

GRETINA Workshop

Chinh Vu - LBNL

LBNL next generation DSP Board

July 25, 2004 GRETINA Workshop at ANL 2

Outline

• Review of the LBNL DSP board design flow.

• Report on current LBNL DSP boards.

• Proposed next generation of LBNL DSP board for GRETINA (Chinh Vu, Sergio Zimmermann, Harold Yaver)

July 25, 2004 GRETINA Workshop at ANL 3

Review of the LBNL DSP board design flow

• System Flow

• Digital Signal Processing Module

• DSP Functions used in FPGA

• Flow of data in the DSP board

July 25, 2004 GRETINA Workshop at ANL 4

System Flow

Aux. Det. Trigger

Global TriggerModule

Signal Digitizers

Local TriggerModule

30 Crystals

Data Storage

2.2 MB/s

Aux. Det. Data

66 MB/s

75 dual Processors

Workstations, Servers

6.9 MB/s

2.3 MB/s + Aux. Data

Network Switch

Processing Farm

Readout Computer

Crystal Pre-amplifier

July 25, 2004 GRETINA Workshop at ANL 5

Digital Signal Processing Module

Preamp/adc

Preamp/adc

Preamp/adc

FPGA FIFO VME/cPCI

Clock distribution & local oscillator

Digital Inputs/Outputs

Gigabit Serial InterfaceTrigger/Timing

100 MHz

100 MHz l k

External h

Control and monitor i

10 Inputs

July 25, 2004 GRETINA Workshop at ANL 6

DSP Functions used in FPGA

Data processing in FPGALeading Edge Discrimination: • yn = xn - xn-k (differentiation)• yn = (xn + xn-2) + xn-1<<1 (×4, Gaussian filtering)• Threshold comparison → LED time

Constant Fraction Discrimination: • yn = xn - xn-k (differentiation) • yn = (xn + xn-2) + xn-1<<1 (×2, Gaussian filtering)• yn = xn-k- fxn (constant fraction, f is an attenuation factor)• Zero crossing comparison → CFD time

Trapezoidal filter and energy determination (V.T Jordanov, G.F. Knoll, NIM A345 (1994) 337-345)• yn = yn-1 + ( (xn + xn-2m-k) )– (xn-m + xn-m-k) )• Maximum tracking → energy

Pole-Zero correction• yn = xn + In /τ (where τ is the pre-amplifier time constant)• In = In-1 + xn

July 25, 2004 GRETINA Workshop at ANL 7

Flow of data in the DSP board

Delay 1 k

Delay 2 m

Delay 3 k

Delay 4 m

Leading Edge Disc.

Const. FractionDisc.

EnergyP/Z

From ADC

LED Time

CFD Time

CFD Amplitudes

Energy

July 25, 2004 GRETINA Workshop at ANL 8

Report on current LBNL DSP boards.

• Commissioning of the 20 DSP boards

• Current support test system

July 25, 2004 GRETINA Workshop at ANL 9

Commissioning of the 20 DSP boards

July 25, 2004 GRETINA Workshop at ANL 10

Commissioning of the 20 DSP boards

• All 20 boards work reliably

• Currently 15 of them are using to test the first detector with 3 crystals each for a total of 111 channels

July 25, 2004 GRETINA Workshop at ANL 11

Current support test system

• It was developed for easy using with GUI for easy access and review of important parameters.

• It helps in quickly debug and testing the 20 boards

• Will helps to troubleshooting the boards later.

• Will helps expedite the new DSP development

July 25, 2004 GRETINA Workshop at ANL 12

Current support test system

July 25, 2004 GRETINA Workshop at ANL 13

Current support test system

July 25, 2004 GRETINA Workshop at ANL 14

Proposed next generation of LBNL DSP board for GRETINA (Chinh Vu, Sergio Zimmermann, Harold Yaver)

• Goals:• Changes proposed to the current DSP board• Preparation for the next generation of DSP board

July 25, 2004 GRETINA Workshop at ANL 15

Proposed Goals:

• Increase the ADC resolution to 14 bits for better tracking of incident gamma rays.

• Taking advantage of the latest and faster devices plus the later support tools.

• Reduce the system total cost due to cheaper parts with more internal logic (I.e Spartan 3 versus Vertex 2 FPGA)

• Pack more ADC channels into a board (I.e 10 channels)

July 25, 2004 GRETINA Workshop at ANL 16

Changes proposed to the current DSP board

• Comparison of current high speed ADC

Current ADC

AD9432

Analog Dev

AD6645

Ti

ADS5500

Unit

Number of bits 12 14 14

Sampling rate 105 105 125 MSPS

Analog input BW 500 270 750 MHz

Differential input range 2 2 2.3 Volts

Analog V/ Dig V 5/3.3 5/3.3 3.3/3.3 Volts

Cost (quantity of 100) ~88 ~114 ~124 $

July 25, 2004 GRETINA Workshop at ANL 17

Changes proposed to the current DSP board

•New FPGA with more logic, memory and cheaper

Virtex II XC2V3000

Spartan 3XC3S4000

Spartan 3XC3S5000

unit

System Gate 3 4 5 million

Total slice 14,336 27,000 33,000

Distributed RAM 448 430 520 Kbits

Block RAM 1728 1,728 1,872 Kbits

Dedicated Multiplier 96 96 104

Digital Clock Manager 12 4 4

Maximum I/O 720 712 784 Pads

Cost ~900 ~500 ~600 $

July 25, 2004 GRETINA Workshop at ANL 18

Changes proposed to the current DSP board

• Interface bus could be one of the following – Current VME-64x – PXI (Extension of CPCI for Measurement and

Automation System) – Optical G-link

July 25, 2004 GRETINA Workshop at ANL 19

Preparation for the next generation of DSP board

• Participated in seminar of the latest FPGA tool set flow for DSPapplications using XILINX ISE 6.2i, core generator together with Math Lab and Simulink to quickly implement DSP functions in FPGA.

• We are about to receive the new AGILENT Logic analyzer with capability of FPGA internal node probing for help in debugging of FPGA problems.

• Test and debugging support system for development of this new board will be quickly develop based on National Instrument’s Lab Window test system for current DSP board.