LC3 – ControllerFPGAsMultipliersDebounce CircuitBasic Operation of N and P Type FETsLogic Gates Built from FETs

Review for Final Exam

Output Forming

Logic

CurrentState

Input Forming

Logic

FF

FF

FF

LC-3 Datapath

OFLIFL

FF

FF

FF

LC-3 Datapath

Next State

CurrentState

DatapathControl

Datapath Status

Instruction Fetch

1. Copy PC contents to MARenaPC = 1 & ldMAR= 1

2. Perform memory readselMDR=1 & ldMDR=1

Increment PC selPC = 00 & ldPC = 1

3. Copy memory output register contents to IRenaMDR = 1 & ldIR = 1 IR

PC

ALU

enaPCldMAR

ldPC

selPC

selMD

RldM

DR

enaMDR

ldIR

AB

The Control Logic

IFL FlipFlops

OFL

IR N Z P

DR

SR2

selM

AR

selP

C

alu

Con

trol

SR1

ldM

DR

ldM

AR

regW

E

ldP

C

ldIR

mem

WE

enaM

AR

Men

aAL

Uen

aMD

Ren

aPC

selE

AB

1se

lEA

B2

selM

DR

nzpM

atch

The Fetch Cycle

1. PC MAR

2. PC PC+1, Mem[MAR] MDR

3. MDR IR

Fetch0

Fetch1

Fetch2

enaPCldMAR

enaMDRldIR

selPC <= “00”ldPCselMDR <= ‘1’ldMDR

A Note on Timing

• In all cases:– Buses are driven and muxes are selected during a state

– Registers and memory inputs are latched on the rising clock edge at the end of the state

F0 master loads

Fetch 0 master loads during the last state of the previous instruction

Fetch 0

Fetch 1

Fetch 2

The contents of the PC are loaded into MAR

PC contents are driven onto the Bus

Fetch 0

Fetch 1

Fetch 2

The contents of the PC are loaded into MAR

MAR and F1 masters load

Fetch 0

Fetch 1

Fetch 2

Fetch Instruction into MDR / Increment PC

Data is fetched from memory / PC is incremented

Fetch 0

Fetch 1

Fetch 2

Fetch Instruction into MDR / Increment PC

MDR, PC and F2 masters load

Fetch 0

Fetch 1

Fetch 2

Load the instruction into the IR

MDR contents are driven onto the Bus

Fetch 0

Fetch 1

Fetch 2

Load the instruction into the IR

IR master loads

Fetch 0

Fetch 1

Fetch 2

The LEA Instruction15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LEA 1110 PCoffset9DR

LEA0

selEAB1 <= ‘0’selEAB2 <= “10”selMAR <= ‘0’enaMARMDR <= IR[11:9] regWE

to Fetch0

• R[DR] PC + IR[8:0]

• Note that the PC Offset is always a 2’s complement (signed) value

The LDR Instruction15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

• MAR R[BaseR]+offset6• MDR Mem[MAR]• R[DR] MDR

LDR0

SR1 <= IR[8:6]selEAB1 <= ‘1’selEAB2 <= “01” selMAR <= ‘0’enaMARMldMAR

LDR1

LDR2enaMDRDR <= IR[11:9]regWE

to Fetch0

LDR 0110 offset6DR BaseR

selMDR <= ‘1’ldMDR

The LDI Instruction

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

• MAR PC + IR[8:0]• MDR Mem[MAR]• MAR MDR• MDR Mem[MAR]• R[DR] MDR

LDI0

LDI1

LDI2 enaMDRldMAR

to Fetch0

LDI 1010 PCoffset9DR

LDI4

LDI3

enaMDRDR <= IR[11:9]regWE

selMDR <= ‘1’ldMDR

selMDR <= ‘1’ldMDR

selEAB1 <= ‘0’selEAB2 <= “10”selMAR <= ‘0’enaMARMldMAR

The STR Instruction15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

• MAR R[BaseR]+offset• MDR R[SR]• Write memory

STR0

SR1 <= IR[8:6]selEAB1 <= ‘1’selEAB2 <= “01”

selMAR <= ‘0’enaMARMldMAR

STR1

STR2 memWE

SR1 <= IR[11:9]aluControl <= PASSenaALUselMDR <= ‘0’ldMDR

to Fetch0

STR 0111 offset6SR BaseR

The STI Instruction15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

• MAR PC + IR[8:0]• MDR M[MAR]• MAR MDR• MDR R[SR]• Write memory

enaMDRldMAR

STI 1011 PCoffset9SR

SR1 <= IR[11:9]aluControl <= PASSenaALUselMDR <= ‘0’ldMDR

memWE

selEAB1 <= ‘0’selEAB2 <= “10”selMAR <= ‘0’enaMARMldMAR

selMDR <= ‘1’ldMDR

STI0

STI1

STI2

to Fetch0

STI4

STI3

The JSRR Instruction

• Note: Same opcode as JSR! (determined by IR bit 11)

• R7 PC• PC R[BaseR]

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

enaPC DR <= “111”,regWE

JSRR 0100 0 00000000 BaseR

SR1 <= IR[8:6]selEAB1 <= ‘1’selEAB2 <= “00” selPC <= “01”ldPC

JSRR1

to Fetch0

JSRR0

FPGAs

Using ROM as Combinational Logic

A B C F

0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1

tt1

B

C

A

C

F

schem1

8 x 1ROM(LUT)

lut1

A

B

C

F

Mapping Larger Functions To ROMsA B C D F

0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 10 1 0 0 00 1 0 1 00 1 1 0 00 1 1 1 11 0 0 0 01 0 0 1 01 0 1 0 11 0 1 1 11 1 0 0 11 1 0 1 11 1 1 0 11 1 1 1 1

B

C

D

F

LUT(B+C)

LUT(CD)

B

C

D

LUTA’f1 + Af2

A

f1

f2

Very similar to how we decomposed functions to implement with MUX blocks…

Mapping a Gate Network to LUTs

3LUT #1

Mapping a Gate Network to 3LUTs

3LUT #2

3LUT #3

4LUT #1

Mapping Same Network to 4LUTs

4LUT #2

FPGAs – What Are They?

I/O Buffers

I/O Buffers

I/O

Buf

fers

I/O

Buf

fers

Programmable wiring areas

Programmable logic elements(LEs)

An FPGA is a Programmable Logic Device (PLD)It can be programmed to perform any function desired.

I/O Buffers communicatebetween FPGA andthe outside world

An FPGA Architecture (Island Style)R

ow w

ires

Column WiresLogic Elements

Each LE is configured to do a function

Wire intersections are programmed to either connect or not

Programmable Interconnect Junction

Row wire

Column wire

=1 ON

OFF=0

Connected

Unconnected

Example Problem

ZD0-D5 ND5 Z’

N’P

• Generate the N, Z, P status flags for a microprocessor

Example Problem

ZD0-D5 ND5 Z’

N’P

• Generate the N, Z, P status flags for a microprocessor

Will require 2 4LUTsCan be done with

wiring only or with 1 4LUT

Will require 1 4LUT

6

11

7

12

8

13

9

14

10

15

1 2 3 4 5

D0D1

D2

D3D4D5

Z

P

N

LUT #1: F1 = D0’• D1’• D2’• D3’LUT #7: F2 = F1•D4’•D5’ Z outputLUT #8: F3 = D5 N output LUT #9: F4 = Z’ • N’ P output

Configuring an FPGA

• An FPGA contains a configuration pin– Configuration bits are shifted into FPGA using

this pin, one bit per cycle– Configuration bits in FPGA linked into a long

shift register (SIPO)

• Examples on following slides conceptual– Commercial devices slightly different

Structure of a 3LUT

ConfigurationStorage

Bits(Flip Flops)

LUT Output

LUT Inputs

b0

b1

b2

b3

b4

b5

b6

b7

3

It’s just an 8:1 MUX

LUT inputs select which configbit is sent to LUT output

Programming LUT function setting configuration bits

How are the Configuration Bit Flip Flops Loaded?

D Q b70

1

CLKCONFIG

D Q b60

1

CLKCONFIG

……

A serial-in/parallel-out(SIPO) shift register

These are the configuration bitswhich the LUT selects from

Configuring the Programmable Interconnect

Row wire

Column wire

Configurationbit b

Arranged in a SIPOshift register also

Multipliers

0101

Add

Binary Shift/Add Multiplication

0 1 0 1

0 1

Full Adder

‘0000’

Multiplicand

Multiplier

Shift Register

Result Shift Register

0 0 0 0 - - - -

11000000

0101

1

Load

Binary Shift/Add Multiplication

0 1 0 1

Full Adder

‘0000’

Multiplicand

Multiplier

Shift Register

0 1 0 1 - - - -

1100

0101

0101

0 1

Result Shift Register

Shift

Binary Shift/Add Multiplication

0 1 0 1

Full Adder

‘0000’

Multiplicand

Multiplier

Shift Register

0 0 1 0 1 - - -

100-

0 1

Result Shift Register

0101

Add

Binary Shift/Add Multiplication

0 1 0 1

Full Adder

‘0000’

Multiplicand

Multiplier

Shift Register

0 0 1 0 1 - - -

100-0010

0111

10 1

Result Shift Register

Load

Binary Shift/Add Multiplication

0 1 0 1

Full Adder

‘0000’

Multiplicand

Multiplier

Shift Register

0 1 1 1 1 - - -

100-

0111

0111

0 1

Result Shift Register

Shift

Binary Shift/Add Multiplication

0 1 0 1

Full Adder

‘0000’

Multiplicand

Multiplier

Shift Register

0 0 1 1 1 1 - -

00--

0 1

Result Shift Register

0000

Add

Binary Shift/Add Multiplication

0 1 0 1

Full Adder

‘0000’

Multiplicand

Multiplier

Shift Register

0 0 1 1 1 1 - -

00--0011

0011

00 1

Result Shift Register

Load

Binary Shift/Add Multiplication

0 1 0 1

Full Adder

‘0000’

Multiplicand

Multiplier

Shift Register

0 0 1 1 1 1 - -

00--

0011

0011

0 1

Result Shift Register

Shift

Binary Shift/Add Multiplication

0 1 0 1

Full Adder

‘0000’

Multiplicand

Multiplier

Shift Register

0 0 0 1 1 1 1 -

0---

0 1

Result Shift Register

0000

Add

Binary Shift/Add Multiplication

0 1 0 1

Full Adder

‘0000’

Multiplicand

Multiplier

Shift Register

0 0 0 1 1 1 1 -

0---0001

0001

00 1

Result Shift Register

Load

Binary Shift/Add Multiplication

0 1 0 1

Full Adder

‘0000’

Multiplicand

Multiplier

Shift Register

0 0 0 1 1 1 1 -

0---

0001

0001

0 1

Result Shift Register

Shift

Binary Shift/Add Multiplication

0 1 0 1

Full Adder

‘0000’

Multiplicand

Multiplier

Shift Register

0 0 0 0 1 1 1 1

----

0 1

Result Shift Register

Debouncer

Draw a State Graph

S2

S3

noisy

noisy’

noisy’

noisy•timerDone’

noisy

clrTimer

noisy•timerDone

debouncedclrTimer

noisy’

S0

noisy’•timerDone’

noisy’•timerDone

noisy

debounced S1

An Improved State Graph

S1

noisy’/clrTimer

noisy/clrTimer

noisy•timerDone

debounced

S0

noisy’•timerDone

noisy’•timerDone’

As mentioned, Mealymachines often requirefewer states…

Looks like the FSMcan be implementedwith just a single FFDo you see why there is no

need for a reset input?noisy•timerDone’

Basic Operation of N and P Type FETs

S

D

G = Gnd

S

D

N-Type FET

S

D

G = Vcc

S

D

P-Type FET

S

D

G = Vcc

S

D

S

D

G = Gnd

S

D

Logic Gates Built from FETs

Logic Gate Implementation UsingField Effect Transistors

P

I O P

P

I1 I2

O

P PI2

I1O

I1

I2

O

I1

I2

OI O