lec 11 sequential logic circuits (1) (1)
TRANSCRIPT
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CMOS Digital Integrated Circuits
Lec 11
CMOS Digital Integrated Circuits1
Sequential CMOS LogicCircuits
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Sequential Logic
OutIn
Memory
Combinational
Logic
circuit
Sequential
CMOS Digital Integrated Circuits2
The output is determined byCurrent inputs
Previous inputs
Output =f(In, Previous In)
The regenerative behavior of sequential circuits is due to either adirect or an indirect feedback connection between the output andinput
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Critical Components of Sequential Circuits
Basic Regenerative Circuits Categories of Basic Regenerative Circuits
1. Bistable Circuits: Two stable states or operation modes, each of
them can be attained under certain input and output conditions. The
most widely used and the most important class which is used forthe basic latch, flip-flop circuits, registers, and memory elements.
2. Monostable Circuits: One stable state or operation mode
CMOS Digital Integrated Circuits3
circuit can preserve for a certain time period. The output oscillateswithout settling into a stable operating mode.
Sequential
Circuits
Bistable Monostable Astable
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Behavior of Bistable Elements (1/7)
Two Identical Cross-Coupled Inverter Circuit Voltage Transfer Curves
The output voltage of inverter (1) is equal to the input voltage of
inverter (2), and the output voltage of inverter (2) is equal to the
input voltage of inverter (1). A andB are stable points: If the circuit is initially operating at one
of them, it will preserve this state. The gain is smaller than unity.A
Vi2=Vo1stable
CMOS Digital Integrated Circuits4
Vi1
Vi2Vo2
Vo11
2
C
BVi1=Vo2
stable
unstable
Energy
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Behavior of Bistable Elements (3/7)
Analysis of the Output Voltages Let the initially operating point is at vo1=vo2=Vth, and assume that
the gate capacitance (Cg) of each inverter is much larger than thedrain capacitance (Cd).
The drain current of each inverter isequal to the gate current of the other
inverter.
ig1 = id2 =gmvg2
vg1 1
2vg2
ig1 id1
id2 ig2
CMOS Digital Integrated Circuits6
ig2 = id1 =gmvg1gm is the small-signal transconductance of the inverter.
The gate voltages can be expressed by gate charges, q1 and q2
vg1 = q1/ Cg
vg2 = q2/ Cg Also the small-signal gate currents can be expressed as
ig1 = Cg dvg1/dt
ig2 = Cg dvg2/dt
.
(Eq. B)
(Eq. C)
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Behavior of Bistable Elements (4/7)
Analysis of the Output Voltages Combine Eq. A and C, we have
Replace the gate voltages by Eq. B, we obtain
vg11
2vg2
ig1 id1
id2 ig21
2
1
2g gm
g
gm
g
g
v
v
dg v C
d t
d vg C
d t
=
=
CMOS Digital Integrated Circuits7
The above equations can be simplified to
1
2
2
1
m
g
m
g
g dqdtC
g dq
dtC
q
q
=
=
;1
0120
1
2
2
2
1
2
2
1
1g
Cqq
C
g
dt
qd
dt
qd
g
Cq
C
g
m
g
g
m
m
g
g
m ==
==
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Behavior of Bistable Elements (5/7)
Analysis of the Output Voltages
Therefore,
where q1(0) = Cgvg1(0) Replace the gate charge of both inverters with the corresponding
output voltages variables, we have
( ) ( ) ( )
eett qqqq
tq
00
2
)0(0
2
)0(0 '
101
'
101
1
++
=
tt ''0 fort >>
0
CMOS Digital Integrated Circuits8
For large values oft, the above equations can be approximated as
( ) ( ) ( )
ee
eet
oot
ooo
oooo
o
vvvvtv
tv
00
00
2
)0(0
2
)0(0
22'
101'
1011
2
++
=
+=
( ) ( )( )
( ) ( )( )e
et
ooo
t
ooo
vvtv
vvtv
0
0
)0(0
2
1
)0(02
1
'2022
'1011
+
+
0 fort >>0
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Behavior of Bistable Elements (6/7)
Analysis of the Output Voltages Depending on the polarity of the initial small perturbationsdvo1(0)
anddvo1(0), the vo1 and vo2 will diverge from their initial values of
Vth to either VOL and VOH.
The polarity ofdvo1 must always be opposite to that ofdvo2,because of the charge-conservation principle. Therefore, vo1 and
vo2 always diverge into opposite directions.vo2
CMOS Digital Integrated Circuits9
vo1: Vth VOHor VOL
vo2: Vth
VOL or VOH
VOH
VOH
VOLVOL
Vth
vo1Vth
unstable
Phase-plane Representation
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Behavior of Bistable Elements (7/7)
Analysis of the Output Voltages As a bistable circuit settles from unstable operating point to its
stable point, a signal travels around 2 INV loop n times.
1
2
Loop
vo1
vo2
vo1(t)/vo1(0)et/0000
CMOS Digital Integrated Circuits10
ur ng n erva = , e s gna rave s aroun e oop n mes
AneT/0
t
VOH
VOL
Vthvo1
vo2
An
loop 1 loop 2 loop n
A1
A2
T
et/0
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Naming Conventions
A latch is level sensitive
A register is edge-triggered
There are many different naming conventions For instance, many books call edge-triggered elements flip-flops
CMOS Digital Integrated Circuits11
Digital Integrated Circuits2nd
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Latch versus Register
Latch
stores data when
clock is low
D Q D Q
Register
stores data when
clock rises
CMOS Digital Integrated Circuits12
Clk Clk
Clk Clk
D D
Q Q
Digital Integrated Circuits2nd
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Latches
In Out
Positive Latch
CLK
DG
Q In Out
Negative Latch
CLK
DG
Q
CMOS Digital Integrated Circuits13
clk
In
Out
Out
stable
Out
follows In
clk
In
Out
Out
stable
Out
follows In
Digital Integrated Circuits2nd
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SR Latch Circuit
The two cross-coupled inverters can perform a simple memory
function ofholding its state. However, the two-inverter circuit
alone has no provision for allowing its state to be changed
externally from one stable operating point to other.
In order to allow such a change of state, we need toadd simple
switches which can be used to force or trigger the circuit from one
operating point to the other.
CMOS Digital Integrated Circuits14
S
R Q
Q
NOR-based
SR Latch
S
R Q
Q
Schematic Diagram of SR Latch
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SR Latch Circuit (Cont.)
The below circuit shows the simple CMOS SR latch which
consists of two triggering inputs, S (set) andR (reset).
The SR Latch consists of two CMOS NOR2 gates. One of the
input terminals of each NOR gate is used to cross-couple to the
output of the other NOR gate. The second input enables triggering
of the circuit.
VDDVDD
CMOS Digital Integrated Circuits15
RS M1 M2 M3 M4
Q Q
M5
M6
M7
M8 basic cross
coupled inverter
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SR Latch Circuit
Truth Table
Set:S=1,R=0 Qn+1=1, Qn+1=0. The SR latch will beset
regardless of its previous state.
Reset:S=0,R=1 Qn+1=0, Qn+1=1. The SR latch will bereset
regardless of its previous state.
Hold:S=0,R=0 Qn+1=Qn, Qn+1=Qn. The previous states will be
held.
Not Allow:S=1,R=1 Qn+1=0, Qn+1=0
S
R Q
Q
CMOS Digital Integrated Circuits16
S R Qn+1 Qn+1 Operation
0 0 Qn Qn Hold
1 0 1 0 Set
0 1 0 1 Reset
1 1 0 0 Not Allowed
Truth Table of NOR-based (active high inputs) SR latch
active high
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SR Latch Circuit
Operation Modes of the Transistors
S R Qn+1 Qn+1 Operation
NMOS PMOS
VOH VOL VOH VOL M1, M2 on;M3,M4 off M7, M8 on;M5,M6off
VOL VOH VOL VOH M1, M2 off;M3,M4 on M7, M8 off;M5,M6on
VOL VOL VOH VOL M1, M4 off;M2, on M6, M8 on;M7, on
VOL VOL VOL VOH M1 M4 off;M3, on M6 M8 on;M5, on
1111 11111111 11112222 22223333 333311112222
1111 11111111 11112222 2222333333331111 2222
CMOS Digital Integrated Circuits17
VDD
RS M1
VDD
M2 M3 M4
Q QM5
M6
M7
M8 basic cross
coupled inverter
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SR Latch Circuit
Transient Analysis
For transient analysis, we have to consider an event which results
in a state change, reset set, or set reset
In either case, we note that both of the output nodes undergo
simultaneous voltage transitions. One is from logic-low to logic-high, and the other is from logic-high to logic-low.
The exact transient analysis need to solve two coupled differential
CMOS Digital Integrated Circuits18
.
For simplicity, we can assume that thetwo events take place insequencerather than simultaneously. (overestimation)
Switching Time Calculation
The total lumped capacitance at each output node can be
approximated as
CQ =Cgb,2+Cgb,5+Cdb,3+Cdb,4+Cdb,7+Csb,7+Cdb,8
CQ =Cgb,3+Cgb,7+Cdb,1+Cdb,2+Cdb,5+Csb,5+Cdb,6
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SR Latch Circuit
Transient Analysis (Cont.) Assuming that the latch is initially reset and that a set operation is
being performed, the rise time associated with node Q can be
estimated as
rise,Q(SR-latch) = fall,Q(NOR2) + riseQ(NOR2)
VDDVDD
CMOS Digital Integrated Circuits19
RS M1 M2 M3 M4
QQ
CQ
CQ
Q M2 on
rise,Q(NOR2)
01 10
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SR Latch Circuit
NAND-based (active low signals)
Q Q
VDD VDD
basic crosscoupled inverter
CMOS Digital Integrated Circuits20
S R
S R Qn+1 Qn+1 Operation
0 0 1 1 Not Allowed0 1 1 0 Set
1 0 0 1 Reset
1 1 Qn Qn Hold
active low
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Clocked Latch and Flip-Flop Circuits
The previous SR latch circuits areasynchronous sequential
circuits.
Thesynchronization can be introduced through clock CK, which
the outputs will respond to the input levels only during the active
period of a clock pulse.
Clocked SR Latch
SQ
SR Latch
CMOS Digital Integrated Circuits21
When CK=0, S,R have no influence of Q, QHold
Set State: CK=1, S=1,R=0 Qn+1=1, Qn+1=0
Reset State: CK=1, S=0,R=1 Qn+1=0, Qn+1=1
Not Allowed: CK=1, S=1,R=1
R
Q
CK
Active High
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AOI-based Implementation of
Clocked NOR-based SR Latch
VDDVDDCK
NOR SR
Latch
The AOI-based implementation need a very small transistor count,compared with the circuit consisting of two AND2 and two NOR2 gates
NOR-based: 20 transistors
AOI-based: 12 transistors
CMOS Digital Integrated Circuits22
RS M1 M2 M3 M4
QQ
M1 CKCK
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Operation of Clocked SR Latch
Operation CK S R Qn+1 Qn+1
Hold 0 X X Qn Qn
Set 1 1 0 1 0
Reset 1 0 1 0 1
Not Allow 1 1 1 1 1
CMOS Digital Integrated Circuits23
When Glitch ON S (orR) occurs during CK= 1, Q is set (or reset).
Level Sensitive: When CK= 1, any changes in S,R will effect Q.
R
S
Q
Glitch
Glitch Free Q
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Clocked NAND-based SR Latch
S
RQ
Q
CK
CMOS Digital Integrated Circuits24
When CK= 1, S andR have no influence of Q and QHold
Operation CK S R Qn+1 Qn+1
Hold 1 X X Qn Qn
Set 0 0 1 1 0
Reset 0 1 0 0 1
Not Allow 0 0 0 0 0
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NAND
SR Latch
VDDVDDCK
OAI-based Implementation of Clocked NAND-based SR Latch
The OAI-based implementation need a very small transistor count,compared with the circuit consisting of two OR2 and two NAND2 gates
CMOS Digital Integrated Circuits25
R
S M1
M2
M3
M4QQ
CKSynchronous operationLevel sensitive
Not allowed input sequence
(any changes in S andR as CK=1 will be reflected onto outputs)
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Clocked JK Latch
J K Qn Qn S R Qn+1 Qn+1 Operation
CK = 0 hold
CK = 1 active
J
K Q
Q
CK
NAND SR
S
RNo not-allowedinput combination
CMOS Digital Integrated Circuits26
00
00
01
10
11
11
01
10
HoldHold
0
0
1
1
0
1
1
0
1
1
1
0
0
0
1
1
Reset
Reset
11
00
01
10
01
11
11
00
SetSet
1
1
1
1
0
1
1
0
0
1
1
0
1
0
0
1
Toggle
Toggle
CK = 1
OSC
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AOI-based Implementation of
NOR-based Clocked JK Latch (1/2)
J
K Q
Q
CK
NAND SRS
R
NOR SRS
CMOS Digital Integrated Circuits27
J
K Q
Q
CK
S
R
K Q
Q
CKR
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AOI-based Implementation of
NOR-based Clocked JK Latch (2/2)
VDDVDDCK
The AOI-based implementation has a very small transistor count,
and a more compact circuit compared to all-NAND realization.
CMOS Digital Integrated Circuits28
K
CKCK
J
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JK Toggle Switch
J=K=1
J=1 JK
LatchCK
K=1
Q
Q
CK T1
CMOS Digital Integrated Circuits29
IffJKP > T1 (awkward to implement)
Output Q changes only once per clock period No not allowed input
Timing issues
Level sensitive
Q
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Master-Slave Flip-Flop
NAND
SR
J
K
CK
NAND
SR
Qm
Qm
Qs
Qs
CK
S S
R R
CMOS Digital Integrated Circuits30
Two cascaded latches operating on opposite clock phases insuresthat the flip-flop isnever transparent; i.e., a change occurring inthe primary inputs is never reflected directly to the outputs.
Eliminates oscillations whenJ = K =1.
Still level sensitive.
Number of transistors:
NAND-based: 36
AOI-based: 28
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D-Latch
D-latch is obtained by modifying the clocked NOR-based SR latch
circuit. The circuit has a single inputD which is connected to S
input, andD is also inverted and connected toR input.
The applications of D-latch are primarily for temporary storage ofdata or as a delay element.
D
SR Latch
CMOS Digital Integrated Circuits31
IfCK=1Qn+1= D
IfCK=0Qn+1= Qn
Q
CK
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D-Latch (Cont.)
D-latch is a mux-based latch which can be represented as
1 Q 0 Q
CMOS Digital Integrated Circuits32
Negative latch
(transparent whenCK= 0)
Positive latch
(transparent when CK= 1)
CK CK
Q=CKQ+CKIn Q=CKQ+CKIn
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D-Latch
Implementation with Transmission Gates
Transmission gate D-latch: Use switch-like properties of
transmission gates
CK
D
Q
CK
Q
CMOS Digital Integrated Circuits33
Operation: For CK= 1, Qn+1=D and Qn+1=D. A bit is loaded. ForCK = 0, Qn+1=Qn and Qn+1=Qn. Thus, a bit is stored.
What about changes inD relative to changes in CK?
Setup time andHold time relative to CK: 10
Device counts for TG-based reduced from AOI/OAI
AOI-based: 14
TG-based: 8 (plus 2 to invert clock)
D-Latch
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D-Latch
Implementation with Three-State
Similar to the TG-based implementation, except as if connection
between n and pFETs in a driving inverter and input side of a driven
D Q
CK = 1
Q
D Q
CK = 0
Q
CMOS Digital Integrated Circuits34
transmission gate is served. Require addition of inverter at input first.
CK
CK
CK
CKQ Q
D
VDD
VDD
VDD
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D-Latch
Implementation with Three-State (Cont.)
The first three-state inverter acts as the input switch. Accept the input
signal when CKis high, the second three-state inverter is at its high
impedance state, and Q = D.
The first three-state inverter is inactive when theCKgoes low, and thesecond three-state inverter completes the two-inverter loop, which
preserves its state (Qn+1= Qn)
CMOS Digital Integrated Circuits35
CK
CK
CK
CKQ QD
VDD
VDD
VDD
D-Latch
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D Latch
Setup Time and Hold Time
Q
D
CKtsetup
thold
tclock-to-
CMOS Digital Integrated Circuits36
Tsetup: time before the negative-CK edge theD-input has to be stable
The setup time is the delay between the data input of the register and the
storage element. As the data takes a finite time to travel to the storage
point, the clock cannot be changed until the correct data value appears.
Thold: time after the negative-CK edgeD-input has to remain stable The hold time relates to the delay between the clock input to the register
and the storage element. That is, the data has to be held for this period
while the clock travels to the point of storage.
Tclock-to-Q: Delay from the negative-CK edge to new value of Q output
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Edge Triggered Master-Slave Operation
Negative D-Latch
CK
D
QCK
D
QCK=0
D
QCK=1
CMOS Digital Integrated Circuits37
CK
CK
CK
D
Q
CK
D
QCK=1
D
QCK=0
Positive D-Latch
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Positive Edge Triggered Master-Slave Flip-Flop
CK
CKD
QmCK
CK
CK
Qs
CK
Qm
Master Slave
Qs
negative level-sensitive positive level-sensitive
CMOS Digital Integrated Circuits38
D
or =
1.CK=0: Master Qm tracks currentD;Slave Qs=previousD sample
2.CK=01: Master stores Qm =D(new D
sample).
3.CK=1:Master passes Qm =D to Slaveoutput Qs
4.CK=10: Slave locks in newD, and
Master Qm begins trackingD.
Qs
Qs
Qm
QmD
For CK=1
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DFF Transient Response
CMOS Digital Integrated Circuits39
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DFF Transient Response with Setup Time Violation
CMOS Digital Integrated Circuits40
D Fli Fl
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D Flip-Flop
Clock Skew Issues
In a TG or three-state implemented flip-flop, if CKand CKchanges
are skewed (misaligned) enough, then a change in Master can
immediately propagate into Slave violating the master-slave (edge-
triggered) concept. If global or shared drivers used, can use the following to reduce skew:
CMOS Digital Integrated Circuits41
For the global case, skew can also arise due to interconnect delay.
CK IN 0
CK
CK
1 Adjust devices sizes to matchinverter delay
Non-Bistable Sequential
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Non-Bistable Sequential
Schmitt Trigger
The Schmitt trigger has aninverter-like voltage transfer
characteristic, but withtwodifferent threshold voltages for
increasing and decreasing input signals.
In Out
Vout VOH
CMOS Digital Integrated Circuits42
VTC with hysteresis
Restores signal slopes
Vin
VOL
VM VM+
(positive feedback)
Schmitt Trigger Application
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Schmitt Trigger Application
Noise SuppressionVin
VM
VM+
Vout
CMOS Digital Integrated Circuits43
t0 t t0+ tp t
Digital Integrated Circuits2ndVin
Vout
VOH
VOL
VM
VM+
Schmitt Trigger
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gg
The Circuit(1)
Vin
M2
VDD
X Vout
M4
CMOS Digital Integrated Circuits44
Moves switching threshold
of the first inverter
M1 M3
S h i T i Si l d VTC
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Schmitt Trigger Simulated VTC
2.5
VM1
2.0
1.5
2.5
2.0
1.5
kM1/(kM2+kM4)
out
out
CMOS Digital Integrated Circuits45
Digital Integrated Circuits2nd
VM2
Vin (V)
Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of the
PMOS deviceM4. The width is k* 0.5 m.mmmm
1.0
0.5
0.00.0 0.5 1.0 1.5 2.0 2.5
k = 2k = 3
k = 4
k = 1
Vin (V)
1.0
0.5
0.00.0 0.5 1.0 1.5 2.0 2.5
(kM1+kM3)/kM2
Schmitt Trigger
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Schmitt Trigger
The Circuit(2)
VDD
M3
M4
M6
CMOS Digital Integrated Circuits46
VDD
OutIn
M1
M5
M2
X
Digital Integrated Circuits2nd
M lti ib t Ci it
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Multivibrator Circuits
Bistable Multivibrator
flip-flop, Schmitt Trigger
S
R
T
CMOS Digital Integrated Circuits47
Monostable Multivibrator
Astable Multivibrator
one-shot
oscillator
Digital Integrated Circuits2nd
T iti T i d M t bl
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Transition-Triggered Monostable
DELAYIn
Out
CMOS Digital Integrated Circuits48
td td
Digital Integrated Circuits2nd
Astable Multivibrators (Oscillators)
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Astable Multivibrators (Oscillators)
0 1 2 N-1
Ring Oscillator
V V V3.0
CMOS Digital Integrated Circuits49
simulated response of 5-stage oscillator
0.0
0.0
0.5
1.0
1.5
2.0
2.5
20.50.5
time (ns)
Volts
1.0 1.5
Digital Integrated Circuits2nd