OS Structure

CSC501 Operating Systems Principles

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Announcements

q TA’s office hour has changedQ Thursday 1:30pm – 3:00pm, MRC-409CQ Or email: awang@ncsu.edu

q From department: No audit allowed

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mailto:awang@ncsu.edu

Last Lecture

q Introduction to OSQ AbstractionQ Separation of mechanisms and policies

q Today:Q Computer architectureQ OS structure

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Basic Computer Architecture

q A (partial) list of hardware:Q Central processing unit (CPU)Q Memory management unit (MMU)Q Persistent storage (e.g., Disk)Q Peripheral devices (e.g., NIC)

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Basic Computer Architecture

the single core

Basic Computer Architecture

q A (partial) list of hardware:Q Central processing unit (CPU)Q Memory management unit (MMU)Q Persistent storage (e.g., Disk)Q Peripheral devices (e.g., NIC)

q Recent developmentQ Performance: Multiprocessor, MulticoreQ Security: TPM

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Multicore Architecture

q Replicate multiple processor cores on a single die

Core 1 Core 2 Core 3 Core 4

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Why Multicore ?q PerformanceQ Difficult to make single-core clock frequencies even

higher Q Parallelism: Many new applications are multithreaded

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The Memory Hierarchyq How many layersQ CPU Registers -> CPU Cache (L1, L2, L3) ->

Memory -> Diskq Why?Q Motivated by the mismatch between processor

and memory speedQ Motivated by the fact that most programs have a

high degree of locality in their accessesv Spatial locality: accessing things nearby recent accessesv Temporary locality: reusing an item previously accessed

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The Memory Hierarchyq Comparison between different types of memoryQ Metric: Size, Speed, Cost

size:speed:

$/Mbyte:

32 - 256 B2 ns

Register Cache Memory32KB - 4MB

4 ns$100/MB

512 MB60 ns

$1.50/MB

20 GB8 ms

$0.05/MB

larger, slower, cheaper

HDD

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The Memory Hierarchy -- Multicore

q Single-core chip:Q L1 cache, L2 cache, …

q Multi-core chips:Q L1 caches private?Q L2 caches private?Q Memory private?

memory

L2 cache

L1 cache L1 cacheC O

R E

1

C O R

E 0

L1 cache is privateExample: Dual-core Intel Xeon processors 2

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The Memory Hierarchy -- Multicore

memory

L2 cache

L1 cache L1 cacheC O

R E

1

C O R

E 0

L2 cache

Both L1 and L2 are private

Examples: AMD Opteron, AMD Athlon, Intel Pentium D

memory

L2 cache

L1 cache L1 cacheC O

R E

1

C O R

E 0

L2 cache

L3 cache L3 cache

A design with L3 caches

Example: Intel Itanium 212

Private vs shared caches

q Advantages/disadvantages?

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Private vs shared caches

q Advantages of private:Q They are closer to core, so faster accessQ Reduces contention

q Advantages of shared:Q Threads on different cores can share the same

cache dataQ More cache space available

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Question: In multicore environment

with private L1/L2 cache, is there any serious issue we

should address?

memory

L2 cache

L1 cache L1 cacheC O

R E

1

C O R

E 0

L2 cache

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The cache coherence problemq Since we have private caches, how to keep the

data consistent across cores?Q Each core should perceive the memory as a

monolithic array, shared by all the cores

Suppose variable x initially contains 15213

Core 1 Core 2 Core 3 Core 4

One or more levels of

cache

One or more levels of

cache

One or more levels of

cache

One or more levels of

cache

Main memoryx=15213

multi-core chip

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Core 1 reads x

Core 1 Core 2 Core 3 Core 4

One or more levels of

cachex=15213

One or more levels of

cache

One or more levels of

cache

One or more levels of

cache

Main memoryx=15213

multi-core chip

Core 2 reads x

Core 1 Core 2 Core 3 Core 4

One or more levels of

cachex=15213

One or more levels of

cachex=15213

One or more levels of

cache

One or more levels of

cache

Main memoryx=15213

multi-core chip

Core 1 writes to x, setting it to 21660

Core 1 Core 2 Core 3 Core 4

One or more levels of

cachex=21660

One or more levels of

cachex=15213

One or more levels of

cache

One or more levels of

cache

Main memoryx=21660

multi-core chipassuming

write-through caches

Core 2 attempts to read x… gets a stale copy

Core 1 Core 2 Core 3 Core 4

One or more levels of

cachex=21660

One or more levels of

cachex=15213

One or more levels of

cache

One or more levels of

cache

Main memoryx=21660

multi-core chip

Any solutions?

Solutions for cache coherenceq This is a general problem with multiprocessors,

not limited just to multi-core

q There exist many solution algorithms, coherence protocols, etc.

q A simple solutionQ Invalidation-based protocol with snooping

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Invalidation protocol with snooping

q Invalidation:If a core writes to a data item, all other copies of this data item in other caches are invalidated

q Snooping: All cores continuously “snoop” (monitor) the bus connecting the cores.

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Outline

q Computer architectureq OS structureQ MonolithicQ LayeredQ Microkernel

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Monolithic

user applications

OS: procs+data

hardware

user/kernel boundary

Why? Why?

Layer

user

filesysteminter-machine net.

device mgr + driversreal-time clock mgr

IPCprocess coordprocess mgr

memory mgr (low)

hardware

user/kernel boundary

memory mgr (high)

Microkernel

hardware

kernel

FS memsvrprocsvr ……

userapp

userapp

userapp

user/kernelboundary?

Comparison

Performance Extensibility Reliability Scalability

Monolithic

Layered

Microkernel

Best WorstIn between

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Virtual Machines (VMs)

q Old concept which is heavily revived todayQ the real hardware is "cloned" in several identical VMsQ OS functionality built on top of the VM

Memorynic

nicNICdiskCPU

ConsoleOS

GuestOS

GuestOS

GuestOS

GuestOS

Scheduler MemoryMgmtSCSIDriver

EthernetDriver

VMM

Lab 0

q Lab 0 is available on the webQ Due 1/20 at 11:45pm sharpQ Electronic submission (late assignments

automatically rejected)

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Next Lecture

q Processes, threads, and synchronization

q We will start class on time, so please don’t come late!

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