lec9_retiming

8/7/2019 lec9_retiming

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Spring 08, Feb 28Spring 08, Feb 28 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 11

ELEC 7770ELEC 7770

Advanced VLSI DesignAdvanced VLSI Design

Spring 2008Spring 2008

RetimingRetimingVishwani D. AgrawalVishwani D. Agrawal

James J. Danaher ProfessorJames J. Danaher Professor

ECE Department, Auburn UniversityECE Department, Auburn UniversityAuburn, AL 36849Auburn, AL 36849

[email protected]@eng.auburn.edu

http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.htmlhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.html


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RetimingRetiming

Retiming is a functionRetiming is a function--preserving transformationpreserving transformation

of a synchronous sequential circuit.of a synchronous sequential circuit.

FlipFlip--flops are moved according to specific rules.flops are moved according to specific rules.

Original references:Original references: C. E. Leiserson, F. Rose and J. B. Saxe, OptimizingC. E. Leiserson, F. Rose and J. B. Saxe, Optimizing

Synchronous Circuits by Retiming,Synchronous Circuits by Retiming, Proc. 3Proc. 3rdrdCaltechCaltech

Conf. on VLSIConf. on VLSI, 1983, pp. 87, 1983, pp. 87--116.116.

C. E. Leiserson and J. B. Saxe, RetimingC. E. Leiserson and J. B. Saxe, RetimingSynchronous Circuitry,Synchronous Circuitry, AlgorithmicaAlgorithmica, vol. 6, pp. 5, vol. 6, pp. 5--35,35,

1991.1991.


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A Trivial Example: Reduced HardwareA Trivial Example: Reduced Hardware

FF

FF

FF


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Example 2: Faster ClockExample 2: Faster Clock

FF

FF


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Example 3: Reduced FlipExample 3: Reduced Flip--FlopsFlops

FF

FF

FF


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Applications of RetimingApplications of Retiming

Performance optimizationPerformance optimization

Area optimizationArea optimization

Power optimizationPower optimization

Testability enhancementTestability enhancement

FPGA optimizationFPGA optimization


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Fundamental Operation of RetimingFundamental Operation of Retiming

A retiming move in a circuit is caused by movingA retiming move in a circuit is caused by moving

all of the memory elements at the input of aall of the memory elements at the input of a

combinational block to all of its outputs, or vicecombinational block to all of its outputs, or vice--

versa.versa.

Combinational

logicFF

FF

Combinational

logic FF


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A Correlator CircuitA Correlator Circuit

+ + +

= = = =

host

Adder

delay = 7

Comparator

delay = 3Flip-flop

PI

PO

a1 a2 a3 a4


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Graph ModelGraph Model

7 7 7

3 3 3 3

0

0

0 0

0

0 0 0

1

1 1 1

Vertex, vi, combinational, delay = d(vi), assumed unchanged by retiming

d(host) = 0

Edge, e(vi,vj) or eij, weight wij = number of flip-flops between vi and vj

h

a b c d

efg


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Path Delay and Path WeightPath Delay and Path Weight

A set of connected nodes specify a path. A pathA set of connected nodes specify a path. A pathdoes not traverse through the host node.does not traverse through the host node.

Path delay =Path delay = d(vi) = combinational delay of path d(vi) = combinational delay of path

Path weight = wij = clock delay of pathPath weight = wij = clock delay of path Retiming of a node i is denoted by an integer riRetiming of a node i is denoted by an integer ri

It represents the number of registers moved across,It represents the number of registers moved across,initially ri = 0initially ri = 0

Register moved from output to input, ri ri + 1Register moved from output to input, ri ri + 1 Register moved from input to output, ri riRegister moved from input to output, ri ri 11

After retiming, edge weight wij = wij + rjAfter retiming, edge weight wij = wij + rj riri


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Example of Node RetimingExample of Node Retiming

3 3 3 33 3

d(vi) = 12, wij = 0 d(vi) = 12, wij = 0

3 3 3 33 3

d(vi) = 12, wij = 2 d(vi) = 12, wij = 2

r1 = 0 r2 = 0 r3 = 0 r4 = 0 r5 = 0 r6 =0

r1 = 0 r2 = -1 r3 = 0 r4 = 0 r5 = 1 r6 =0


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Legal RetimingLegal Retiming

Retiming is legal if the retimed circuit has noRetiming is legal if the retimed circuit has no

negative weights.negative weights.

A legally retimed circuit is functionally equivalentA legally retimed circuit is functionally equivalent

to the original circuitto the original circuit proof by Leiserson andproof by Leiserson andSaxe (1991)Saxe (1991)

Retiming is the most general method forRetiming is the most general method for

changing the register count and position withoutchanging the register count and position withoutknowing the functions of vertices.knowing the functions of vertices.


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ExampleExample

FF

a

b

c

x

d

c

host x

10

0

0


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Example: Illegal RetimingExample: Illegal Retiming

c

host x

10

0

0

0

0

0

Retiming vector = {0, 0, 0}

c

host x

1 00

0 1

0 1

0

0

0 1


FF

a

b

c

x

d


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Example: Legal RetimingExample: Legal Retiming

c

host x

10

0

0

0

0

0


c

host x

1 0

0

0

0 1

0

0

0 1


FFa

b

c

x

d

FF


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Correlator CircuitCorrelator Circuit

7 7 7

3 3 3 3

0

0

0 0

0

0 0 0

1

1 1 1a b c d

efg

h

Initial retiming vector = {0,0,0,0,0,0,0,0}

Critical path delay = 24

rh=0

ra=0 rb=0 rc=0rd=0

re=0rf=0rg=0


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Retimed Correlator CircuitRetimed Correlator Circuit

7 7 7

3 3 3 3

0

0

01 01

0

01 0 0

10

1

10 1

a b c d

efg

h

retiming vector = {-1,-1,-2,-2,-2,-1,0,0}

Critical path delay = 13

rh=0

ra= -1 rb= -1 rc= -2rd= -2

re= -2rf= -1rg=0


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Retiming TheoremRetiming Theorem

Given a network G(V, E, W) and a cycle time T,Given a network G(V, E, W) and a cycle time T,

(r1, . . . ) is a feasible retiming if and only if:(r1, . . . ) is a feasible retiming if and only if:

1.1. riri rjrj wij wij for all edges (vi,vj)for all edges (vi,vj) EE

2.2. riri rj W(vi,vj)rj W(vi,vj) 11 for all nodefor all node--pairs vi, vj such thatpairs vi, vj such thatD(vi,vj) > TD(vi,vj) > T

Where,Where,

W(vi,vj):W(vi,vj): is the minimum weight for all pathsis the minimum weight for all paths

between vi and vjbetween vi and vjD(vi,vj):D(vi,vj): is the maximum delay among allis the maximum delay among all

minimum weight paths between vi and vjminimum weight paths between vi and vj


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Proof of Condition 1Proof of Condition 1

We assume that the original network is legal, i.e., allWe assume that the original network is legal, i.e., all

edge weights are positive.edge weights are positive.

For an arbitrary edge (vi,vj)For an arbitrary edge (vi,vj) E:E:

riri rjrj wij or wij + rj wij or wij + rj riri 0, 0, means that after retiming the newmeans that after retiming the new

weight wij = wij + rjweight wij = wij + rj ri will be positive. Thus, condition 1ri will be positive. Thus, condition 1

ensures the legality of retiming.ensures the legality of retiming.


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Proof of Condition 2Proof of Condition 2

Given: d(vi) < T, for all i.Given: d(vi) < T, for all i.

Any retimed path whose combinational delay exceedsAny retimed path whose combinational delay exceeds

clock period, will have at least one flipclock period, will have at least one flip--flop.flop.

The above is the requirement for correct operation.The above is the requirement for correct operation.

i j

Original weight, Wij

Retimed weight, Wij = Wij + rj ri 1

Path (i,j), D(i,j) > T

Wij flip-flopsrj flip-flopsri flip-flops


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ReferencesReferences

Two papers by LeisersonTwo papers by Leiserson et alet al. (see slide 2).. (see slide 2).

G. De Micheli,G. De Micheli, Synthesis and Optimization ofSynthesis and Optimization of

Digital CircuitsDigital Circuits, New York: McGraw, New York: McGraw--Hill, 1994.Hill, 1994.

N. Maheshwari and S. S. Sapatnekar,N. Maheshwari and S. S. Sapatnekar, TimingTiming

Analysis and Optimization of Sequential CircuitsAnalysis and Optimization of Sequential Circuits,,

Boston: Springer, 1999.Boston: Springer, 1999.

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