lecture 1: circuits & layout. cmos vlsi design 4th ed. 1: circuits & layout2 outline a...
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Lecture 1: Circuits & Layout
CMOS VLSI Design 4th Ed.1: Circuits & Layout 2
Outline A Brief History CMOS Gate Design Pass Transistors CMOS Latches & Flip-Flops Standard Cell Layouts Stick Diagrams
CMOS VLSI Design 4th Ed.
The First Computer
1: Circuits & Layout 3
The Babbage Difference Engine(1832)25.000 partscost: £17.470
CMOS VLSI Design 4th Ed.
ENIAC – The First Electronic Computer (1946)
1: Circuits & Layout 4
CMOS VLSI Design 4th Ed.
The Transistor Revolution
Fi
1: Circuits & Layout 5
First TransistorBell Labs 1948
CMOS VLSI Design 4th Ed.1: Circuits & Layout 6
A Brief History 1958: First integrated circuit
– Flip-flop using two transistors– Built by Jack Kilby at Texas
Instruments 2010
– Intel Core i7 processor • 2.3 billion transistors
– 64 Gb Flash memory • > 16 billion transistors
Courtesy Texas Instruments
[Trinh09]
© 2009 IEEE.
CMOS VLSI Design 4th Ed.
First Integrated Circuits
1: Circuits & Layout 7
Bipolar Logic1960’s
ECL 3-input NAND GateMotorola
CMOS VLSI Design 4th Ed.
Intel 4004 Microprocessor
1: Circuits & Layout 8
19711000 transistors1 MHz operation
CMOS VLSI Design 4th Ed.1: Circuits & Layout 9
Growth Rate
53% compound annual growth rate over 50 years– No other technology has grown so fast so long
Driven by miniaturization of transistors– Smaller is cheaper, faster, lower in power!– Revolutionary effects on society
[Moore65]
Electronics Magazine
CMOS VLSI Design 4th Ed.1: Circuits & Layout 10
Annual Sales >1019 transistors manufactured in 2008
– 1 billion for every human on the planet
CMOS VLSI Design 4th Ed.1: Circuits & Layout 11
Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large,
expensive, power-hungry, unreliable 1947: first point contact transistor
– John Bardeen and Walter Brattain at Bell Labs– See Crystal Fire
by Riordan, Hoddeson
AT&T Archives. Reprinted with
permission.
CMOS VLSI Design 4th Ed.1: Circuits & Layout 12
Transistor Types Bipolar transistors
– npn or pnp silicon structure– Small current into very thin base layer controls
large currents between emitter and collector– Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors– nMOS and pMOS MOSFETS– Voltage applied to insulated gate controls current
between source and drain– Low power allows very high integration
CMOS VLSI Design 4th Ed.1: Circuits & Layout 13
1970’s processes usually had only nMOS transistors– Inexpensive, but consume power while idle
1980s-present: CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit Proc
[Vadasz69]
© 1969 IEEE.
Intel Museum.
Reprinted with permission.
CMOS VLSI Design 4th Ed.
Moore’s Law In 1965, Gordon Moore noted that the number of
transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor
technology will double its effectiveness every 18 months
1: Circuits & Layout 14
CMOS VLSI Design 4th Ed.1: Circuits & Layout 15
Moore’s Law: Then 1965: Gordon Moore plotted transistor on each chip
– Fit straight line on semilog scale– Transistor counts have doubled every 26 months
Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates[Moore65]
Electronics Magazine
CMOS VLSI Design 4th Ed.1: Circuits & Layout 16
And Now…
CMOS VLSI Design 4th Ed.
Evolution in Complexity
1: Circuits & Layout 17
CMOS VLSI Design 4th Ed.1: Circuits & Layout 18
Feature Size
Minimum feature size shrinking 30% every 2-3 years
CMOS VLSI Design 4th Ed.
Die Size Growth
1: Circuits & Layout 19
CMOS VLSI Design 4th Ed.1: Circuits & Layout 20
Corollaries Many other factors grow exponentially
– Ex: clock frequency, processor performance
CMOS VLSI Design 4th Ed.
Power Dissipation
1: Circuits & Layout 21
CMOS VLSI Design 4th Ed.
22
Power density
400480088080
8085
8086
286386
486Pentium® proc
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Pow
er D
ensi
ty (
W/c
m2)
Hot Plate
NuclearReactor
RocketNozzle
Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp
Courtesy, Intel
CMOS VLSI Design 4th Ed.
23
Productivity Trends
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
2003
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2005
2007
2009
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
xxx
xxx
x
21%/Yr. compoundProductivity growth rate
x
58%/Yr. compoundedComplexity growth rate
10,000
1,000
100
10
1
0.1
0.01
0.001
Log
ic T
ran
sist
or p
er C
hip
(M)
0.01
0.1
1
10
100
1,000
10,000
100,000
Pro
du
ctiv
ity
(K)
Tra
ns.
/Sta
ff -
Mo.
Source: Sematech
Complexity outpaces design productivity
Com
ple
xity
Courtesy, ITRS Roadmap
CMOS VLSI Design 4th Ed.24
Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more
functions per chip; chip cost does not increase significantly
Cost of a function decreases by 2x But …
– How to design chips with more and more functions?– Design engineering population does not double every
two years… Hence, a need for more efficient design methods
– Exploit different levels of abstraction
CMOS VLSI Design 4th Ed.25
Design Metrics
How to evaluate performance of a digital circuit (gate, block, …)?– Cost– Reliability– Scalability– Speed (delay, operating frequency) – Power dissipation– Energy to perform a function
CMOS VLSI Design 4th Ed.26
Cost of Integrated Circuits
NRE (non-recurrent engineering) costs– design time and effort, mask generation– one-time cost factor
Recurrent costs– silicon processing, packaging, test– proportional to volume– proportional to chip area
CMOS VLSI Design 4th Ed.27
NRE Cost is Increasing
CMOS VLSI Design 4th Ed.28
Die Cost
Single die
Wafer
From http://www.amd.com
Going up to 12” (30cm)
CMOS VLSI Design 4th Ed.29
Cost per Transistor
0.00000010.0000001
0.0000010.000001
0.000010.00001
0.00010.0001
0.0010.001
0.010.01
0.10.111
19821982 19851985 19881988 19911991 19941994 19971997 20002000 20032003 20062006 20092009 20122012
cost: cost: ¢-per-¢-per-transistortransistor
Fabrication capital cost per transistor (Moore’s law)
CMOS VLSI Design 4th Ed.30
Yield%100
per wafer chips ofnumber Total
per wafer chips good of No.Y
yield Dieper wafer Dies
costWafer cost Die
area die2
diameterwafer
area die
diameter/2wafer per wafer Dies
2
CMOS VLSI Design 4th Ed.31
Defects
area dieareaunit per defects
1yield die
is approximately 3
4area) (die cost die f
CMOS VLSI Design 4th Ed.32
Some Examples (1994)Chip Metal
layersLine width
Wafer cost
Def./ cm2
Area mm2
Dies/wafe
r
Yield Die cost
386DX 2 0.90 $900 1.0 43 360 71% $4
486 DX2 3 0.80 $1200 1.0 81 181 54% $12
Power PC 601
4 0.80 $1700 1.3 121 115 28% $53
HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73
DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149
Super Sparc 3 0.70 $1700 1.6 256 48 13% $272
Pentium 3 0.80 $1500 1.5 296 40 9% $417
CMOS VLSI Design 4th Ed.1: Circuits & Layout 33
CMOS Gate Design Activity:
– Sketch a 4-input CMOS NOR gate
A
B
C
DY
CMOS VLSI Design 4th Ed.1: Circuits & Layout 34
Complementary CMOS Complementary CMOS logic gates
– nMOS pull-down network– pMOS pull-up network– a.k.a. static CMOS
pMOSpull-upnetwork
outputinputs
nMOSpull-downnetwork
Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1
Pull-down ON 0 X (crowbar)
CMOS VLSI Design 4th Ed.1: Circuits & Layout 35
Series and Parallel nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON Parallel: either can be ON
(a)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
OFF OFF OFF ON
(b)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
ON OFF OFF OFF
(c)
a
b
a
b
g1 g2 0 0
OFF ON ON ON
(d) ON ON ON OFF
a
b
0
a
b
1
a
b
11 0 1
a
b
0 0
a
b
0
a
b
1
a
b
11 0 1
a
b
g1 g2
CMOS VLSI Design 4th Ed.1: Circuits & Layout 36
Conduction Complement Complementary CMOS gates always produce 0 or 1 Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1– Thus Y=1 when either input is 0– Requires parallel pMOS
Rule of Conduction Complements– Pull-up network is complement of pull-down– Parallel -> series, series -> parallel
A
B
Y
CMOS VLSI Design 4th Ed.1: Circuits & Layout 37
Compound Gates Compound gates can do any inverting function Ex: (AND-AND-OR-INVERT, AOI22)Y A B C D
A
B
C
D
A
B
C
D
A B C DA B
C D
B
D
YA
CA
C
A
B
C
D
B
D
Y
(a)
(c)
(e)
(b)
(d)
(f)
CMOS VLSI Design 4th Ed.1: Circuits & Layout 38
Example: O3AI Y A B C D
A B
Y
C
D
DC
B
A
CMOS VLSI Design 4th Ed.1: Circuits & Layout 39
Signal Strength Strength of signal
– How close it approximates ideal voltage source VDD and GND rails are strongest 1 and 0
nMOS pass strong 0– But degraded or weak 1
pMOS pass strong 1– But degraded or weak 0
Thus nMOS are best for pull-down network
CMOS VLSI Design 4th Ed.1: Circuits & Layout 40
Pass Transistors Transistors can be used as switches
g = 0
s d
g = 1
s d
0 strong 0
Input Output
1 degraded 1
g = 0
s d
g = 1
s d
0 degraded 0
Input Output
strong 1
g = 1
g = 1
g = 0
g = 01
g
s d
g
s d
CMOS VLSI Design 4th Ed.1: Circuits & Layout 41
Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well
g = 0, gb = 1
a b
g = 1, gb = 0
a b
0 strong 0
Input Output
1 strong 1
g
gb
a b
a b
g
gb
a b
g
gb
a b
g
gb
g = 1, gb = 0
g = 1, gb = 0
CMOS VLSI Design 4th Ed.1: Circuits & Layout 42
Tristates Tristate buffer produces Z when not enabled
EN A Y
0 0 Z
0 1 Z
1 0 0
1 1 1
A Y
EN
A Y
EN
EN
CMOS VLSI Design 4th Ed.1: Circuits & Layout 43
Nonrestoring Tristate Transmission gate acts as tristate buffer
– Only two transistors– But nonrestoring
• Noise on A is passed on to Y
A Y
EN
EN
CMOS VLSI Design 4th Ed.1: Circuits & Layout 44
Tristate Inverter Tristate inverter produces restored output
– Violates conduction complement rule– Because we want a Z output
A
YEN
A
Y
EN = 0Y = 'Z'
Y
EN = 1Y = A
A
EN
CMOS VLSI Design 4th Ed.1: Circuits & Layout 45
Multiplexers 2:1 multiplexer chooses between two inputs
S D1 D0 Y
0 X 0 0
0 X 1 1
1 0 X 0
1 1 X 1
0
1
S
D0
D1Y
CMOS VLSI Design 4th Ed.1: Circuits & Layout 46
Gate-Level Mux Design How many transistors are needed? 20
1 0 (too many transistors)Y SD SD
44
D1
D0S Y
4
2
2
2 Y2
D1
D0S
CMOS VLSI Design 4th Ed.1: Circuits & Layout 47
Transmission Gate Mux Nonrestoring mux uses two transmission gates
– Only 4 transistorsS
S
D0
D1
YS
CMOS VLSI Design 4th Ed.1: Circuits & Layout 48
Inverting Mux Inverting multiplexer
– Use compound AOI22– Or pair of tristate inverters– Essentially the same thing
Noninverting multiplexer adds an inverter
S
D0 D1
Y
S
D0
D1Y
0
1S
Y
D0
D1
S
S
S
S
S
S
CMOS VLSI Design 4th Ed.1: Circuits & Layout 49
4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects
– Two levels of 2:1 muxes– Or four tristates
S0
D0
D1
0
1
0
1
0
1Y
S1
D2
D3
D0
D1
D2
D3
Y
S1S0 S1S0 S1S0 S1S0
CMOS VLSI Design 4th Ed.1: Circuits & Layout 50
D Latch When CLK = 1, latch is transparent
– D flows through to Q like a buffer When CLK = 0, the latch is opaque
– Q holds its old value independent of D a.k.a. transparent latch or level-sensitive latch
CLK
D Q
Latc
h D
CLK
Q
CMOS VLSI Design 4th Ed.1: Circuits & Layout 51
D Latch Design Multiplexer chooses D or old Q
1
0
D
CLK
QCLK
CLKCLK
CLK
DQ Q
Q
CMOS VLSI Design 4th Ed.1: Circuits & Layout 52
D Latch Operation
CLK = 1
D Q
Q
CLK = 0
D Q
Q
D
CLK
Q
CMOS VLSI Design 4th Ed.1: Circuits & Layout 53
D Flip-flop When CLK rises, D is copied to Q At all other times, Q holds its value a.k.a. positive edge-triggered flip-flop, master-slave
flip-flop
Flo
p
CLK
D Q
D
CLK
Q
CMOS VLSI Design 4th Ed.1: Circuits & Layout 54
D Flip-flop Design Built from master and slave D latches
QM
CLK
CLKCLK
CLK
Q
CLK
CLK
CLK
CLK
D
Latc
h
Latc
h
D QQM
CLK
CLK
CMOS VLSI Design 4th Ed.1: Circuits & Layout 55
D Flip-flop Operation
CLK = 1
D
CLK = 0
Q
D
QM
QMQ
D
CLK
Q
CMOS VLSI Design 4th Ed.1: Circuits & Layout 56
Race Condition Back-to-back flops can malfunction from clock skew
– Second flip-flop fires late– Sees first flip-flop change and captures its result– Called hold-time failure or race condition
CLK1
D Q1
Flo
p
Flo
p
CLK2
Q2
CLK1
CLK2
Q1
Q2
CMOS VLSI Design 4th Ed.1: Circuits & Layout 57
Nonoverlapping Clocks Nonoverlapping clocks can prevent races
– As long as nonoverlap exceeds clock skew We will use them in this class for safe design
– Industry manages skew more carefully instead 1
11
1
2
22
2
2
1
QMQD
CMOS VLSI Design 4th Ed.1: Circuits & Layout 58
Gate Layout Layout can be very time consuming
– Design gates to fit together nicely– Build a library of standard cells
Standard cell design methodology
– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules– nMOS at bottom and pMOS at top– All gates include well and substrate contacts
CMOS VLSI Design 4th Ed.1: Circuits & Layout 59
Example: Inverter
CMOS VLSI Design 4th Ed.1: Circuits & Layout 60
Example: NAND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 VDD rail at top
Metal1 GND rail at bottom 32 by 40
CMOS VLSI Design 4th Ed.1: Circuits & Layout 61
Stick Diagrams Stick diagrams help plan layout quickly
– Need not be to scale– Draw with color pencils or dry-erase markers
c
AVDD
GND
Y
AVDD
GND
B C
Y
INV
metal1
poly
ndiff
pdiff
contact
NAND3
CMOS VLSI Design 4th Ed.1: Circuits & Layout 62
Wiring Tracks A wiring track is the space required for a wire
– 4 width, 4 spacing from neighbor = 8 pitch Transistors also consume one wiring track
CMOS VLSI Design 4th Ed.1: Circuits & Layout 63
Well spacing Wells must surround transistors by 6
– Implies 12 between opposite transistor flavors– Leaves room for one wire track
CMOS VLSI Design 4th Ed.1: Circuits & Layout 64
32
40
Area Estimation Estimate area by counting wiring tracks
– Multiply by 8 to express in
CMOS VLSI Design 4th Ed.1: Circuits & Layout 65
Example: O3AI Sketch a stick diagram for O3AI and estimate area
– Y A B C D
AVDD
GND
B C
Y
D
6 tracks = 48
5 tracks = 40