lecture 1 design hierarchy chapter 1. digital system design flow 1.register-transfer levl (rtl) –...
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Lecture 1Design Hierarchy
Chapter 1
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Digital System Design Flow
1. Register-Transfer Levl (RTL)– e.g. VHDL/Verilog
2. Gate Level Design3. Circuit Level Design4. Physical Layout
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Verilog
• Include a set of 26 predefined functional models of common combinational logic gates called primitives.
• Primitives– The most basic functional objects that can be used
to compose a design– Are built into the language by means of internal
truth tables– Examples: and, nand, or, nor, xor, xnor
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More on Primitives
• 3-input nand primitive– Input signal a, b, and c– Output signal y
• Each primitive has ports (corresponding to hardware pins and terminals)– The output port(s) of a primitive must be first in
the list, followed by the primitive’s input ports.
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Instantiated Primitives
• Instantiated Primitives (nor, and,nand) are connected by wires.
• A wire is a data-type which is used to establish connectivity in a design, just as a physical wire establishes connectivity between gates.
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Example: a Full Adder
• Binary Addition• Gate-Level Synthesis• Verilog Representation
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Binary Addition (1)
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Binary Addition (2)
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Derivation of ∑
Question: What primitive best implements ∑? • Inputs: A, B• Outputs: xor (∑, A, B)
B A ∑
0 0 0
1 0 1
0 1 1
1 1 0
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Derivation of Carry Out
Question: What primitive best implements Co? • Inputs: A, B• Outputs: and (Co, A, B)
B A Co
0 0 0
1 0 0
0 1 0
1 1 1
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A Half Adder
A half adder is useful for adding LSB.
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Limitation of a Half Adder
A half-adder does not account for carry-in.
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Truth Table of ∑ of a Full Adder Cin B A ∑
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Identical to ∑ of a Half Adder
Cin+B+A=Cin+∑HA=Cin XOR ∑HA
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Truth Table of Co of a Full Adder Cin B A Co
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Identical to ∑ of a Half Adder
Use a Half Adderwith Cin and ∑HA to generate Co
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Schematic of a Full Adder
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A 3 bit parallel adder
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Gate Level vs. Verilog Model of a Full Adder
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Explanation
• The keywords module and endmodule encapsulate the text that describes the module
• The module name is Add_full• Module Ports are– Input a, b, c_in– Output c_out, sum
• Module instances: Add_half, or
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Nested Module
• Add_half is a child module of Add_full
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Gate Level Design
• Basic Gates– AND, NAND,OR, NOR, XOR, XNOR,NOT
• Universal Gates– NAND Gates– NOR Gates
• Multiple Inputs Logic Gates
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NAND Based Logic Gates
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NOR Based Logic Gates
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Multiple Inputs Logic Gates
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Circuit Level
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Physical Design
• Floor Planning– Estimates of the area of major units in the chip
and defines their relative placements.– Estimate wire lengths and wring congestions.– Challenge: estimate the size of each unit without
proceeding through a detailed design of the chip.• Layout• Design Verification• Tapeout
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A Sample Floor Plan
λ= ½ of minimum channel length
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A Sample Layout
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Layout of an Inverter
In a 0.6 um process 4/2=1.2 um/0.6 um.
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Design Verification
• LVS (Layout vs. Schematic) checks that transistors in a layout are connected in the same way as in the circuit schematic.
• DRC (Design Rule Checkers) verify that the layout satisfies design rules.
• ERC (Electrical Rule Checkers) scan for problems such as noise or premature wearout.
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Tapeout
• Tapeout gets its name from the old practice of writing a specifications of masks to a magnetic tape.
• GDS• Foundries:– TSMC– UMC– IBM
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Fabricated Chip
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IC Decapsulation
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Cross Section
Ball
Bottom Metal Trace
Via
Dielectric
Silver- Epoxy
Wire Bond
Top Metal Trace
package material(plastic)
IC Chip
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Low Cost Package1
12
7
•Red: Top layer trace
•Green: Via
•Blue: Bottom layer trace
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Package Parasitics