lecture 1 © dr. alaaeldin amin slide 1 coe 405 design and modeling of digital systems dr. alaaeldin...
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![Page 1: Lecture 1 © Dr. Alaaeldin Amin Slide 1 COE 405 Design and Modeling of Digital Systems Dr. Alaaeldin A. Amin Computer Engineering Department E-mail: amin@ccse.kfupm.edu.saamin@ccse.kfupm.edu.sa](https://reader036.vdocument.in/reader036/viewer/2022062518/56649ee05503460f94bf01d0/html5/thumbnails/1.jpg)
Lecture 1 © Dr. Alaaeldin Amin Slide 1
COE 405 Design and Modeling of
Digital Systems
Dr. Alaaeldin A. Amin
Computer Engineering Department
E-mail: [email protected]
Home Page : http://www.ccse.kfupm.edu.sa/~amin
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Lecture 1 © Dr. Alaaeldin Amin Slide 2
Course Objective
Learning VHDL Write Functionally Correct and well-documented
VHDL Code of Combinational or Sequential Digital Systems Intended for Modeling or Synthesis Purposes
Define and Use the 3 Major Modeling Styles (Structural, DataFlow, Behavioral)
Define a Suitable Test Bench for Model Verification
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Lecture 1 © Dr. Alaaeldin Amin Slide 3
Digital System Design
Realization of a specification Subject to the Optimization of Area (Chip, PCB) Speed Power dissipation Design time Testability
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Lecture 1 © Dr. Alaaeldin Amin Slide 4
Digital System Design
REG1 REG2
Main Logic Unit
REG3
Logic
FiniteState
Machine
Data PathControl
Path
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Lecture 1 © Dr. Alaaeldin Amin Slide 5
Digital System Design Cycle
Design Idea System Specification
Behavioral (Functional) Design
Logic Design
Circuit Design
Physical Design
Fabrication & Packaging
Data Path Design
Pseudo Code, Flow Charts
Bus & Register Structure
Netlist (Gate & Wire Lists)
Transistor List
VLSI / PCB Layout
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Lecture 1 © Dr. Alaaeldin Amin Slide 6
Number of Transistors in the CPU(Intel family)
0,001
0,01
0,1
1
10
100
1970 1975 1980 1985 1990 1995 2000
tra
nsi
sto
rs i
n m
illi
on
sDigital System complexity
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Lecture 1 © Dr. Alaaeldin Amin Slide 7
How to deal with the complexity?
Moore’s Law: Number of transistors that can be packed on a chip doubles every 18 months while the price stays the same.
Hierarchy: structure of a design at different levels of description
Abstraction: hiding the lower level details.
![Page 8: Lecture 1 © Dr. Alaaeldin Amin Slide 1 COE 405 Design and Modeling of Digital Systems Dr. Alaaeldin A. Amin Computer Engineering Department E-mail: amin@ccse.kfupm.edu.saamin@ccse.kfupm.edu.sa](https://reader036.vdocument.in/reader036/viewer/2022062518/56649ee05503460f94bf01d0/html5/thumbnails/8.jpg)
Lecture 1 © Dr. Alaaeldin Amin Slide 8
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Lecture 1 © Dr. Alaaeldin Amin Slide 9
Hierarchy
Top
–Down
Bottom
–UP
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Lecture 1 © Dr. Alaaeldin Amin Slide 10
Abstractions
An Abstraction is a Simplified Model of Some Entity Which Hides Certain Amount of the Internal Details of this EntityExamples are: NAND gate, Transistor, Abstract Data Type, etc.Lower Level Abstractions Give More Details of the Modeled Entity.
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Lecture 1 © Dr. Alaaeldin Amin Slide 11
Hardware Levels of Abstraction
Several Levels of Abstractions (Details) are Commonly Used: System Level Chip Level Register Level Gate Level Circuit (Transistor) Level Layout (Geometric) Level
More Details
(Less Abstract)
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Lecture 1 © Dr. Alaaeldin Amin Slide 12
Design Domains & Levels of Abstraction
Designs Can Be Expressed / Viewed in one of 3 Possible Domains Behavioral Domain (Behavioral View) Structural/Component Domain (Structural View) Physical Domain (Physical View)
A Design Modeled in a Given Domain Can be Represented at Several Levels of Abstraction (Details)
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Lecture 1 © Dr. Alaaeldin Amin Slide 13
Design Domains & Levels of Abstraction
Design Domain
Behavioral Structural Physical Abstraction Level System English Specs Computer, Disk
Units, Radar, etc. Boards, MCMs, Cabinets
Chip Algorithms, Flow Charts
Processors, RAMs, ROMs
Chips, Floor Plans, PCBs
Register Data Flow, Reg. Transfer
Registers, ALUs, Counters, MUX, etc.
Std. Cells, Floor Plans
Gate Boolean Equations
AND, OR, XOR, FFs, etc
Cells, Gates, FFs, PCBs
Circuit (Tr) Diff, and element Equations
Transistors, R, L, C, etc …
Mask Geometry (Layout)
Black Box
ViewGrey Box
ViewWhite Box
View
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Lecture 1 © Dr. Alaaeldin Amin Slide 14
Design methodsFull custom Maximal freedom High performance blocks Slow
Semi-custom Gate Arrays
Mask Programmable (MPGAs) Field Programmable (FPGAs))
Standard Cells Silicon Compilers & Parametrizable Modules (adder,
multiplier, memories)
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Lecture 1 © Dr. Alaaeldin Amin Slide 15
Design vs. Synthesis
Synthesis: The Process of Transforming H/W from One Level
of Abstraction to a Lower One
Design: A Sequence of Synthesis Steps Down to a Level of
Abstraction Which is Manufacturable
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Lecture 1 © Dr. Alaaeldin Amin Slide 16
Eng
lish
Spe
cs
Alg
orith
mic
Des
c.
Dat
a F
low
(RT
L)
Logi
c
Circ
uit (
Tra
nsis
tor)
Mas
k La
yout
Geo
met
ry
Beh
avio
ral
Do
mai
nS
tru
ctu
ral
Do
mai
n
System
Chip
Register
Gate
Circuit
Layout
Nat
ural
Lan
guag
eS
ynth
esis
Alg
orith
mic
Syn
thes
is, o
rH
igh-
Leve
l Syn
thes
is
Logi
cS
ynth
esis
Layo
utS
ynth
esis
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Lecture 1 © Dr. Alaaeldin Amin Slide 17
BehavioralDomain
StructuralDomain
System
Chip
Register
LogicSynthesis
Logic
Circuit(Transistor)
Mask LayoutGeometry
Gate
Circuit
Layout
LayoutSynthesis
English Specs
AlgorithmicDesc.
Data Flow(RTL)
Natural LanguageSynthesis
Algorithmic Synthesis, orHigh-Level Synthesis
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Lecture 1 © Dr. Alaaeldin Amin Slide 18
Design Automation & CAD Tools
Design Entry (Description) Tools Schematic Capture Hardware Description Language (HDL)
Simulation (Design Verification) Tools Simulators (Logic level, Transistor Level, High Language
Level “HLL”)
Synthesis ToolsTest Vector Generation Tools
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Lecture 1 © Dr. Alaaeldin Amin Slide 19
HARDWARE DESCRIPTION LANGUAGES
HDL are used to describe the hardware for the purpose of modeling, simulation, testing, design, and documentation. Modeling: behavior, flow of data, structure Simulation: verification and test Design: synthesis
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Lecture 1 © Dr. Alaaeldin Amin Slide 20
Purpose of VHDL
Problem Need a method to quickly design, implement, test, and document
increasingly complex digital systems Schematics and Boolean equations inadequate for million-gate IC
Solution A hardware description language (HDL) to express the design Associated computer-aided design (CAD) or electronic design
automation (EDA) tools for synthesis and simulation Programmable logic devices for rapid implementation of hardware Custom VLSI application specific integrated circuit (ASIC)
devices for low-cost mass production
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Lecture 1 © Dr. Alaaeldin Amin Slide 21
History of VHDLTwo widely-used HDLs today VHDL Verilog HDL (from Cadence, now IEEE standard)
VHDL - VHSIC Hardware Description Language
Very High Speed Integrated Circuit
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Lecture 1 © Dr. Alaaeldin Amin Slide 22
VHDL history Created by DOD to document military designs for
portability IEEE standard 1076 (VHDL) in 1987 Revised IEEE standard 1076 (VHDL) in 1993 IEEE standard 1164 (object types standard) in 1993 IEEE standard 1076.3 (synthesis standard) in 1996
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Lecture 1 © Dr. Alaaeldin Amin Slide 23
VHDL: Why to use?Reasons to use VHDL Power and flexibility Device-independent design Portability among tools and devices Device and tool benchmarking capability VLSI ASIC migration Quick time-to-market and low cost (with programmable logic)
Problems with VHDL Loss of control with gate-level implementation (so what?) Inefficient logic implementations via synthesis (engineer-
dependent) Variations in synthesis quality among tools (always improving)
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Lecture 1 © Dr. Alaaeldin Amin Slide 24
Design Flow in VHDLDefine the design requirementsDescribe the design in VHDL Top-down, hierarchical design approach Code optimized for synthesis or simulation
Simulate the VHDL source code Early problem detection before synthesis
Synthesize, optimize, and fit (place and route) the design for a device Synthesize to equations and/or netlist Optimize equations and logic blocks subject to constraints Fit into the components blocks of a given device
Simulate the post-layout design model Check final functionality and worst-case timing
Program the device (if PLD) or send data to ASIC vendor
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Lecture 1 © Dr. Alaaeldin Amin Slide 25
Design Tool Flow (Design Tool Flow (11))
VHDLDesign
Test Bench/Stimulus
Source Simulation Software
Waveform Data File
Synthesis Software
DeviceSelection
SynthesisDirectives
Equations orNetlist
To Fitter Software
Functional Simulation
Courtesy of Prof. R.L. Haggard,
Tennessee Technological University
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Lecture 1 © Dr. Alaaeldin Amin Slide 26
Design Tool Flow (Design Tool Flow (22))
Fitter (Place & Route) Software
DeviceProgramming
Fileor ASIC Data
Report File
Equations orNetlist
From SynthesisTest Bench/
Stimulus
Post-fit Simulation Software
Waveform Data FilePost-fitModel
Full-timing Simulation
Courtesy of Prof. R.L. Haggard,
Tennessee Technological University
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Lecture 1 © Dr. Alaaeldin Amin Slide 27
STYLES in VHDLLevels of Abstraction (Architectural Styles):Behavioral High level, algorithmic, sequential execution Hard to synthesize well Easy to write and understand (like high-level language code)
Dataflow Medium level, register-to-register transfers, concurrent execution Easy to synthesize well Harder to write and understand (like assembly code)
Structural Low level, netlist, component instantiations and wiring Trivial to synthesize Hardest to write and understand (very detailed and low level)
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Lecture 1 © Dr. Alaaeldin Amin Slide 28
SUMMARYThe VLSI digital design problem is described.
VLSI design automation and CAD tools are mentioned.
Purpose and background of VHDL have been pointed out.
VHDL and programmable logic are the best current solution for rapid design, implementation, testing, and documenting of complex digital systems.
A standard 6-step design synthesis process is used with VHDL.
The general flow of information through standard VHDL synthesis CAD tools was described.