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Lecture 1: Introduction toDigital Logic Design

CK Cheng

CSE Dept.

UC San Diego

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Outlines

• Administration

• Motivation

• Scope

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Administration

Web site:

http://www.cse.ucsd.edu/classes/fa12/cse140-a/

WebCT:

http://ted.ucsd.edu

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Administration

Instructor: CK Cheng, CSE2130, ckcheng+140@ucsd.edu, 858 534-6184

Teaching Assistants:• Shih-Hung Weng, s2weng@ucsd.edu • Jyoti Wadhwani, jwadhwan@ucsd.edu

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Administration

Schedule

• Outline (Use index to check the location of the textbooks)

• Lectures: 3:00-3:50PM, MWF, Center 115.

• Discussion: 9:00-9:50AM, F, Center 101.

• Office hours: CSE2130– 10:30-11:30AM, T– 1:00-2:00PM, W

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AdministrationTextbook: Digital Design and Computer Architecture, D.M. Harris

and S.L. Harris, Morgan Kaufmann, Second Edition, 2012.

Grading

• iClicker: 5% (a ramp function saturates at 80% of class points)

• CK Cheng Office Hr. visits: 2% bonus (1% per visit)

• Homework: 10% (grade on style, completeness or correctness)

• Midterm 1: 25% (M 10/22) (style, completeness and correctness)

• Midterm 2: 30% (W 11/14)

• Midterm 3: 30% (F 12/07)

• Optional take home final exam due 6PM, F. 12/14: 1% bonus

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Motivation• Microelectronic technologies have revolutionized

our world: cell phones, internet, rapid advances in medicine, etc.

• The semiconductor industry has grown from $21 billion in 1985 to $304 billion in 2010.

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Robert Noyce, 1927 - 1990• Nicknamed “Mayor of Silicon

Valley”

• Cofounded Fairchild Semiconductor in 1957

• Cofounded Intel in 1968

• Co-invented the integrated circuit

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Gordon Moore, 1929 - • Cofounded Intel in

1968 with Robert Noyce.

• Moore’s Law: the number of transistors on a computer chip doubles every year (observed in 1965)

• Since 1975, transistor counts have doubled every two years.

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Moore’s Law

“If the automobile had followed the same development cycle as the computer, a Rolls-Royce would today cost $100, get one million miles to the gallon, and explode once a year . . .”

– Robert Cringley

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iClicker

• The purpose of this course is that we:A. Learn what’s under the hood of an electronic

component

B. Learn the principles of digital design

C. Learn to systematically debug increasingly complex designs

D. Design and build digital systems

E. All of the above

F. Most of the above

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iClicker

Digital system can be built upon

A.Mechanical relays

B.Silicon transistors

C.DNAs

D.Quantum mechanical phenomena

E.All of the above

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Scope: Position in the Design Flow

The class assumes

CMOS transistors

AND, OR logic

Flip-Flip registers

Synchronous designs, but the application reaches beyond the assumed region.

Physics

Devices

AnalogCircuits

DigitalCircuits

Logic

Micro-architecture

Architecture

OperatingSystems

ApplicationSoftware

electrons

transistorsdiodes

amplifiersfilters

AND gatesNOT gates

addersmemories

datapathscontrollers

instructionsregisters

device drivers

programs

focus o

f th

is c

ours

e

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Scope: Sequence of Courses• CSE20: Discrete Math

• CSE140/L: Digital System

• CSE141/L: Computer Architecture

• CSE142-149: Architecture, Design Automation, Embedded Systems

• CSE237, 240-249, 291: Architecture, Design Automation, Embedded Systems

• ECE260A-C: VLSI Designs

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We will cover four major things in this course:

- Combinational Logic (H2)- Sequential Networks (H3)- Standard Modules (H5)- System Design (H4, H6-8)

Scope: Content

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Scope: Overall Picture of CS140

ControlSubsystem

Conditions

Control

Mux

Memory File

ALU

Memory Register

Conditions

Input

Pointer

CLK: Synchronizing Clock

Data Path Subsystem

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fi(x)

x1

.

.

.xn

fi(x)

Combinational Logic vs Sequential Network

Combinational logic:

yi = fi(x1,..,xn)

CLKSequential Networks1. Memory 2. Time Steps (Clock)

yit = fi (x1

t,…,xnt, s1

t, …,smt)

sit+1 = gi(x1

t,…,xnt, s1

t,…,smt)

fi(x)

x1

.

.

.xn

fi(x)fi(x)

x1

.

.

.xn

fi(x) si

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Scope

Subjects Building Blocks Theory

Combinational Logic

AND, OR, NOT, XOR

Boolean Algebra

Sequential Network

AND, OR, NOT, FF

Finite State Machine

Standard Modules

Operators,

Interconnects, Memory

Arithmetic, Universal Logic

System Design Data Paths, Control Paths

Methodologies

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Perspective

Class notesHomeworkTextbook

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Part I. Combinational Logic

• I) Specification• II) Implementation• III) Different Types of Gates

ab + cdab

cd

ecd

ab

e (ab+cd)