lecture 10: pn junction & mos...
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Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10
Lecture 10: PN Junction & MOS Capacitors
Prof. Niknejad
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Lecture Outline
� Review: PN Junctions Thermal Equilibrium
� PN Junctions with Reverse Bias (3.3-3.6)
� MOS Capacitors (3.7-3.9):– Accumulation, Depletion, Inversion
– Threshold Voltage
– CV Curve
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Results of MT #1
� Good Job!
� This is only 17% of your grade
13STD DEV
99MAX
34MIN
74AVG
Homework 15%Laboratory 20%Midterm #1 17%Midterm #2 18%Final 30%
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
PN Junction in Thermal Equilibrium
� Contact potential develops between P and N region
� Diffusion current balanced by drift current
� Depletion region is a “space-charge” region where the concentration of free carriers is low
� The depletion region is charged due to the immobile background ions (donors and acceptors)
� Used the “Depletion Approximation” to estimate the charge density � calculate the electric fields and potential variation using electrostatics in 1D
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Have we invented a battery?
� Can we harness the PN junction and turn it into a battery?
� Numerical example:
2lnlnln
i
ADth
i
A
i
Dthpnbi n
NNV
n
N
n
NV =
+=−≡ φφφ
mV60010
1010logmV60lnmV26
20
1515
2=×==
i
ADbi n
NNφ
?
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Contact Potential
� The contact between a PN junction creates a potential difference
� Likewise, the contact between two dissimilar metals creates a potential difference (proportional to the difference between the work functions)
� When a metal semiconductor junction is formed, a contact potential forms as well
� If we short a PN junction, the sum of the voltages around the loop must be zero:
mnpmbi φφφ ++=0
pnmnφ
pmφ
+
−biφ )( mnpmbi φφφ +−=
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
PN Junction Capacitor
� Under thermal equilibrium, the PN junction does not draw any current
� But notice that a PN junction stores charge in the space charge region (transition region)
� Since the device is storing charge, it’s acting like a capacitor
� Positive charge is stored in the n-region, and negative charge is in the p-region:
nodpoa xqNxqN =
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Reverse Biased PN Junction
� What happens if we “reverse-bias” the PN junction?
� Since no current is flowing, the entire reverse biased potential is dropped across the transition region
� To accommodate the extra potential, the charge in these regions must increase
� If no current is flowing, the only way for the charge to increase is to grow (shrink) the depletion regions
+
−Dbi V+−φ
DV 0<DV
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Current Under Reverse Bias
� Under thermal equilibrium current is zero � If we apply a reverse bias, we are increasing the barrier
against diffusion current� Drift current is low since the field only moves minority
carriers across junction� In fact, current is not zero but very small since the minority
carrier concentration is low. Minority carriers within one diffusion length of junction can contribute to a reverse bias current. This is more or less independent of the applied bias
pn
+− DV−pφ
nφ Dn V+φ
pφ0dX )( Dd VX
0E 0E
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Voltage Dependence of Depletion Width
� Can redo the math but in the end we realize that the equations are the same except we replace the built-in potential with the effective reverse bias:
+−=+=
da
DbisDnDpDd NNq
VVxVxVX
11)(2)()()(
φε
bi
Dn
da
a
d
DbisDn
Vx
NN
N
qN
VVx
φφε −=
+−= 1
)(2)( 0
bi
Dp
da
d
a
DbisDp
Vx
NN
N
qN
VVx
φφε −=
+−= 1
)(2)( 0
bi
DdDd
VXVX
φ−= 1)( 0
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Charge Versus Bias
� As we increase the reverse bias, the depletion region grows to accommodate more charge
� Charge is not a linear function of voltage
� This is a non-linear capacitor
� We can define a small signal capacitance for small signals by breaking up the charge into two terms
bi
DaDpaDJ
VqNVxqNVQ
φ−−=−= 1)()(
)()()( DDJDDJ vqVQvVQ +=+
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Derivation of Small Signal Capacitance
� From last lecture we found
� Notice that
�++=+ DV
DDJDDJ v
dV
dQVQvVQ
D
)()(
RD VVbipa
VV
jDjj
VxqN
dV
d
dV
dQVCC
==
−−===
φ1)( 0
bi
D
j
bi
Dbi
paj
V
C
V
xqNC
φφφ −
=−
=112
00
da
da
bi
s
da
d
a
bis
bi
a
bi
paj NN
NNq
NN
N
qN
qNxqNC
+=
+
==
φεφε
φφ 2
2
220
0
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Physical Interpretation of Depletion Cap
� Notice that the expression on the right-hand-side is just the depletion width in thermal equilibrium
� This looks like a parallel plate capacitor!
da
da
bi
sj NN
NNqC
+=
φε
20
0
1
0
11
2 d
s
dabissj XNN
qC
εφε
ε =
+=
−
)()(
Dd
sDj VX
VCε=
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
A Variable Capacitor (Varactor)
� Capacitance varies versus bias:
� Application: Radio Tuner
0j
j
C
C
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
P-type Si Substrate
N-type Diffusion RegionOxide
“Diffusion” Resistor
� Resistor is capacitively isolation from substrate – Must Reverse Bias PN Junction!
– PN Junction creates a distributed capacitance with substrate (RC transmission line)
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
MOS Capacitor
� MOS = Metal Oxide Silicon� Sandwich of conductors separated by an insulator � “Metal” is more commonly a heavily doped polysilicon
layer n+ or p+ layer� NMOS � p-type substrate, PMOS � n-type substrate
Oxide (SiO2)
Body (p-type substrate)
Gate (n+ poly)
011.7sε ε=
03.9oxε ε=
Very Thin!
~ 1nmoxt
x
0
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
P-I-N Junction
� Under thermal equilibrium, the n-type poly gate is at a higher potential than the p-type substrate
� No current can flow because of the insulator but this potential difference is accompanied with an electric field
� Fields terminate on charge!
ln ap
i
NkT
q nφ = − 550mV
nφ + ≈
Body (p-type substrate)
Gate (n+ poly)
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Fields and Charge at Equilibrium
� At equilibrium there is an electric field from the gate to the body. The charges on the gate are positive. The negative charges in the body come from a depletion region
Body (p-type substrate)
++++++++++++++++++− − − − − − − − −− − − − − − − −
− − − − − − − − − 0dX
+
−oxV +
−BV oxE
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Good Place to Sleep: Flat Band
� If we apply a bias, we can compensate for this built-in potential
� In this case the charge on the gate goes to zero and the depletion region disappears
� In solid-state physics lingo, the energy bands are “flat” under this condition
( )FB pnV φ φ+= − −
( ) 0G GB FBQ V V= =
Body (p-type substrate)
+−0FBV <
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Accumulation
� If we further decrease the potential beyond the “flat-band” condition, we essentially have a parallel plate capacitor
� Plenty of holes and electrons are available to charge up the plates
� Negative bias attracts holes under gate
( )G ox GB FBQ C V V= −
Body (p-type substrate)
−+GB FBV V<++++++++++++++++++−−−−−−−−−−−−−−−−−−
B GQ Q=
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Depletion
� Similar to equilibrium, the potential in the gate is higher than the body
� Body charge is made up of the depletion region ions
� Potential drop across the body and depletion region
Body (p-type substrate)
+−GB FBV V> + + + + + + + + + +
( )B a d GBQ qN X V= −− − − − − − − − −− − − − − − − −
( )G GB BQ V Q= −
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Body (p-type substrate)
+ + + + + + + + + +
Inversion
� As we further increase the gate voltage, eventually the surface potential increases to a point where the electron density at the surface equals the background ion density
� At this point, the depletion region stops growing and the extra charge is provided by the inversion charge at surface
+−GB TV V=− − − − − − − − −− − − − − − − −
sq
kTs i an n e N
φ
= = s pφ φ= −
sφ
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Threshold Voltage
� The threshold voltage is defined as the gate-body voltage that causes the surface to change from p-type to n-type
� For this condition, the surface potential has to equal the negative of the p-type potential
� We’ll derive that this voltage is equal to:
12 2 ( 2 )Tn FB p s a p
ox
V V q NC
φ ε φ= − + −
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Inversion Stops Depletion
� A simple approximation is to assume that once inversion happens, the depletion region stops growing
� This is a good assumption since the inversion charge is an exponential function of the surface potential
� Under this condition:
,max( )G Tn BQ V Q≈ −
,max( ) ( )G GB ox GB Tn BQ V C V V Q= − −
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Q-V Curve for MOS Capacitor
� In accumulation, the charge is simply proportional to the applies gate-body bias
� In inversion, the same is true
� In depletion, the charge grows slower since the voltage is applied over a depletion region
GQ
( )GBV VTnVFBV
inver
sion
accu
mula
tion
depletion
,maxBQ−
( )N GBQ V−
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Numerical Example
� MOS Capacitor with p-type substrate:
� Calculate flat-band:
� Calculate threshold voltage:
20nmoxt = 16 35 10 cmaN −= ×
( ) (550 ( 402)) 0.95VFB pnV φ φ+= − − = − − − = −
12 2 ( 2 )Tn FB p s a p
ox
V V q NC
φ ε φ= − + −
13
-6
3.45 10 F/cm
2 10 cmox
oxox
Ct
ε −×= =×
19 12 162 1.6 10 1.04 10 5 10 2 0.4.95 2( 0.4) 0.52VTn
ox
VC
− −× × × × × × × ×= − − − + =
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Num Example: Electric Field in Oxide
� Apply a gate-to-body voltage:
� Device is in accumulation
� The entire voltage drop is across the oxide:
� The charge in the substrate (body) consist of holes:
2.5GB FBV V= − <
56
2.5 0.55 ( 0.4) V8 10
2 10 cmGB pox n
oxox ox
VVE
t t
φ φ+
−
+ − − + − −= = = = − ××
7 2( ) 2.67 10 C/cmB ox GB FBQ C V V −= − − = ×
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 10 Prof. A. Niknejad
Numerical Example: Depletion Region
� In inversion, what’s the depletion region width and charge?
,max 2 0.8VB s p p p pV φ φ φ φ φ= − = − − = − =
2,max ,max
1
2a
B ds
qNV X
ε
=
,max,max
2144nms B
da
VX
qN
ε= =
7 2,max ,max 1.15 10 C/cmB a dQ qN X −= − = − ×