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Lecture 13

MOSFET Differential Amplifiers

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topics• Ideal characteristics of differential amplifier

– Input differential resistance– Input common-mode resistance– Differential voltage gain– CMRR

• Non-ideal characteristics of differential amplifier– Input offset voltage – Input biasing and offset current

• Differential Amplifier with active load• Frequency rresponse

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Figure 7.1 The basic MOS differential-pair configuration.

MOS differential pair

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Figure 7.2 The MOS differential pair with a common-mode input voltage vCM.

Common mode operation

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Exercise 7.1 kRmAIVVVmAL

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Figure 7.3 (Continued)

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Figure 7.4 The MOS differential pair with a differential input signal vid applied. With vid positive: vGS1 vGS2, iD1 iD2, and vD1 vD2; thus (vD2 vD1) will be positive. With vid negative: vGS1 vGS2, iD1 iD2, and vD1 vD2; thus (vD2 vD1) will be negative.

Differential mode operation

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Figure 7.5 The MOSFET differential pair for the purpose of deriving the transfer characteristics, iD1 and iD2 versus vid vG1 – vG2.

Large signal operation

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Figure 7.6 Normalized plots of the currents in a MOSFET differential pair. Note that VOV is the overdrive voltage at which Q1 and Q2 operate when conducting drain currents equal to I/2.

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Figure 7.7 The linear range of operation of the MOS differential pair can be extended by operating the transistor at a higher value of VOV.

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Figure 7.8 Small-signal analysis of the MOS differential amplifier: (a) The circuit with a common-mode voltage applied to set the dc bias voltage at the gates and with vid applied in a complementary (or balanced) manner. (b) The circuit prepared for small-signal analysis. (c) An alternative way of looking at the small-signal operation of the circuit.

Small signal operation (differential gain)

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2

12

1

2

1

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Microelectronic circuits 13

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Common-mode gain et CMRR

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(1) The differential pair is taken single-endedly

(2) The output is taken differentially

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/2

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12

2

1

21

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Figure 7.11 Analysis of the MOS differential amplifier to determine the common-mode gain resulting from a mismatch in the gm values of Q1 and Q2.

Consider gm mismatch

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Microelectronic circuits 17

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Figure 7.25 (a) The MOS differential pair with both inputs grounded. Owing to device and resistor mismatches, a finite dc output voltage VO results. (b) Application of a voltage equal to the input offset voltage VOS to the terminals with opposite polarity reduces VO to zero.

Input offset voltage

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Microelectronic circuits 20tos

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Differential amplifier with active load

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Differential amplifier with active load

1. Differential gain 2. Common-mode gain et CMRR3. Input offset voltage

Active load

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Figure 7.29 Determining the short-circuit transconductance Gm ; io/vid of the active-loaded MOS differential pair.

1. Find the transconductance Gm

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Microelectronic circuits 26

2. Find the output resistance Ro

3. Find the differential gain

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Microelectronic circuits 27

Figure 7.31 Analysis of the active-loaded MOS differential amplifier to determine its common-mode gain.

Common-mode gain et CMRR

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Frequency response

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