Lecture 17OUTLINEThe MOS Capacitor (contd)Small-signal capacitance(C-V characteristics)

Reading: Pierret 16.4; Hu 5.6

MOS Capacitance MeasurementiacC-V MeterGATEMOS Capacitor VG is scanned slowly Capacitive current due to vac is measuredSemiconductorEE130/230A Fall 2013Lecture 17, Slide *

MOS C-V Characteristics (p-type Si)VGaccumulationdepletioninversionVFBVTQinvslope = -CoxVGaccumulationdepletioninversionVFBVTCCoxIdeal C-V curve:Lecture 17, Slide *EE130/230A Fall 2013

Capacitance in Accumulation (p-type Si)As the gate voltage is varied, incremental charge is added (or subtracted) to (or from) the gate and substrate. The incremental charges are separated by the gate oxide.M O SDQQ-DQ-QCoxLecture 17, Slide *EE130/230A Fall 2013

Flat-Band Capacitance(p-type Si)At the flat-band condition, variations in VG give rise to the addition/subtraction of incremental charge in the substrate, at a depth LDLD is the extrinsic Debye Length, a characteristic screening distance, or the distance where the electric field emanating from a perturbing charge falls off by a factor of 1/e CoxCDebyeLecture 17, Slide *EE130/230A Fall 2013

Capacitance in Depletion (p-type Si) As the gate voltage is varied, the depletion width varies.Incremental charge is effectively added/subtracted at a depth W in the substrate.M O SDQQ-DQ-QCoxWCdepLecture 17, Slide *EE130/230A Fall 2013

Capacitance in Inversion (p-type Si)CASE 1: Inversion-layer charge can be supplied/removed quickly enough to respond to changes in gate voltage. Incremental charge is effectively added/subtracted at the surface of the substrate.M O SDQ-DQCoxWTTime required to build inversion-layercharge = 2NAto/ni , where to = minority-carrier lifetime at surfaceLecture 17, Slide *EE130/230A Fall 2013

Capacitance in Inversion (p-type Si)CASE 2: Inversion-layer charge cannot be supplied/removed quickly enough to respond to changes in gate voltage. Incremental charge is effectively added/subtracted at a depth WT in the substrate.M O SDQ-DQWTCoxCdepLecture 17, Slide *EE130/230A Fall 2013

Supply of Substrate Charge (p-type Si)Accumulation:Depletion:Inversion:Case 1Case 2Lecture 17, Slide *EE130/230A Fall 2013C. C. Hu, Modern Semiconductor Devices for ICs, Figure 5-17

MOS Capacitor vs. MOS Transistor C-V(p-type Si) VGaccumulationdepletioninversionVFBVTCMOS transistor at any f,MOS capacitor at low f, orquasi-static C-VMOS capacitor at high fCminCmax=CoxCFBLecture 17, Slide *EE130/230A Fall 2013

Quasi-Static C-V Measurement(p-type Si)The quasi-static C-V characteristic is obtained by slowly ramping the gate voltage (< 0.1V/s), while measuring the gate current IG with a very sensitive DC ammeter. C is calculated from IG = C(dVG/dt)VGaccumulationdepletioninversionVFBVTCCmax=CoxCminCFBLecture 17, Slide *EE130/230A Fall 2013

Deep Depletion(p-type Si)If VG is scanned quickly, Qinv cannot respond to the change in VG. Then the increase in substrate charge density Qs must come from an increase in depletion charge density Qdep depletion depth W increases as VG increases C decreases as VG increases

Lecture 17, Slide *EE130/230A Fall 2013

MOS C-V Characteristic for n-type SiLecture 17, Slide *VGaccumulationdepletioninversionVTVFBCMOS transistor at any f,MOS capacitor at low f, orquasi-static C-VMOS capacitor at high fCminCmax=CoxCFBEE130/230A Fall 2013

Examples: C-V CharacteristicsDoes the QS or the HF-capacitor C-V characteristic apply?MOS capacitor, f=10kHzMOS transistor, f=1MHzMOS capacitor, slow VG rampMOS transistor, slow VG rampLecture 17, Slide *EE130/230A Fall 2013

Example: Effect of DopingHow would the normalized C-V characteristic below change if the substrate doping NA were increased?VFBVTCminVFBVTC/Cox1Lecture 17, Slide *EE130/230A Fall 2013

Example: Effect of Oxide ThicknessHow would the normalized C-V characteristic below change if the oxide thickness xo were decreased?VFBVTCminLecture 17, Slide *VFBVTC/Cox1EE130/230A Fall 2013

Derivation of Time to Build Inversion-Layer Charge(for an NMOS device, i.e. p-type Si)The net rate of carrier generation is: (ref. Lecture 5, Slide 24)wheresince trap states that contribute most significantly to G-R have an associated energy level near the middle of the band gap.Within the depletion region, n and p are negligible, so where tn tp to Therefore, the rate at which the inversion-layer charge density Qinv (units: C/cm2) increases due to thermal generation within the depletion region (of width W) isLecture 17, Slide *EE130/230A Fall 2013

For a fixed value of gate voltage, the total charge in the semiconductor is fixed:ThereforeThe solution to this differential equation iswhereLecture 17, Slide *EE130/230A Fall 2013

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