lecture 19marked
TRANSCRIPT
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8/12/2019 Lecture 19marked
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EE105 Fall 2007 Lecture 19, Slide 1 Prof. Liu, UC Berkeley
Lecture 19
OUTLINE
Common-gate stage
Source follower
Reading: Chapter 7.3-7.4
ANNOUNCEMENTS For Problem 4 of HW10, use VDD= 1.8V and VTH= 0.4V
Note: Midterm #2 will be held on Thursday 11/15
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8/12/2019 Lecture 19marked
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EE105 Fall 2007 Lecture 19, Slide 2 Prof. Liu, UC Berkeley
Diode-Connected MOSFETs
Note that the small-signal model of a PMOSFET is identical to
that of an NMOSFET
1
1
1
o
m
X rg
R 2
2
1
o
m
Y rg
R
Diode-connected NMOSFET
Small-signal analysis circuit Small-signal analysis circuit
Diode-connected PMOSFET
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EE105 Fall 2007 Lecture 19, Slide 3 Prof. Liu, UC Berkeley
Summary of MOSFET Impedances
Looking intothe drain, theimpedance isroif the gateand sourceare (ac)
grounded.
Looking intothe gate, theimpedance isinfinite ().
Looking into thesource, theimpedance is 1/gmin parallel with roifthe gate and drainare (ac) grounded.
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EE105 Fall 2007 Lecture 19, Slide 4 Prof. Liu, UC Berkeley
Common-Gate Amplifier Stage
An increase in Vin
decreases VGS
and hence decreases ID.
The voltage drop across RDdecreasesVoutincreases
The small-signal voltage gain (Av) is positive.
Dmv RgA
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EE105 Fall 2007 Lecture 19, Slide 5 Prof. Liu, UC Berkeley
Operation in Saturation Region
For M1to operate in saturation, V
outcannot fall below V
b-V
TH.
Trade-off between headroom and voltage gain.
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EE105 Fall 2007 Lecture 19, Slide 6 Prof. Liu, UC Berkeley
I/O Impedances of CG Stage ( = 0)
Dout RR
m
ing
R 1
Small-signal analysis circuit for
determining output resistance, Rout
Small-signal analysis circuit for
determining input resistance, Rin
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8/12/2019 Lecture 19marked
7/16EE105 Fall 2007 Lecture 19, Slide 7 Prof. Liu, UC Berkeley
CG Stage with Source Resistance
S
m
D
v
Rg
RA
1
in
m
S
mX v
gR
gv
1
1
1
1
Sm
Dm
in
X
X
out
in
out
RgRg
v
v
v
v
v
v
Small-signal equivalent
circuit seen at input
For = 0:
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8/12/2019 Lecture 19marked
8/16EE105 Fall 2007 Lecture 19, Slide 8 Prof. Liu, UC Berkeley
OSOmSSmOout rRrgRRgrR 11
The output impedance of a CG stage with source resistance isidentical to that of CS stage with degeneration.
Small-signal analysis circuit for
determining output resistance, Rout
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8/12/2019 Lecture 19marked
9/16EE105 Fall 2007 Lecture 19, Slide 9 Prof. Liu, UC Berkeley
CG Stage with Biasing
R1
and R2establish the gate bias voltage.
R3 provides a path for the bias current of M1 to flow.
Dm
Sm
m
in
out RgRgR
gR
v
v
/1||
/1||
3
3
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8/12/2019 Lecture 19marked
10/16EE105 Fall 2007 Lecture 19, Slide 10 Prof. Liu, UC Berkeley
CG Stage with Gate Resistance
For low signal frequencies, the gate conducts no current.Gate resistance does not affect the gain or I/O impedances.
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8/12/2019 Lecture 19marked
11/16EE105 Fall 2007 Lecture 19, Slide 11 Prof. Liu, UC Berkeley
CG Stage Example
DOS
m
Omout RrR
grgR ||||
11
2
11
SmmDm
in
X
X
outv
Rgg
Rg
v
v
v
vA
21
1
1
Small-signal equivalent
circuit seen at input
Small-signal equivalent
circuit seen at output
inSmmin
S
mm
mm
X vRgg
v
Rgg
ggv
21
21
21
1
1
11
11
1
2
111
1O
m
SOmout rg
RrgR
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8/12/2019 Lecture 19marked
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EE105 Fall 2007 Lecture 19, Slide 12 Prof. Liu, UC Berkeley
Source Follower Stage
Small-signal analysis circuit for
determining voltage gain, Av
1
||1
||
LO
m
LO
in
out
v
Rrg
Rr
v
vA
Equivalent circuit
Looutinm
Lomout
Rrvvg
Rrvgv
1
outin vvv 1
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EE105 Fall 2007 Lecture 19, Slide 13 Prof. Liu, UC Berkeley
Source Follower Example
In this example, M2acts as a current source.
21
1
21
||1
||
OO
m
OOv
rrg
rrA
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EE105 Fall 2007 Lecture 19, Slide 14 Prof. Liu, UC Berkeley
Routof Source Follower
The output impedance of a source follower is relatively low,whereas the input impedance is infinite (at low frequencies);thus, it is useful as a voltage buffer.
L
m
LO
m
out Rg
Rrg
R ||1
||||1
Small-signal analysis circuit for
determining output resistance, Rout
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EE105 Fall 2007 Lecture 19, Slide 15 Prof. Liu, UC Berkeley
Source Follower with Biasing
RGsets the gate voltage to VDD; RSsets the drain current.(Solve the quadratic equation to obtain the value of ID.)
221
THSDDDoxnD VRIV
LWCI
Assuming l= 0:
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EE105 Fall 2007 Lecture 19, Slide 16 Prof. Liu, UC Berkeley
Supply-Independent Biasing
If Rsis replaced by a current source, the drain current IDbecomes independent of the supply voltage VDD.