lecture 2.2 bjt dc biasing

8/3/2019 Lecture 2.2 BJT DC Biasing

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BJT DC BiasingEE 21 Fundamentals of Electronics

1

EE21Slides(AAMS)

Analysis of Transistor Circuits

As previously mentioned, transistor is not some

magical device with efficiency > 100%

The improved output AC power level is the result of

energy transfer from applied DC supplies.

AC and DC response of a transistor amplifier system is

taken into consideration

Superposition theorem is applied2

EE21Slides(AAMS)

DC Analysis of Transistor Circuits

NPN transistors are to be used in the

configurations

PNP transistors change analysis simply by

reversing all current directions and voltage

polarities

Capacitors are open at DC; capacitors are

chosen such that they have near-zero

reactance at frequencies of interest.3

EE21Slides(AAMS)

Important relationships

4

BE

BC

BE

II

II

VV

)1(

7.0

EE21Slides(AAMS)

Basic Transistor Configurations

Fixed bias

Emitter-stabilized bias

Voltage-divider bias

Feedback bias

Miscellaneous configurations

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EE21Slides(AAMS)

Fixed Bias

6

RC

EE21Slides(AAMS)


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Equivalent Ckt (DC analysis)

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RC

RC

EE21Slides(AAMS)

DC Analysis of Fixed bias

INPUT (B-E) LOOP:

8

0BEBBCC

VRIV

B

BECCB

R

VVI

EE21Slides(AAMS)

Fixed Bias: Output Loop

9

RC

EE21Slides(AAMS)

DC Analysis of Fixed Bias

OUTPUT (C-E) LOOP:

The bottom equation is the equation of your

loadline.

10

0CECCCC

VRIV

CCCCCERIVV

EE21Slides(AAMS)

Reviewing the subscripted

voltage notation VCE = VC VE.

VBE = VB VE.

But in the fixed bias circuit, the emitter terminal

is directly connected to ground, thus VE = 0,

Therefore, VCE = VC

VBE = VB.

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EE21Slides(AAMS)

Example: Fixed-bias circuit

For the fixed bias

circuit, determine:a. Base current IB

b. Q-point coordinates

c. VB and VC

d. VBC

e. Interpret the value

of VBC.

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EE21Slides(AAMS)


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Loadline and Q-point

The equation is called the

loadline, defined by the load resistance Rc.

It is a line relating the output voltage VCE and

the output current IC.

At a certain DC bias, a transistor circuit has a

Q-point (operating point), with coordinates

(VCEQ, ICQ). 13

CCCCCERIVV

EE21Slides(AAMS)

Transistor Saturation

A transistor in saturation = distorted signal*

Current is theoretically maximum if VCE = 0.

i.e.

Taking RCE as theoretical short, the loadline

equation for ICsatis given by

14

00

CSatC

CE

CE

II

VR

C

CCCSat

R

VI

EE21Slides(AAMS)

Transistor Cutoff

The loadline equation also gives us the value

of the transistor cutoff, where IC = 0.

Taking RCE as theoretical open circuit, the

loadline equation gives the expression for

VCEcutoff:

15

0

CECutoff

C

CECE

V

I

VR

CCCECutoff VV

EE21Slides(AAMS)

Loadline plotting

The two points (VCEcutoff, 0) and (0, ICsat) are the

two intercepts of the loadline.

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EE21Slides(AAMS)

Loadline Variations: Rc

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EE21Slides(AAMS)

Loadline Variations: Vcc

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EE21Slides(AAMS)


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Emitter-Stabilized Bias Circuit

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RC

EE21Slides(AAMS)

DC Analysis of Emitter-Stabilized Bias

INPUT (B-E) LOOP:

butIE= IB(+1), therefore

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0EEBEBBCC

RIVRIV

EB

BECCB

RR

VVI

)1(

0)1( EBBEBBCC

RIVRIV

EE21Slides(AAMS)

DC Analysis of Emitter-Stabilized Bias

OUTPUT (C-E) LOOP:

letting ICbe approximately equal to IE,

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0EECECCCC

RIVRIV

)( ECCCCCERRIVV

0ECCECCCC

RIVRIV

EE21Slides(AAMS)

Notes:

VE - emitter-ground voltage

VC collector-ground voltage:

VB base-ground voltage

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CCCCECECRIVVVV

ECEEERIRIV

EBEBVVV

EE21Slides(AAMS)

Example: Emitter-Stabilized Bias

For the network shown,

determine:1. Base current

2. Q-point coordinates

3. Vc, VE, and VB

4. VBC

5. Interpret VBC.

6. Plot the loadline and

Q-point of the circuit.

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EE21Slides(AAMS)

Home/Dorm/etc. work

Repeat examples 1 (fixed bias) and 2 (emitter-

stabilized) for =100.

Plot the corresponding loadlines and Q-points

and compare them with what we solved in

class.

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EE21Slides(AAMS)


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Voltage-Divider Bias Circuit

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EE21Slides(AAMS)

DC Analysis of Voltage-Divider Bias

Two methods of analysis:

Exact: method is always useable, requires

Thvenins theorem on the input side of thenetwork

Approximate: especially useful for designing VD

circuits, however, it can only be used upon

meeting a required design criteria.

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EE21Slides(AAMS)

Voltage-Divider Bias: Exact Analysis

Use Thvenins

theorem on the

input side of the

network:

We need Thvenin

resistance and

voltage to construct

TEC for the inputside 27

EE21Slides(AAMS)

Input Side Equivalence

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21

2

2

21 //

RR

RVVE

RRR

CCRTH

TH

EE21Slides(AAMS)

Equivalent circuit with TEC @ Input

The voltage-divider

circuit can now beanalyzed in the

same manner as the

emitter-stabilized

bias configuration.

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EE21Slides(AAMS)


INPUT (B-E) LOOP:

again, letIE= IB(+1), therefore

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0 EEBETHBTH RIVRIE

ETH

BETHB

RR

VEI

)1(

0)1( EBBETHBTH

RIVRIE

EE21Slides(AAMS)


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OUTPUT (C-E) LOOP:

letting ICbe approximately equal to IE,

0EECECCCC

RIVRIV

)(ECCCCCERRIVV

0ECCECCCC

RIVRIV

EE21Slides(AAMS)

Voltage Divider Approximate Analysis

Base-ground resistance, denoted as Ri, is much

larger when reflected to the input loop

Accepting this, then Ri>>R2 for the voltage div Thus, IB


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Voltage Feedback Bias

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EE21Slides(AAMS)

DC Analysis of Voltage Feedback

First we note that

assume IB very small, such that

The base-emitter loop is as follows:

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BCCIII '

BCCIII '

0' EEBEBBCCCC

RIVRIRIV EE21Slides(AAMS)


Substituting the following relations:

39 ECB

BECCB

RRR

VVI

BCCIII ' CE II

0EBBEBBCBCC

RIVRIRIV

EE21Slides(AAMS)


C.E. Loop:

substituting and isolating VCE

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0' EECECCCC

RIVRIV

ECCIII '

)(ECCCCCE

RRIVV EE21Slides(AAMS)

Example: Voltage Feedback Bias

For the

configuration below,determine IC and IE.

Repeat for=135.

41

EE21Slides(AAMS)

Miscellaneous Bias Configurations

Configurations not falling under the four

common circuits discussed Procedure for analysis, though, is the same:

Use the input side of the circuit to find an

expression for the input current (aka controlling

current)

Find the load-line using the output side of the

circuit

Circuit simplification (such as Thvnins thm) may

be applied if necessary.42

EE21Slides(AAMS)


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Example 1: Common-base circuit

For the common-base circuit, determine the

voltage VCB and the current IB. Assume =1.

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EE21Slides(AAMS)

Example 2: Common-collector configuration

Determine VCE and IE.

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EE21Slides(AAMS)

Transistor Network Design

Circuit design: Use appropriate relationships

such as ohms law & doubly-subscripted

voltage calculations.

For voltage-divider circuit networks, the

approximate analysis is used (recall design

criteria).

If multiple resistors are unknown, the

relationship is a good place to

start.45

CCEVV

10

1

EE21Slides(AAMS)

Example 3:Voltage-Divider Circuit Design

Design a voltage divider circuit with the

following requirements:

Biasing voltage Vcc = 20 Volts

= 80

Q-point coordinates: (8 V, 10 mA)

What quantities are unknown?

46

EE21Slides(AAMS)

lecture 2.2 bjt dc biasing

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