lecture 3 - ecee
TRANSCRIPT
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Week 3Dr. David Ward
Hybrid Embedded Systems
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Today’s AgendaDiscuss Homework and Labs
HW #2 due September 17Interrupt Systems
NIOS II, HAL, PIOL b # O iLab # 3 Overview
PS/2 Keyboard design
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Expanding the I/O SystemInterrupt system: Allow devices to get processor’s attentionInterrupt system: Allow devices to get processor s attention
Processor interrupts
Memory - I/O Bus
MainMemory
I/OController
I/OController
I/OController
Disk Disk Graphics Network
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Push Buttons
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I t t TInterrupt TermsHardware interrupt
an exception caused by a signal from hardware (request for action)IRQ- “Interrupt ReQuest” ISR- Interrupt Service Routine
Code executed on the main processor in service of the deviceInterrupt vector
commonly referred to term for memory location holding the address of the interrupt service routine (ISR)address of the interrupt service routine (ISR)
Interrupt mask used to block interrupts
Software ExceptionSoftware ExceptionAny condition or signal that interrupts normal program execution.
Software: divide by 0, illegal opcode, etc.
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Interrupt Terminolgy (Nios II)application context
the status of the Nios II processor and the HAL during normal program execution, outside of the exception handler. context switch
the process of saving the Nios II processor's registers on an exception, and restoring them on return from the interrupt service routine. exception handler
the complete system of software routines, which service all exceptions and pass control to ISRs as necessary. exception overheadexception overhead
additional processing required by exception processing. The exception overhead for a program is the sum of all the time occupied by all context switches.
implementation-dependent instructiona Nios II processor instruction that is not supported on all implementations of the Nios II core. For example, the mul and div instructions are implementation-dependent, because they are not supported on the Nios II/e core.
interrupt contextthe status of the Nios II processor and the HAL when the exception handler is executing.
interrupt request (IRQ) a signal from a peripheral requesting a hardware interrupt.
interrupt service routine (ISR) a software routine that handles an individual hardware interrupt.
invalid instructionan instruction that is not defined for any implementation of the Nios II processoran instruction that is not defined for any implementation of the Nios II processor.
unimplemented instructionan implementation-dependent instruction that is not supported on the particular Nios II core implementation that is in your system. For example, in the Nios II/e core, mul and div are unimplemented.
other exceptionan exception which is not a hardware interrupt nor a trap.
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Difference between Interrupts andDifference between Interrupts and Software Exceptions
I t t i h dInterrupt is a hardware-based eventSoftware exceptions originate from the programoriginate from the program currently running on processor
Handled in a similar way as interrupts: each designed cause will change the gprogram to an “exception handler” routine.routine.
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NIOS II InterruptMany devicesInterrupt controller is generated by SOPC builder
Controlled by IRQ number assignmentControlled by IRQ number assignment32 level-senitive interrupt request lines
irq0 – irq31Software or Hardware prioritySoftware or Hardware priority
Software (32 slave IRQs)Priority encoded IRQ[0] is highest priority
Hardware (64 slave IRQs)Hardware (64 slave IRQs)Passes highest priority to the master portLesser priority IRQs undetectable until higher priority IRQ is clearedcleared
Supports nested interrupts
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NIOS II Interrupt Controller
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NIOS II Interrupt Controller 2
Up to 64 slave IRQ signals
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Exception Handling in Nios IISaves the status register in estatus
This means that if hardware interrupts are enabled, the EPIE bit of estatus is set.
Disables hardware interrupts. Saves the next execution address in ea (r29)- the effective address registeraddress register. Transfers control to the Nios II processor exception addressNios II exceptions and interrupts are not vectored.p p
The same exception address receives control for all types of interrupts and exceptions. The exception handler at that address must determine theThe exception handler at that address must determine the type of exception or interrupt.
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Hardware Abstraction Layer (HAL)
Lightweight runtime environment
provides simple device p pdriver interfaceallows access to devices with common C library functions
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HAL ServicesIntegration with C standard libraryDevice driversHAL APISystem initializationDevice initialization
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Interfacing with HALApplication developers
using HAL API or C standard librarydo not consider the underlying hardware
Device driver developersk d f l l l h dmaking drivers for low-level hardware
interface newly written drivers with HAL
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Generic Devices in HALCharacter-mode devicesTimer devicesFile subsystemsEthernet devicesDMA devicesFlash memory devices
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Exception Handling in HALTop level exception handler
creates private stackstores register values onto the stackdetermines the type of exception and invoke the right SW or HW handlerright SW or HW handler
Software exception handlerHardware interrupt handlerp
ISRs for peripherals
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NIOS II I E i C l DiNIOS II Interrupt or Exception Control Diagram
1 Save the status registers1. Save the status registers2. Disable interrupts3. Save the EA (effective 3 (address register)…where the program was executing before interruptbefore interruptTransfer control to the interrupt vector
EA is also known as PC (Program Counter)
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Exception Handling in HALCh k if h d i iCheck estatus to see if hardware interrupt is enabled
if yes check to see if the interrupt is hardware byif yes, check to see if the interrupt is hardware by checking ipending
if yes, corresponding ISR is called
if no, call the software exception handlerHardware interrupts have higher priority than
ft tisoftware exceptions
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Exception Handling in HALUpon returning from exceptions, the top-level handler
restores the stack pointerrestores the registers from the stacke its b issuing an eret instructionexits by issuing an eret instruction
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Exception Handling in HALHW Handlers
32 hardware interrupts (0 to 31, with 0 as highest priority)
priority is HAL specificpriority is HAL specific and not NIOS II
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E i H dli i HALException Handling in HALSW handlersSW handlers
used for unimplemented instructionse.g. running multiplication on NIOS II with noe.g. running multiplication on NIOS II with no multipliers
traps
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Interrupt Diagram Stepsaddsubandor
userprogram(1) I/O
interrupt
CPU
ornop
interrupt
(2) save EA
IOCMemory
readstore
(3) Get interruptservice addrand change interrupt
service
IOC
device
Advantage:
...rtimemory
gNIOS EA to thataddress
serviceroutine(4)
:
Advantage:User program progress is only halted during actual transfer
Disadvantage, special hardware is needed to:Cause an interrupt (I/O device)Cause an interrupt (I/O device)Detect an interrupt (processor)Save the proper states to resume after the interrupt (processor)
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Get Interrupt Service Address(3) Get interrupt service addr and change NIOS EA to that address
For each IRQ #, there is a memory address story in an interrupt vector table (also in memory).
Upon that hardware selecting which IRQ, a LOAD to the corresponding vector table entry is performed
The result of that loaded value (4 bytes) is placed inThe result of that loaded value (4 bytes) is placed in the EA (effective address) of the NIOS ProcessorThus the next instruction executed is the code for the Interrupt Service Routine (ISR)p ( )
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PIO Core Types: Output, Input w/ Interrupt, Bi-directional
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PIO Device MapBase address assigned from SOPC
(But device is 4 register locations (4 bytes each location)Registers are: DATA Direction InterruptMaskRegisters are: DATA, Direction, InterruptMask, Edgecapture
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PIO CORE Data
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PIO CORE Edgecapture
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PIO CORE Interrupt (IRQ) Generation
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PIO CORE Configurations
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Expanded PIO Device Map
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Expanded PIO Device Map
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Expanded PIO Device Map
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Expanded PIO Device Map
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Hardware Abstraction Layer (HAL).
– System software that allows programmer to control the hardware devices using a series of function callsde ces us g a se es o u c o ca s
– Control how or whether interrupts should be handled– i.e. turn off interrupts when code executing on NIOS II CPU is
critical (time constraint) don’t allow serial input cable to getcritical (time constraint), don t allow serial input cable to get processor’s attention
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HAL Interface
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NIOS II Interrupt SetupDeclare variable for holding information that will be
d f d i t ISRpassed from device to ISREnable the device
Set the control registers on the deviceSet the control registers on the deviceRegister the ISR with the HAL system
Done in main()Done in main()Develop code for ISR
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Enable Device and Register ISREnable Device and Register ISRDeclare
i bl tvariable to hold state of device that will be
d t
Set the controls on
passed to ISR
controls on the PIO device to capture and causecause interrupts
Register the ISR with the HAL interface: assign address of the ISR to theInterrupt vector table.
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Enable Device and Register ISR
Memory-
This is decided at SOPC builder time, user can
ymapped device address assigned at
define which IRQ # [0 up to 31]
gSOPC builder time
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NIOS II Interrupt Example ISR#include “system.h”#include “altera_avalon_pio_regs.h”#include “alt_types.h”
static void handle_button_interrupts(void* context, alt_u32 id)
{{
// cast the context pointer to an integer pointer.volatile int* edge_capture_ptr = (volatile int*) context;
//Read the edge capture register on the button PIO & Store value.*edge_capture_ptr= IORD_ALTERA_AVALON_PIO_EDGE_CAP(BUTTONS_BASE);
//Write to the edge capture register to reset it. IOWR_ALTERA_AVALON_PIO_EDGE_CAP(BUTTONS_BASE, 0);
// reset interrupt capability for the Button PIO. IOWR_ALTERA_AVALON_PIO_IRQ_MASK(BUTTONS_BASE, 0xf);
}
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NIOS II I t t E l ISR E d dNIOS II Interrupt Example ISR-Expandedstatic void handle_button_interrupts(void* context, alt_u32 id)
{
// cast the context pointer to an integer pointer// cast the context pointer to an integer pointer.volatile int* edge_capture_ptr = (volatile int*) context;
//Read the edge capture register on the button PIO & Store value.*edge_capture_ptr= IORD_ALTERA_AVALON_PIO_EDGE_CAP(BUTTONS_BASE);
//Write to the edge capture register to reset it. IOWR_ALTERA_AVALON_PIO_EDGE_CAP(BUTTONS_BASE, 0);
// reset interrupt capability for the Button PIO// reset interrupt capability for the Button PIO. IOWR_ALTERA_AVALON_PIO_IRQ_MASK(BUTTONS_BASE, 0xf);if ( *edge_capture_ptr == 1) // Check if the first button was pressed
LCDwrite("hello world\n");
if ( *edge_capture_ptr == 4) // Check if the 4th button was pressed{
IOWR(LEDS_BASE,0, (1 & 0xF)); // Write 1 to the LEDsusleep(1000000);IOWR(LEDS BASE 0 (0 & 0xF)); // Write 0 to the LEDsIOWR(LEDS_BASE,0, (0 & 0xF)); // Write 0 to the LEDs
}
}
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NIOS II I t t H dli P fNIOS II Interrupt Handling Performance
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PS/2 Keyboard
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Lab #3 Files on class web siteASCII-Map.pdf
Keyboard code to ASCII code mappingKB_ScanCode.v
Verilog file to read serial keyboard data to 8 bit parallel datadataImplementation details in Chapter 7.6 (textbook)
Scan2ASCII.mifScan2ASCII.mifMemory initialization file
Initialize ROM
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Keyboard Interface LogicSynchronous serial
Bidirectional data and clock• Converted to 8-bit ASCII
KeyboardInterfaceLogic
•Data xmission is synchronized w/ clock•Xmission starts when data is 0•Xmission stop bit (1) terminates transfer
Odd-Parity bit
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Keyboard Communication ModesKeyboard samples clock line every 60 uSecs
Checks the status of clock (if 0clock (if 0 cannot send) before sending
•Forces the clock signal to 0 for > 60 uSec•Done while preparing data •Then allows keyboard to drive clock to 1
•When system sends data to the keyboard, it forces the data line to 0 until the keyboard starts to clock the data stream
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Keyboard Commands
Keyboard Commands to System
System Commands to Keyboard
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Standard 104-keyStandard 104 key Keyboard
61
Keyboard Scan yCodes & ASCII Characters(ASCII-Map.pdf)
•Xmits Make codeWhen key pressed•Break code is 0xF0 followed by Make codewhen key is released
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KB_ScanCode.v
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Detect Start and Stop
•Uses fast system clock (~50Mhz)•Waits for KBData to become 0 then issues StartBitDetectedRemains 1 ntil Completed signal is recei ed•Remains 1 until Completed signal is received
•Completed signal comes from Data Bit Collection module
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Data Bit Collection
•Shift register that clocks data bits as they appear on KBDataon rising edge of KBClock
•Uses KBClock for this state machine•Waits for StartBitDetected, then cycles through Bit1-Bit8 states
•Data bits appear on KBData on rising edge of KBClock•When all bits have been detected, it goes to stop state
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Waiting For Key Release
•Waits for 0xF0 on ScanCode
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ASCII Conversion MemoryASCII Conversion Memory Initialization File (scan2ASCII.mif)
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