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Introduction to CMOS VLSI Design Lecture 3 Manufacturing & Layout David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh

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Page 1: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

Introduction to

CMOS VLSI

Design

Lecture 3

Manufacturing & Layout

David Harris, Harvey Mudd College

Kartik Mohanram and Steven Levitan

University of Pittsburgh

Page 2: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing2

The Manufacturing Process

For a great tour through the IC manufacturing process

and its different steps, check

http://www.fullman.com/semiconductors/semiconductors.html

Page 3: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 3

CMOS Fabrication

CMOS transistors are fabricated on silicon wafer

Lithography process similar to printing press

On each step, different materials are deposited or

etched

Easiest to understand by viewing both top and

cross-section of wafer in a simplified manufacturing

process

Page 4: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing4

oxidation

opticalmask

processstep

photoresist coatingphotoresistremoval (ashing)

spin, rinse, dryacid etch

photoresist

stepper exposure

development

Typical operations in a single

photolithographic cycle (from [Fullman]).

Photo-Lithographic Process

Page 5: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing5

CMOS Process at a Glance

Define active areas

Etch and fill trenches

Implant well regions

Deposit and patternpolysilicon layer

Implant source and drainregions and substrate contacts

Create contact and via windowsDeposit and pattern metal layers

Page 6: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing6

Patterning of SiO2

Si-substrate

Si-substrate Si-substrate

(a) Silicon base material

(b) After oxidation and depositionof negative photoresist

(c) Stepper exposure

Photoresist

SiO2

UV-light

Patternedoptical mask

Exposed resist

SiO2

Si-substrate

Si-substrate

Si-substrate

SiO2

SiO2

(d) After development and etching of resist,chemical or plasma etch of SiO

2

(e) After etching

(f) Final result after removal of resist

Hardened resist

Hardened resist

Chemical or plasmaetch

Page 7: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing7

Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

N Well Process

Page 8: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 8

Well and Substrate Taps

Substrate must be tied to GND and n-well to VDD

Metal to lightly-doped semiconductor forms poor connection called

Shottky Diode

Use heavily doped well and substrate contacts / taps

n+

p substrate

p+

n well

A

YGND V

DD

n+p+

substrate tap well tap

n+ p+

Page 9: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 9

Inverter Mask Set

Transistors and wires are defined by masks

Cross-section taken along dashed line

GND VDD

Y

A

substrate tap well tap

nMOS transistor pMOS transistor

Page 10: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 10

Detailed Mask Views

Six masks

– n-well

– Polysilicon

– n+ diffusion

– p+ diffusion

– Contact

– Metal

Metal

Polysilicon

Contact

n+ Diffusion

p+ Diffusion

n well

Page 11: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing11

Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

Page 12: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 12

Fabrication Steps

Start with blank wafer

Build inverter from the bottom up

First step will be to form the n-well

– Cover wafer with protective layer of SiO2 (oxide)

– Remove layer where n-well should be built

– Implant or diffuse n dopants into exposed wafer

– Strip off SiO2

p substrate

Page 13: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 13

Oxidation

Grow SiO2 on top of Si wafer

– 900 – 1200 C with H2O or O2 in oxidation furnace

p substrate

SiO2

Page 14: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 14

Photoresist

Spin on photoresist

– Photoresist is a light-sensitive organic polymer

– Softens where exposed to light

p substrate

SiO2

Photoresist

Page 15: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 15

Lithography

Expose photoresist through n-well mask

Strip off exposed photoresist

p substrate

SiO2

Photoresist

Page 16: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 16

Etch

Etch oxide with hydrofluoric acid (HF)

– Seeps through skin and eats bone; nasty stuff!!!

Only attacks oxide where resist has been exposed

p substrate

SiO2

Photoresist

Page 17: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 17

Strip Photoresist

Strip off remaining photoresist

– Use mixture of acids called piranah etch

Necessary so resist doesn’t melt in next step

p substrate

SiO2

Page 18: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 18

n-well

n-well is formed with diffusion or ion implantation

Diffusion

– Place wafer in furnace with arsenic gas

– Heat until As atoms diffuse into exposed Si

Ion Implanatation

– Blast wafer with beam of As ions

– Ions blocked by SiO2, only enter exposed Si

n well

SiO2

Page 19: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 19

Strip Oxide

Strip off the remaining oxide using HF

Back to bare wafer with n-well

Subsequent steps involve similar series of steps

p substrate

n well

Page 20: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing20

Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

Self Aligned

Gate:

Poly masks

the channel

Page 21: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 21

Polysilicon

Deposit very thin layer of gate oxide

– < 20 Å (6-7 atomic layers)

Chemical Vapor Deposition (CVD) of silicon layer

– Place wafer in furnace with Silane gas (SiH4)

– Forms many small crystals called polysilicon

– Heavily doped to be good conductor

Thin gate oxide

Polysilicon

p substraten well

Page 22: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 22

Polysilicon Patterning

Use same lithography process to pattern polysilicon

Polysilicon

p substrate

Thin gate oxide

Polysilicon

n well

Page 23: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 23

Self-Aligned Process

Use oxide and masking to expose where n+ dopants should be

diffused or implanted

N-diffusion forms nMOS source, drain, and n-well contact

p substraten well

Page 24: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 24

N-diffusion

Pattern oxide and form n+ regions

Self-aligned process where gate blocks diffusion

Polysilicon is better than metal for self-aligned gates because it

doesn’t melt during later processing

p substraten well

n+ Diffusion

Page 25: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 25

N-diffusion cont.

Historically dopants were diffused

Usually ion implantation today

But regions are still called diffusion

n wellp substrate

n+n+ n+

Page 26: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 26

N-diffusion cont.

Strip off oxide to complete patterning step

n wellp substrate

n+n+ n+

Page 27: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing27

Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

N well contactP substrate contact

Page 28: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 28

P-Diffusion

Similar set of steps form p+ diffusion regions for pMOS source and

drain and substrate contact

p+ Diffusion

p substraten well

n+n+ n+p+p+p+

Page 29: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 29

Contacts

Now we need to wire together the devices

Cover chip with thick field oxide

Etch oxide where contact cuts are needed

p substrate

Thick field oxide

n well

n+n+ n+p+p+p+

Contact

Page 30: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 30

Metalization

Sputter on aluminum over whole wafer

Pattern to remove excess metal, leaving wires

p substrate

Metal

Thick field oxide

n well

n+n+ n+p+p+p+

Metal

Page 31: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing31

CMOS Process Walk-Through

(j) After deposition and patterning of first Al layer.

Al

(k) After deposition of SiO2insulator, etching of via’s,

deposition and patterning ofsecond layer of Al.

AlSiO

2

Page 32: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing32

Advanced Metallization

Page 33: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing33

Advanced Metallization

Page 34: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 34

Layout

Chips are specified with set of masks

Minimum dimensions of masks determine transistor

size (and hence speed, cost, and power)

Feature size f = distance between source and drain

– Set by minimum width of polysilicon

Feature size improves 30% every 3 years or so

Normalize for feature size when describing design

rules

Express rules in terms of l = f/2

– E.g. l = 0.3 mm in 0.6 mm process

Page 35: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing35

Design Rules

Interface between designer and process engineer

Guidelines for constructing process masks

Unit dimension: Minimum line width▪ scalable design rules: lambda parameter

▪ absolute dimensions (micron rules)

Rules from▪ Manufacturing process (antenna rules)

▪ Final result (shorts/opens)

Could be▪ Electrical – maximum current

▪ Mechanical – surface planarity

▪ Thermal - overheating

▪ Optical – mask requirements

▪ Characterization – only some size transistors well characterized

Rules used to be 3 pages, now a book, soon worse…

Page 36: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 36

Simplified Design Rules

Conservative rules to get you started

Page 37: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 37

Inverter Layout

Transistor dimensions specified as Width / Length

– Minimum size is 4l / 2l, sometimes called 1 unit

– In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm

long

Page 38: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing38

CMOS Process Layers

Layer

Polysilicon

Metal1

Metal2

Contact To Poly

Contact To Diffusion

Via

Well (p,n)

Active Area (n+,p+)

Color Representation

Yellow

Green

Red

Blue

Magenta

Black

Black

Black

Select (p+,n+) Green

Page 39: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing39

Layers in 0.25 mm CMOS process

Page 40: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing40

Intra-Layer Design Rules

Metal24

3

10

90

Well

Active3

3

Polysilicon

2

2

Different PotentialSame Potential

Metal13

3

2

Contactor Via

Select

2

or6

2Hole

Minimum size, spacing rules

Page 41: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing41

Transistor Layout (inter layer rules)

1

2

5

3

Tra

nsi

stor

Page 42: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing42

Vias and Contacts

1

2

1

Via

Metal toPoly ContactMetal to

Active Contact

1

2

5

4

3 2

2

Page 43: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing43

Select Layer

1

3 3

2

2

2

WellSubstrate

Select3

5

well contactsubstrate contact

Page 44: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing44

CMOS Inverter Layout

A A’

np-substrate Field

Oxidep+n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A’

A A’

N well contactP substrate contact

N well contactP substrate contact

Page 45: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing45

Layout Editor (what is missing?)

Page 46: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing46

Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.

Page 47: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

EE141© Digital Integrated Circuits2nd Manufacturing47

Sticks Diagram

1

3

In Out

VDD

GND

Stick diagram of inverter

• Dimensionless layout entities

• Only topology is important

• Final layout generated by

“compaction” program

Page 48: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 48

Gate Layout

Layout can be very time consuming

– Design gates to fit together nicely

– Build a library of standard cells

Standard cell design methodology

– VDD and GND should abut (standard height)

– Adjacent gates should satisfy design rules

– nMOS at bottom and pMOS at top

– All gates include well and substrate contacts

Page 49: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 49

Example: Inverter

Page 50: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 50

Example: NAND3

Horizontal N-diffusion and p-diffusion strips

Vertical polysilicon gates

Metal1 VDD rail at top

Metal1 GND rail at bottom

32 l by 40 l

Page 51: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 51

Stick Diagrams

Stick diagrams help plan layout quickly

– Need not be to scale

– Draw with color pencils or dry-erase markers

Page 52: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 52

Wiring Tracks

A wiring track is the space required for a wire

– 4 l width, 4 l spacing from neighbor = 8 l pitch

Transistors also consume one wiring track

Page 53: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 53

Well spacing

Wells must surround transistors by 6 l

– Implies 12 l between opposite transistor flavors

– Leaves room for one wire track

Page 54: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 54

Area Estimation

Estimate area by counting wiring tracks

– Multiply by 8 to express in l

Page 55: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 55

Example: O3AI

Sketch a stick diagram for O3AI and estimate area

– Y A B C D

Page 56: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 56

Example: O3AI

Sketch a stick diagram for O3AI and estimate area

– Y A B C D

Page 57: Lecture 3 Manufacturing & Layout - University of Pittsburghkmram/1192-2192/lectures/ManufacturingLayout.pdf · 1: Circuits & Layout CMOS VLSI Design Slide 34 Layout Chips are specified

CMOS VLSI Design1: Circuits & Layout Slide 57

Example: O3AI

Sketch a stick diagram for O3AI and estimate area

– Y A B C D