lecture 3 - small signal analysis (2 spp pdf)
DESCRIPTION
2 slides per page copy (for clearer images)TRANSCRIPT
2/13/2012
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Small-signal Analysis EE 21 – Fundamentals of Electronics
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AC Small-signal analysis
• DC Analysis serves to establish the Q-point of the network
• The signal fed into an amplifier is AC
• Transistor network amplifies AC signal accordingly
• Actually, signal has AC and DC components, but we treat signal as AC only
• Small signal analysis: considers only small fluctuations / oscillations
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Two-port system
• Two pairs of terminals; one pair for input and one pair for output
• For CE configuration: input terminals are base & emitter, output terminals are collector & emitter (note the common-emitter)
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The four important parameters
• Measured at the terminals of the two-port system being considered (that is, the amplifier configuration only; external source and load impedances are NOT included)
• Input impedance, Zi
• Output impedance, Zo
• Voltage gain, Av
• Current gain, Ai
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Input impedance
• Impedance seen AT the input terminals
• Determines how much of the signal reaches the amplifier configuration
*Rs is a source resistance (or measuring equipment resistance)
5 i
ii
I
VZ
S
iSi
R
VVI
E
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Output Impedance
• Impedance at the output terminals with applied input signal set to 0.
• Determines how much current reaches the load
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S
Oi
R
VVI
O
OO
I
VZ
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Voltage gain
• Ratio of output to input voltage; measure of amplification
• No-load voltage gain: amplifier network only
• Voltage gain with respect to the source:
7
i
ONL
V
VAv
i
O
S
i
S
OS
V
V
V
V
V
VAv
Attenuation Factor (for presence of source Resistance)
No-load voltage gain
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Current Gain
• Ratio of output to input current
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Li
iO
ii
LO
i
Oi
RV
ZV
ZV
RV
I
IA
/
/
L
iNLi
R
ZAvA
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Bipolar Junction Transistor Models
• T-model
• π (hybrid-π) model
• H-model (re model)
• Discuss several models; networks will be analyzed using a combination of the three models; focus on CE configuration
• Assume large enough ro (output impedance of the transistor); ro is taken as the slope of the transistor’s output characteristics
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T-model
Recall the AC resistance of a diode:
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RIN
RIN
IB
DI
mVr
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T-model
• With equivalent diode resistance:
• Input resistance/impedance:
(gm – ‘transconductance’ factor)
(re – ‘transfer resistance’ factor)
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RIN
b
ee
B
beIN
i
ri
I
VR
1
e
b
ii
eIN rR 1
m
eg
r1
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Transconductance
• ‘Trans’ – involves a transfer/relationship between input and output terminals
• Conductance – quotient of I/V; inverse of resistance
• Other terms such as ‘transfer resistance’ or ‘transimpedance’ follow in the same manner
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π-model
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π-model
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rIV bbe eein rrrZ 1
r
VI be
B
ZIN
m
eg
r1
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π-model
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ZIN
mbe
e
beB
gV
r
VI
mbe
BC
gVII
mbeC gVI
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H-model (re model)
hie=
• Combines the T and pi models
• Involves 4 hybrid parameters: • hi-input resistance
• ho-output conductance
• hr-reverse transfer voltage ratio
• hf-forward transfer current ratio
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hfe IB
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Relationships between models
• One must be comfortable switching between transistor models
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eie rrh
QE
eI
mVr
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feh
AC Analysis of BJT CE Networks • DC analysis is first performed to determine
emitter current for re (The equations will be frequently used instead of the assumption IC = IE
• AC analysis involves:
• Remove DC sources and short out coupling capacitors at the input and output
• Relocate resistances according to their connections (input and output side)
• Bypass capacitors are replaced with shorts (assume working at critical frequencies) 18
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BE II 1 BE II
1
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BJT Fixed Bias
19
• AC analysis is started by removing the DC components and replacing capacitors with short equivalents
• Removal of components allows us to relocate RB and RC
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BJT Fixed Bias: AC Equivalent
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• Note that Vi is the input signal to the network; right after the capacitor.
• ro can be assumed large enough to permit the parallel combination ro//Rc ≈ Rc.
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BJT Fixed Bias: AC Analysis
• Input impedance:
• Output impedance:
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ieBi
eBi
hRZ
rRZ
//
//
CCoo RRrZ //
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BJT Fixed Bias: AC Analysis
• Voltage gain, Av:
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e
ib
r
VI
oCbO rRIV ||
oC
e
iO rR
r
VV ||
e
oC
i
O
r
rR
V
VAv
|| E
E 2
1 S
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BJT Fixed Bias: AC Analysis
• Current Gain, Ai:
23
eBCo
oB
i
Oi
rRRr
rR
I
IA
Co
obO
Rr
rII
eB
Bib
rR
RII
C
iNLi
R
ZAvA
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eB
B
i
Oi
rR
R
I
IA
Example: Fixed-bias circuit
• In the fixed-bias circuit, determine:
• re
• Zi, Zo, Av, Ai
• Repeat the solution with ro negligible.
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Emitter-Stabilized Bias
• Two cases:
• Bypassed RE
• Unbypassed RE
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Emitter Stabilized Bias: AC Equivalent Circuit - Bypassed
• Bypass capacitor shorts out emitter resistance; thus equivalent circuit (and corresponding quantities) is the same with the fixed bias circuit. 26
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Unbypassed emitter resistance
27 *Analysis of unbypassed circuit assumes negligible ro
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Unbypassed emitter resistance
28 *Reflected resistance shows βRe in the input circuit and only RE in the output side of the circuit Note: hie = βre
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Unbypassed RE
• Input impedance:
• Alternatively we can label
• Output impedance: (negligible ro)
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EieBi
EeBi
RhRZ
RrRZ
||
||
Co RZ
Eeb RrZ
EE
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Unbypassed RE
• Voltage gain
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CbCOO RIRIV Ee
ib
Rr
VI
C
Ee
iO R
Rr
VV
b
C
Ee
Cv
Z
R
Rr
RA
EE
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Unbypassed RE
• Current Gain: using Zb=(βre+βRE)
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bB
Bib
ZR
RII
BO II
bB
BiO
ZR
RII
bB
Bi
ZR
RA
C
iNLi
R
ZAvA
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DC significance of emitter resistance and AC significance of bypass capacitor
• DC analysis: the emitter resistance is added to improve the stability of the transistor amplifier; i.e. less sensitive to temperature
• The bypass capacitor is open during AC analysis
• AC analysis: presence of emitter resistance reduces voltage (significantly) and current gain
• Bypass capacitor shorts out the emitter resistance, hence increasing the amplifier’s voltage and current gain 32
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Example: Emitter-Stabilized Bias
• Determine:
(a) Zi and Zo
(b) Av
(c) Ai
(d) Repeat a,b, and c without including ro and the bypass capacitor.
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BJT Voltage Divider
• We will first consider only a voltage divider network with a bypassed emitter resistance
• Note: if ro is given, it can be ignored if the following condition is met:
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CO Rr 10
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BJT Voltage Divider: AC Equivalent circuit (Bypassed RE)
35
Note that the significant difference is simply the presence of an additional resistance at the input.
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BJT Voltage Divider: AC Analysis (Bypassed RE)
• Input impedance:
• Output impedance:
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ei rRRZ |||| 21
CoCO RrRZ ||
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BJT Voltage Divider: AC Analysis (Bypassed RE)
• Voltage gain
• Current gain: Let R’ = R1||R2 and applying CDR:
• The right equation is used when ro can be ignored.
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e
oCv
r
rRA
||
eeCo
oi
rR
R
rRRr
rRA
'
'
'
'
EE
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Unbypassed Emitter Resistance (ro disregarded)
38 Note: hie = βre
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Unbypassed Emitter Resistance (ro disregarded) • Input impedance
• Output impedance:
39
bi
Eei
ZRZ
RrRRZ
||'
|||| 21
CO RZ
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Unbypassed Emitter Resistance (ro disregarded) • Voltage Gain
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CbO RIV
Ee
i
b
ib
Rr
V
Z
VI
C
Ee
iO R
Rr
VV
Ee
Cv
Rr
RA
EE
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Unbypassed Emitter Resistance (ro disregarded) • Current Gain
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bO II
Ee
i
b
ibRrRR
RRI
ZR
RII
21
21
||
||
'
'
bEe
iZR
R
RrRR
RRA
'
'
||
||
21
21
C
iNLi
R
ZAvA
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Example: Voltage Divider Bias
• Ignoring ro, determine the input and output impedances as well as the voltage and current gains of the voltage divider network. Repeat without the bypass capacitor.
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Field Effect Transistor Model
• Recall: FET is a voltage-controlled device with a very high input impedance
• Transconductance: shows relationship between change in collector current corresponding to a change in gate-to-source voltage:
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gsmd VgI
gs
dm
V
Ig
Graphical interpretation
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Mathematical determination of gm
• Derivative: slope of the tangent line at a point
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.. ptQgs
d
ptQgs
dm
dV
dI
V
Ig
2
1p
gs
DSS
gs V
VI
dV
d
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Mathematical determination of gm
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P
GS
GSP
GSDSS
P
GS
GS
DSSV
V
dV
d
V
VI
V
V
dV
dI 1121
2
PP
GSDSS
VV
VI
1012
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Mathematical determination of gm
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P
GS
GSP
GSDSS
P
GS
GS
DSSV
V
dV
d
V
VI
V
V
dV
dI 1121
2
PP
GSDSS
VV
VI
1012
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Mathematical determination of gm
• Manipulating the previous equation to yield only positive values of gm:
• Maximum slope occurs when VGS = 0, thus:
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P
GS
P
DSSm
V
V
V
Ig 1
2
P
DSS
PP
DSSm
V
I
VV
Ig
201
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Mathematical determination of gm
• The equation for transconductance can thus be simplified to:
• Where
• Specification sheets often use notation yfs
• DC analysis is required to obtain gm at Q-point. 49
P
GSmm
V
Vgg 10
P
DSSm
V
Ig
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FET AC Equivalent circuit • gm : amplification factor (β in BJTs)
• rd : FET output impedance
• Measured using output characteristics
• Specification sheets use label yos and rd is taken as inverse
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FET AC Equivalent Circuit
• Removing rd yields a much manageble equivalent circuit:
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AC Analysis of FET networks
• DC analysis is performed to determine Q-point location, also for transconductance value (VGSQ is required in the equation for gm)
• AC analysis similar to BJT (relocation of resistances, determining of input and output impedances, etc)
• Equivalent circuits presented will include rd as a general illustration; can later be ignored
• Only gain considered in FET networks is voltage gain; current gain is undefined (why?)
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FET Fixed Bias
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FET Fixed Bias: AC equivalent
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Note the defined polarity of Vgs as it appears on the usual configuration. If Vgs becomes negative, the current source changes direction as well.
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FET Fixed Bias: AC Analysis
• Input impedance:
• Output impedance:
55
Gi RZ
DDdO RRrZ ||
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FET Fixed Bias: AC Analysis
• Voltage gain
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DdgsmO RrVgV ||
igs VV
DdimO RrVgV ||
DmDdmv RgRrgA || EE
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Example: JFET Fixed Bias
• For the JFET fixed bias circuit, determine the following:
• gm
• Zi and Zo
• Voltage gain, Av
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FET Self-bias
• Will be analyzed with and without bypass capacitor
• For unbypassed, rd will be removed (including rd is left as a reading assignment)
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FET Self-bias: bypassed RS
• Equivalent network with the source resistance bypassed by capacitor yields same equivalent circuit as that of the fixed bias circuit (thus with the same Zi, Zo, and Av)
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Unbypassed RS (rd removed)
60 Input impedance:
Gi RZ
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Unbypassed RS (rd removed)
• For output impedance, consider the circuit below, with Vi set to 0:
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Unbypassed RS (rd removed)
• Applying KCL:
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ODgsm IIVg
SDOgs RIIV )(
SDmSOmSDOmDO RIgRIgRIIgII )(
SmDSmO RgIRgI 11
DO II EE
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Unbypassed RS (rd removed)
• The output voltage is calculated as:
• The output impedance is defined by:
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O
OO
I
VZ
DODDO RIRIV
DO
O
DOO
RZ
I
RIZ
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Unbypassed RS (rd removed)
• For the voltage gain:
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0 RsGSi VVV
SDiGS RIVV
gsmD VgI
SgsmiGS RVgVV
Smgsi
Sgsmgsi
RgVV
RVgVV
1
EE
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Unbypassed RS (rd removed)
• Manipulating Vi and Vgs:
65
Sm
igs
Rg
VV
1
DgsmRO RVgVVD
D
Sm
im R
Rg
Vg
1
Sm
Dm
i
Ov
Rg
Rg
V
VA
1
EE
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Example: FET Self-bias
• Determine the following:
(a) gm
(b) Zi and Zo
(c) Av
(d) Output voltage if Vin is a sinusoidal 10mV.
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FET Voltage Divider
• Consider only the bypassed source resistance case
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FET Voltage divider AC equivalent
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Only difference from fixed-bias circuit is the input impedance Zi:
21 || RRZ i
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Systems Approach: Effects of source and load impedance
• Previous examples were solved using circuit analysis of corresponding transistor models; all gains were no-load gains
• Two-port system provides alternate solution to the same problem
• Solution varies slightly; two-port model is effective in inspecting effects of source and load impedance, which aren’t parts of the amplifier network
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2-port system model for transistor (both BJT and JFET) • Recall: Two-port system:
• Applying Thevenin’s theorem to the output side of the circuit yields the following:
, thus,
70
OTH ZZ
i
O
NLvV
VA ivNLOTH VAVE
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Two-port equivalent circuit
• Substituting the TEC yields the following circuit:
• This is the two-port model for any transistor amplifier network (the values used are Zi, Zo, and AvNL , which we know how to solve for)
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Effect of load impedance RL
• Load impedance has an effect on AC analysis—using two port model:
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Ii Io
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Effect of load impedance, RL
• Applying VDR:
73
Ii Io
LO
LiNLvO
RZ
RVAV
LO
L
NLvvRZ
RAA In general:
As the load resistance RL increases, the voltage gain increases.
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Effect of load impedance RL • Input impedance is not affected by RL
• However, the transistor 2-port system still provides the following equations:
• Where Av is the loaded voltage gain, Zi and Zo are parameters of the network, and RL the load impedance
74
i
i
i
ii
R
V
Z
VI
O
O
O
OO
R
V
Z
VI
L
ivi
R
ZAA
EE
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Example: Effect of RL
• Determine the voltage and current gain for the fixed-bias transistor amplifier using the two-port model and the circuit analysis done previously. Compare the obtained values.
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The AC load line
• Recall that in DC analysis a load line was drawn in a graph of the output characteristics
• Load resistance RL doesn’t contribute since it is isolated by a coupling capacitor
• The AC load line incorporates the load resistance RL , which is parallel to the collector resistance, that is:
76 LCL RRR ||'
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Th
e A
C a
nd
DC
load
lin
e
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Effect of signal source resistance RS • Not to be confused with FET source resistance, which
has the same label (most books also use Rs)
• Source resistance affects how much of the source signal reaches amplifier inputs; Rs may also come from bleeder resistors aside from signal sources
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Effect of source resistance RS
• By inspection,
• The voltage gain is thus altered as:
79
ivNLO VAV
iS
iSi
ZR
ZVV
Si
ivNL
S
OvS
RZ
ZA
V
VA E
E 2
1 S
lid
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(AA
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)
Effect of source resistance RS
• In addition, the input current is also altered since there is an additional resistor in series:
• Note: the parameters Zi and AvNL of a two-port system are unaffected by the internal resistance Rs. These are parameters of the transistor amplifier, which doesn’t ‘see’ Rs.
80
Si
ii
RZ
VI
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Example: Effect of RS
Consider the previous example, this time removing RL and assuming a source internal resistance of 500 ohms.
a. Determine the voltage gain Avs. Use the previously solved quantities of the transistor amplifier network.
b. What percent of the applied signal appears at the input terminals of the amplifier?
c. Determine the voltage gain Avs using the H/re model.
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Combined effect of RL and RS
• Note: the load and source impedances do not change the parameters of the transistor amplifier network (esp. using two-port analysis) but they are included in the entire circuit analysis (if solution using H-model is to be implemented).
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Combined effect of RL and RS
• At the input side:
• At the output side: (where Ro = Zo)
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Si
iSi
RZ
ZVV
OL
LvNLO
ZR
RAV
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Combined effect of RL and RS
• For the total voltage gain, AvS :
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S
i
i
O
S
OvS
V
V
V
V
V
VA
Si
i
OL
LvNL
S
OvS
RZ
Z
ZR
RA
V
VA
EE
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Combined effect of RL and RS
• The current gain can be solved using two equations:
, where
Where AvS is the total voltage gain (including the effects of both source and load resistances)
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L
ivi
R
ZAA
LO
LvNL
i
Ov
RZ
RA
V
VA
L
SivSSi
R
RZAA
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Example: Combined effects of Rs and RL
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• For the fixed-bias circuit, determine the total voltage gain AvS , loaded voltage gain Av = Vo/Vi, and the total current gain Ai using both formulas. The solved parameters of the transistor amplifier are as follows: Zi = 1.071kΩ, Zo=3kΩ, and AvNL = -280.11
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Generalizations of RS and RL effects
• RS and RL effects can easily be extended to the analysis of the other networks
• RS affects the voltage input, Vi, by voltage division; it also affects the input current, Ii, by increasing the series resistance
• RL adds a parallel resistance to the output side; it affects the voltage and current gains of the transistor amplifier
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Example: FET network
• Determine the voltage gain of the FET voltage divider network. The transconductance is given as 2.2 mS.
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Cascaded Systems
• Consists of transistor amplifier networks connected to each other
• Input impedance to succeeding network acts as the load impedance to the previous network when computing for its loaded gain Av, similar to effects of RL
• Note that effects of source resistance are applied as necessary 89
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Cascaded Systems
• Av1 , Av2 , … AvN are all loaded gains Vi/Vo of each individually analyzed network
• Total voltage gain:
Where
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ki
Okk VV
V
VAv
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Cascaded Systems
• Total current gain:
• If source resistance is present, previous equation can be applied:
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ZAA 1
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RZAA
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Decibel representation of gains
• Voltage gains can be represented in decibels:
• The total gain (in decibels) is the algebraic sum of individual decibel gains:
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i
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VAA log20log20)(
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Example 1. Determine the total voltage and current gains of the BJT-BJT cascaded amplifier.
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Example 1. Determine the total voltage gain of the FET-BJT cascaded amplifier. Repeat with the load resistance RL.
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