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Lecture 4: Instruction Set Architecture

ISA types, register usage, memory addressing, endian and alignment, quantitative evaluation

Reading: Textbook (5th edition) Appendix AAppendix B (4th edition)

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What Is ISA?Instruction set architecture is the structure

of a computer that a machine language programmer (or a compiler) must understand to write a correct (timing independent) program for that machine.

For IBM System/360, 1964

ISA types: Stack, Accumulator, and General-purpose registerISA is mature and stable Why do we study it?

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MIPS: A "Typical" RISC ISA32-bit fixed format instruction (3 formats)32 32-bit GPR (R0 contains zero, DP takes pair)3-address, reg-reg arithmetic instructionSingle address mode for load/store: base + displacement no indirection

Simple branch conditionsDelayed branch

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Example: MIPS Assembly Code

; C c o d e : ; c = ( a < = b ) ? ( a - b ) : ( b -a ) ;; a - - M E M ( 4 ) , b - - M E M ( 8 ) , c - -M E M ( 1 2 ); R 8 - - a , R 9 - - b , R 1 0 - - t m p , R 1 1 - - c

l w $ 8 , 4 ( $ 0 ) ; l o a d a t o r e g 8l w $ 9 , 8 ( $ 0 ) ; l o a d b t o r e g 9s l t $ 1 0 , $ 9 , $ 8 ; s e t r e g 1 0 i f b < ab e q $ 1 0 , $ 0 , + 2 ; n o , s k i p n e x t t w os u b $ 1 1 , $ 9 , $ 8 ; c = b - ab e q $ 0 , $ 0 , + 1 ; s k i p n e x ts u b $ 1 1 , $ 8 , $ 9 ; c = a - bs w $ 9 , 1 2 ( $ 0 ) ; s t o r e c

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MIPS Instruction Format (32-bit)

Op31 26 01516202125

Rs1 Rd immediate

Op31 26 025

Op31 26 01516202125

Rs1 Rs2

target

Rd Opx

Register-Register561011

Register-Immediate

Op31 26 01516202125

Rs1 Rs2 immediate

Branch

Jump / Call

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Example: MIPS Binary Code

100011_00000_01000_0000000000000100 // lw $8, 4($0) 100011_00000_01001_0000000000001000 // lw $9, 8($0)000000_01001_01000_01010_00000_101010 // slt $10, $9, $8 000100_01010_00000_0000000000000010 // beq $10, $0, +2 000000_01001_01000_01011_00000_100010 // sub $11, $9, $8 000100_00000_00000_0000000000000001 // beq $0, $0, +1000000_01000_01001_01011_00000_100010 // sub $11, $8, $9 101011_00000_01011_0000000000001100 // sw $9, 12($0)

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Stack ISA

Implicit operands on stackEx. C = A + BPush A

Push B

Add

Pop C

Good code density; used in 60’s-70’s; now in Java VM

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Accumulator ISA

The accumulator provides an implicit input, and is the implicit place to store the result.Ex. C = A + BLoad A

Add B

Store C

Used before 1980

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General-purpose RegistersGeneral-purpose registers are preferred by compilers Reduce memory traffic Improve program speed Improve code density

Usage of general-purpose registers Holding temporal variables in expression evaluation Passing parameters Holding variables

GPR and RISC and CISC RISC ISA is extensively used for desktop, server, and

embedded: MIPS, PowerPC, UltraSPARC, ARM, MIPS16, Thumb

CISC: IBM 360/370, VAX, and Intel 80x86

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Variants of GPR ArchitectureNumber of operands in ALU instructions: two or threeAdd R1, R2, R3 Add R1, R2

Maximal number of memory operands in ALU instructions: zero, one, two, or threeLoad R1, A Load R1, ALoad R2, B Add R3, R1, BAdd R3, R1, R2

Three popular combinations register-register (load-store): 0 memory, 3 operands register-memory: 1 memory, 2 operands memory-memory: 2 memories, 2 operands; or 3 memories, 3

operands

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Register-Memory ArchitectureThere is no implicit operandOne input operand is register, and one in memoryEx. C = A + BLoad R1, AAdd R3, R1, BStore R3, C

Processors include VAX, 80x86

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Register-Register (Load-Store)

Both operands are registersValues in memory must be loaded into a register and stored backEx. C = A + BLoad R1, ALoad R2, BAdd R3, R1, R2Store R3, C

Processors: MIPS, SPARC

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How Many Registers?If the number of registers increases:

Allocate more variables in registers (fast accesses) Reducing spill code Reducing memory traffic

Longer register specifiers (difficult encoding) Increasing register access time (physical registers) More registers to save in context switch

MIPS64: 32 general-purpose registers

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ISA and PerformanceCPU time = #inst × CPI × cycle time

RISC with Register-Register instructions Simple, fixed-length instruction encoding Simple code generation Regularity in CPI Higher instruction counts Lower instruction density

CISC with Register-memory instructions No extra load to accessing memory operands Easy encoding (?) Operands not equivalent Restricted #registers due to memory address encoding Irregularity in CPI

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Memory AddressingInstructions see registers, constant values, and memory

Addressing mode decides how to specify an object to access Object can be memory location, register, or a constant Memory addressing is complicated

Memory addressing involves many factors Memory addressing mode Object size byte ordering alignment

For a memory location, its effective address is calculated in a certain form of register content, immediate address, and PC, as specified by the addressing mode

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Little or Big: Where to Start?Byte ordering: Where is the first byte?Big-endian:IBM, SPARC, MororolaLittle-endian: Intel, DECSupporting both: MIPS, PowerPC

5678

876500000000

Big-endianLittle-endianNumber 0x5678

000000010000000200000003

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AlignmentAlign n-byte objects on n-byte

boundaries (n = 1, 2, 4, 8)

One aligned position, n-1 misaligned positionsMisaligned access is undesirable Expensive logic, slow referencesAligning in registers may be necessary for bytes and half words

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MIPS Data Addressing ModesRegisterADD $16, $7, $8

ImmediateADDI $17, $7, 100

DisplacementLW $18, 100($9)Only these three are supported for data

addressing

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Storage Used by CompilersRegister storage

Holding temporary variables in expression evaluation

Passing parameters Holding variables

Memory storages consists of Stack: to hold local variables Global data area: to hold statically declared

objects Heap: to hold dynamic objects

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Memory Addressing Seen in CISCDirect (absolute)Register indirectIndexedScaledAutoincrementAutodecrementMemory indirect

And more …

ADD R1, (1001)SUB R2, (R1)ADD R1, (R2 + R3) SUB R2, 100(R2)[R3]ADD R1, (R2)+SUB R2, -(R1)ADD R1, @(R3)(see textbook p-A9)

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Choosing Memory Addressing Modes

Choosing complex addressing modes Close to addressing in high-level language May reduce instruction count (thus fast) Increase implementation complexity (may

increase cycle time) Increase CPI

RISC ISA comes with simple memory addressing, and CISC ISA with complex ones

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Frequency of Addressing Modes?

Usage of address modes, VAX machine, SPEC89

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Usage of Immediate Operands In RISC

Alpha, SPEC CINT2000 & CFP2000

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Immediate Size in RISC

Alpha, SPEC CINT2000 & CFP2000; <6% are –ve; 50-70% fit in 8 bits; 75-80% in 16 bits

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Displacement Size in RISC

Displacement bit size: Alpha ISA, SPEC CPU2000 Integer and FP; most +ve; majority of large 14+ bits are –ve; about 1% of displacements need more than 16 bits.

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Operands size, type and formatIn MIPS Opcode encodes operand size Ex. ADD for signed integer, ADDU for unsigned integer,

ADD.D for double-precision FPMost common types include Integer: complement binary numbers Character: ASCII Floating point: IEEE standard 754, single-precision or

double-precisionDecimal format 4-bits for one decimal digit (0-9), one byte for two decimal

digits Necessary for business applications

Fixed Point format in DSP processors: Representing fractions in (-1, +1) 11000101fixed point= -0.10001012

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Dynamic Instruction Mix (MIPS)SPEC2K Int SPEC2K FP

Load 26% 15%Store 10% 2%Add 19% 23%Compare 5% 2%Cond br 12% 4%Cond mv 2% 0%Jump 1% 0%LOGIC 18% 4%FP load 15%FP store 7%FP others 19%

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Compiler Effects

Architectures change for the needs of compilers• How do compilers use registers? How many?• How do compilers use addressing modes?• Anything that compilers do not like?