lecture 41 - university of california,...
TRANSCRIPT
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Lecture 41: Introduction to Reconfigurable Computing
Michael Le, Sp07 Head TAApril 30, 2007
inst.eecs.berkeley.edu/~cs61cCS61C : Machine Structures
Slides Courtesy of Hayden So, Sp06 CS61c Head TA
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2CS61C L41 Intro to Reconfigurable Computing
Following the tech news traditionFollowing the tech news tradition……
NeuroSky of San Jose, CA aims to add more realistic elements to video games by using brain wave-reading technology to help game developers make gaming more realistic.
http://news.yahoo.com/s/ap/20070430/ap_on_hi_te/mind_reading_toys
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3CS61C L41 Intro to Reconfigurable Computing
OutlineOutline
Computing… What does it mean?Processor vs ASICFPGA-based Reconfigurable ComputingReal stuff
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4CS61C L41 Intro to Reconfigurable Computing
Back to basicsBack to basics……
What does the word “computer” mean to you?
Your $700 box sitting under your desk at home?The $2000 laptop you are using to check email right now?The 5-stage pipeline processor?
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5CS61C L41 Intro to Reconfigurable Computing
Informal DefinitionInformal Definition
A computer is a machine that computesadd, subtract, logical operations, decisions
What have we learned about computing in this semester?
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6CS61C L41 Intro to Reconfigurable Computing
Calculating Class Grades*Calculating Class Grades*grade = 0.1 × mt1 + 0.2 × mt2
+0.3 × hw + 0.4 × proj;
grade = 0;tmp = 0.1 × mt1;grade = grade + tmp;tmp = 0.2 × mt2;grade = grade + tmp;tmp = 0.3 × hw;grade = grade + tmp;tmp = 0.4 × proj;grade = grade + tmp;
Time
*This is not how we are going to calculate your grades
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7CS61C L41 Intro to Reconfigurable Computing
Computing Final Grade (2)Computing Final Grade (2)
0.1 mt1 0.2 mt2 0.3 hw 0.4 proj
× × × ×
+ +
+grade
Time
SPACE
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8CS61C L41 Intro to Reconfigurable Computing
2 Ways to Compute2 Ways to Compute
TIME
××××
+
++
Processor (CS61C)
Application Specific Integrated CircuitASIC (EE141)
×
0.1
mt1
tmp
grade
0.1
mt1
tmp
grade
clock cycle 1
+
0.2
mt2
tmp
grade
clock cycle 2
×
0.2
mt2
tmp
grade
clock cycle 3
+ +
0.4
proj
tmp
grade
0.4
proj
tmp
grade
clock cycle n
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9CS61C L41 Intro to Reconfigurable Computing
Processor Processor vsvs ASICASIC
Take longer to compute
slowFlexibleNeed instructions to determine what to do on each cycleSpace is bounded
Take shorter time to compute
fastNot FlexibleNo instruction
Same calculation every cycle
Space unboundedBranches?
Temporal Computing Spatial Computing
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10CS61C L41 Intro to Reconfigurable Computing
Visualizing Spatial ComputingVisualizing Spatial Computing
AMD Opteron 64-bit processor1MB L2 Cache
193 mm sq0.18 micron CMOS
89W @ 1.8GHz~3 Op / cycle (int op)
Full Custom ASIC4x4 Single Value Decomposition
3.5 mm sq90nm CMOS
34mW @ 100 MHz clock70 GOPS = 700 Op / cycle
Actual computation
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11CS61C L41 Intro to Reconfigurable Computing
Between Temporal & Spatial ComputingBetween Temporal & Spatial Computing
Temporal Spatial
SingleProcessor
ASIC
• Slow• Flexible
• Fast• Inflexible
ReconfigurableComputing
??
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12CS61C L41 Intro to Reconfigurable Computing
Reconfigurable ComputingReconfigurable Computing
No standard definition“Computing via a post-fabrication and spatially programmed connection of processing elements.”-John Wawrzynek Sp04
A computer that can RE-configure itself to perform computation spatially as needed
How often do we RE-configure?Coarse-grain? Fine-grain?
Example: FPGA
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13CS61C L41 Intro to Reconfigurable Computing
Introduction to the FPGAIntroduction to the FPGA
Field Programmable Gate ArrayBegan as ASIC replacements
ASIC that can be configured “in the field”At power up, configuration is loaded onto the chipChip acts as an ASIC until power down
Modern FPGA more like computersExploit dynamic, partial reconfigurationEmbedded processors
Xilinx, Altera are 2 major market leaders
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14CS61C L41 Intro to Reconfigurable Computing
The LUTThe LUTLUT: Lookup TableA direct implementation of a truth table
Recall a TT uniquely defines a circuit
An n-LUT implements any n-input combinational logic
Depends on LUT configuration
A B C D Q
0 0 0 0 00 0 0 1 0
…1 1 0 1 11 1 1 0 01 1 1 1 0
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15CS61C L41 Intro to Reconfigurable Computing
Making a 2Making a 2--LUT from Truth TableLUT from Truth Table
A B0 00 11 01 1
16 possible ways
4 configuration bits
OR
0111
TRUE
FALS
EAN
D
NAND
0 00 00 00 1
1 11 11 10 1
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22--LUT: CL and MUX BasedLUT: CL and MUX Based
0 0 0 0 0 0 00 0 0 0 0 1 00 0 0 0 1 0 00 0 0 0 1 1 00 0 0 1 0 0 00 0 0 1 0 1 0
1 1 1 1 1 0 11 1 1 1 1 1 1
cfg3
cfg2
cfg1
cfg0 A B Q
1
0
1
0
1
0
cfg0
cfg1
cfg2
cfg3
B A
Q
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LUTsLUTs in Real Lifein Real Life
3-LUT and 4-LUT are most commonSRAM basedLearn, and use, them a lot in CS150
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18CS61C L41 Intro to Reconfigurable Computing
Sequential logicSequential logicConnecting multiple LUTs gives us ANYcombinational logic we want to implementWe need Flip-Flop to build sequential circuits
FF are so important that they are included natively on FPGAs next to each LUTLUT + FF + … = LB (Logic Block)
clk
CLCL
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19CS61C L41 Intro to Reconfigurable Computing
Logic BlockLogic Block
Can build any 4-input circuitSynchronous OR Asynchronous
Combining Logic Blocks => ANY synchronous digital circuitHow to we build bigger circuit?
1
0LUT FF
D3D2D1D0
LUTCFG CLK MUXCFG
OUT
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20CS61C L41 Intro to Reconfigurable Computing
Routing of FPGARouting of FPGA
With enough smartness in placement and routing, we can implement any synchronous digital circuits!
LB LB LB LB
LB LB LB LB
LB LB LB LB
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Example: Example: XilinxXilinx Virtex2pro xc2vp70Virtex2pro xc2vp70
74,448 Logic Cells (LB)2 PowerPC cores328 18x18 bits multipliers5904 Kbytes on chip memory8 Digital Clock Managers996 I/O pins16 high speed serial I/O ports
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22CS61C L41 Intro to Reconfigurable Computing
Die Photo of a FPGADie Photo of a FPGA
Spartan-3 90nm CMOS
Entire Chip is for Computation
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23CS61C L41 Intro to Reconfigurable Computing
Real Stuff: BEE2Real Stuff: BEE2Developed at Berkeley
Berkeley Wireless Research Center
5 Xilinx xc2vp7040Gbytes DDR2 memoryUsed for research in:
WirelessAstro-Physics (SETI)BioinformaticsSpeech Recognition
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ConclusionConclusion
The Processor is NOT the only way to do computationReconfigurable computers allows different tradeoffs among speed, flexibility, cost, power, etcFPGA offers fine-grain reconfigurability