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Andrew R. NeureutherEECS 105 Microelectronics Devices and Circuits, Spring 2001

Topics:(finish Diffusion Current),Process Flow, Device Cross SectionsSheet Resistance, Counting Squares

Version 1/26/01

Reading: 2.6, 2.5.4 4.1.1, 4.5.7,6.2, 7.1.1, 7.7

Lecture 5, February 26, 2001

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W2 F L5: Silicon Physics

l Drift and diffusion currents (HS 2.4.2, 2.4.3)» Both holes and electrons drift and diffuse => four

current density components

l Process Flow with Layouts for Devices (HS 2.5.4 4.1.1, 4.5.7,6.2, 7.1.1, 7.7)» Generalize microfabrication in E40 to CMOS and

Bipolar

l IC Resistors (HS 2.6)» Sheet resistance and squares

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Mean Free Path Length and Diffusion

Mean free path length

Flux = # atoms/scm2

Current density = (charge) (flux)

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Diffusion Current Density

Jp Diff = (q/Aττc)[1/2 p(x =xr–λ) λλΑΑ –1/2 p(x =xr+λ) λλΑΑ]

Approx: p(x) = p(xr) + (dp/dx)(x- xr)

JpDiff = -q(λλ2/ ττc)(dp/dx) = -qDp(dp/dx) Fick’s Law

Diffusion constant Dp = (λλ2/ ττc) = (distance2/time)

EE 130 develops the Einstein relation that shows that the diffusion constant and the mobility are related by kT/q.

Dp = (kT/q)µµp

Both n and p contribute to the diffusion current J Diff = -qDp(dp/dx) + qDn(dn/dx)

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Total Current: Drift plus Diffusion

J = JDr + J Diff

JDr = (qpµµp + qnµµn)E

J Diff = -qDp(dp/dx) + qDn(dn/dx)

Two types of carriers n and p and two phenomena drift and diffusion give rise to

four current components.

Holes Electrons

Drift

Diffusion

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IC Process Flow and Layout

l Resistor (Figure 2.18)l MOS (Figure 4.1)l CMOS (Figure 4.27)l Diode (Figure 6.3)l Bipolar (Figure 7.1)l Lateral pnp Bipolar (Figure 7.6)

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Process Flow: NMOS => CMOS

1. Grow 500 nm of thermal SiO2 (field oxide) and pattern using Oxide (active area) mask

2. Implant phosphorous Nwell after selecting PMOS area with Nwellmask.

3. Grow 15 nm thermal SiO2 (gate oxide) 4. Deposit 500 nm polysilicon and pattern using Poly mask5. Implant arsenic (n-type) source/drain after protecting PMOS area

with Nwell’ mask6. Implant boron (p-type) source/drain after selecting PMOS area

with Nwell’’ mask7. Deposit 600 nm SiO2 (dielectric) and pattern using Contact Mask8. Sputter 1000 nm Al (metal) and pattern using Metal Mask

Simplified Flow

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MOS Device Cross Section

Fig. 2.19 and 4.1

Dielectric

Gate oxideField oxide

Poly

Metal

Source GateDrain

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Resistor: Process and Layout

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CMOS Cross Section

Fig. 4.27

What is wrong here?

Why the extra contact?

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Bipolar Layout

Fig. 7.1

Base

BaseEmitter

Collector

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Ohms Law

R= ρρ [L/(Wt)] = (1/σ) [L/(Wt)]

R = (1/tσσ) (L/W)

R = (sheet resistance) (layout squares)

R = (1/qNdµµnt)(L/W)

ρρ = 1/σσ = 1/(qpµp+qnµe)

V = RI

usual

general

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Typical Sheet Resistances

l Metal 0.01 Ω/squarel Polysilicon 10 Ω /squarel N+ source/drain doping 100 Ω/squarel Base pinch region 200 to 1000

Ω/squarel N-Well 10,000 Ω/square

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Resistor Design

Fig. 2.21

Contact

Drift

n-type

p-type substrate

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Corners and Terminations

Fig. 2.22

Inside shortcut

0.65 squares0.56 squares

Extra paths

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Typical Process Variations

l Linewidth 3σ = 10%l Film Thickness 3σ = 6%l Doping 3σ = 3%l Mobility 3σ = 1%l Layout Length 3σ = 1%

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Impact of Process Variations

R = (1/qNdµµnt)(L/W)l W = W (1 + εw)l T = t (1 + εt)l Nd = Nd (1 + εN)

l µµn = µµn (1 + εu)

l L = L (1 + εL)

Substitute these expansions, keep first order terms, and bring them all to the numerator.

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Worst Case: Coherent

l Assume min/max 3σ level

l RMAX= R0 (1+| εw |+| εt |+| εN |+| εu |+| εL |) = 1.21

l RMIN = R0 (1-| εw |-| εt |-| εN |-| εu |-| εL |) = 0.79

l ε terms 0.10 + 0.06 + 0.03 + 0.01 + 0.01 = 0.21

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Random Case: IND

l Assume independently normally distributed, then take square root of the sum squares of variations

εεR = sqrt(εεw2 + εεt

2 + εεN2 + εεu

2 + εε2L)

εεR = sqrt(0.102 + 0.062 +0.032 +0.012 +0.012 ) = 0.12

3 εεR range is 0.88 to 1.12

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Geometrical Design Rules

n-well

poly

silic

on

active

1

1

2

3

2

1

metal

act

ive

polysilicon

contact-to-active