lecture 6: universal gates cse 140: components and design techniques for digital systems fall 2014
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Lecture 6: Universal Gates CSE 140: Components and Design Techniques for Digital Systems Fall 2014 CK Cheng Dept. of Computer Science and Engineering University of California, San Diego. Combinational Logic: Other Types of Gates. Universal Set of Gates Other Types of Gates XOR NAND / NOR - PowerPoint PPT PresentationTRANSCRIPT
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Lecture 6: Universal Gates
CSE 140: Components and Design Techniques for Digital Systems
Fall 2014
CK Cheng
Dept. of Computer Science and Engineering
University of California, San Diego
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Combinational Logic: Other Types of Gates
Universal Set of Gates Other Types of Gates
1) XOR2) NAND / NOR3) Block Diagram Transfers
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Universal Set of Gates: Motivation
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AND, OR, NOT: Logic gates related to reasoning from Aristotle (384-322BCE)
NAND, NOR: Inverted AND, Inverted OR gates. VLSI technologies. All gates are inverted.
Multiplexer + input table: FPGA technology. Table based logic for programmability.
XOR: Parity check
In the future, we may have new sets of gates due to new technologies.Given a set of gates, can this set of gates cover all possible switching functions?
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Universal Set
Universal Set: A set of gates such that every switching function can be implemented with the gates in this set.
Examples
{AND, OR, NOT}
{AND, NOT}
{OR, NOT}
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Universal Set
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Universal set is a powerful concept to identify the coverage of a set of gates afforded by a given technology.
If the set of gates can implement AND, OR, and NOT gates, the set is universal.
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Universal Set
Universal Set: A set of gates such that every Boolean function can be implemented with the gates in this set.
Examples
{AND, OR, NOT}
{AND, NOT} OR can be implemented with AND & NOT gates a+b = (a’b’)’
{OR, NOT} AND can be implemented with OR & NOT gates ab = (a’+b’)’
{XOR} is not universal
{XOR, AND} is universal 6
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iClicker
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Is the set {AND, OR} (but no NOT gate) universal?A.YesB.No
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iClicker
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Is the set {f(x,y)=xy’} universal?A.YesB.No
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{NAND, NOR}
{NOR}
{XOR, AND}
X ⊕ 1 = X*1’ + X’*1 = X’ if constant “1” is available.
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Other Types of Gates: Properties and Usage
1) XOR X ⊕ Y = XY’ + X’YIt is a parity function (examples)Useful for testing because the
flipping of a single input changes the output.
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X Y
XY’ X’Y
id x y x ⊕ y
0 0 0 0
1 0 1 1
2 1 0 1
3 1 1 0
x=0 x=1
y=0 0 1
y=1 1 0
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Other Types of Gates: Properties and Usage
(a) Commutative X ⊕ Y = Y ⊕ X(b)Associative (X ⊕ Y) ⊕ Z = X ⊕ (Y ⊕ Z)(c) 1 ⊕ X = X’, 0 ⊕X = 0X’+ 0’X = X(d)X ⊕ X = 0, X⊕X’ = 1
1) XOR X ⊕ Y = XY’ + X’Y
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X Y
XY’ X’Y
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e) If ab = 0, then a ⊕ b = a + bProof: If ab = 0, then a = a (b+b’) = ab+ab’ = ab’
b = b (a + a’) = ba + ba’ = a’b
a+b = ab’ + a’b = a ⊕ b
f) f(x,y)=x ⊕ xy’⊕ x’y ⊕ (x + y) ⊕ x= ?(Priority of operations: AND, ⊕, OR)
Hint: We apply Shannon’s Expansion.
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Shannon’s Expansion (for switching functions)
Formula: f (x,Y) = x * f (1, Y) + x’ * f (0, Y)
Proof by enumeration:If x = 1, f (x,Y) = f (1, Y) : 1*f (1, Y) + 1’*f(0,Y) = f (1, Y)
If x = 0, f(x,Y) = f (0, Y) : 0*f (1, Y) + 0’*f(0,Y) = f(0, Y)
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Back to our problem…
Simplify the function f(X,Y) = X⊕XY’⊕X’Y⊕(X+Y)⊕X
Case X = 1: f (1, Y) = 1 ⊕ Y’⊕ 0 ⊕ 1 ⊕ 1 = YCase X = 0: f (0, Y) = 0 ⊕ 0 ⊕ Y ⊕ Y ⊕ 0 = 0
Thus, using Shannon’s expansion, we havef (X, Y) = Xf(1,Y)+X’f(0,Y)= XY
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XOR gates
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iClicker: a+(b⊕c) = (a+b)⊕(a+c)?A.YesB.No
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2) NAND, NOR gates
NAND, NOR gates are not associative
Let a | b = (ab)’
(a | b) | c ≠ a | (b | c)
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3) Block Diagram Transformation
a) Reduce # of inputs.
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b. DeMorgan’s Law
(a+b)’ = a’b’
(ab)’ = a’+b’
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c. Sum of Products (Using only NAND gates)
Sum of Products (We create many bubbles with NOR gates)
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d. Product of Sums (NOR gates only)
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We will create many bubbles with NAND gates.
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NAND, NOR gates
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Remark:Two level NAND gates: Sum of ProductsTwo level NOR gates: Product of Sums
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Part II. Sequential Networks
Memory / Timesteps
Clock
Flip flopsSpecificationImplementation
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Reading
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[Harris] Chapter 3, 3.1, 3.2