Jaeyong Chung

System-on-Chips (SoC) Laboratory

Incheon National University

Digital Integrated Circuits

Lecture 7

Image Filtering

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More examples : http://lodev.org/cgtutor/filtering.html

BlurOriginal Find Edges Sharpen

Filter coefficients: Kernel

0 0.2 00.2 0.2 0.20 0.2 0

−1 −1 −1−1 8 −1−1 −1 −1

−1 −1 −1−1 9 −1−1 −1 −1

Real numbers in binary

Decimal fraction to binary

Continually multiply the fraction number by 2 until the

fractional part of the result = 0 or the required precision has

been reached. The integers from the solution:

Convert 0.8125 into binary

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Floating-point representation

Real numbers can be represented in either floating-

point or fixed-point format

Floating-point format

IEEE754 Standard

32-bit single precision/ 64-bit double precision

Floating-point hardware is complicated

Require large area and power consumption

Fixed-point format is often preferred for digital signal

processing

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Fixed-point representation

Binary numbers are integer fixed-point representation

Suffer from possible overflow & scaling problems

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Fixed-point representation

Called Q format

Qm.n notation

m bits for integer portion

n bits for fractional portion

Total number of bits N = m + n + 1, for signed numbers

Example: 16 bit number (N=16) and Q2.13 format

2bits for integer portion

13bits for fractional portion

1 signed bit (MSB)

Special cases:

16-bit integer number (N=16) => Q15.0 format

16-bit fractional number (N=16) => Q0.15 format; a.k.a.,

Q.15 or Q15

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Bit-width of integer parts

Range Analysis

Examples

3.45

-4.00

-4.01

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Bit-width of integer parts

n bit X m bit

(n+m) bit for signed and unsigned

n bit + m bit

max(m,n)+1 for signed and unsigned

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Fixed Point Arithmetic - Multiplication

9

Integer Fractional

l

Integer Fractional

m

?

FractionalInteger

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Fixed Point Arithmetic - Addition

10

Integer Fractional Integer Fractional

?

Fractional

l m

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Examples

Q8.0 X Q0.8

Q8.8 + Q8.8

Q9.8 + Q8.8

Q10.4 + Q10.8

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Binary point alignment

Example: Y (Q4.5) = A (Q2.5) + B (Q3.2)

Zero-padding (Recommended)

Y = A + {B, 3’b0};

Part select

Y = {A[7:3]+B, A[2:0]};

Shift

Y = A + (B<<3);

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Round-off schemes

Example: A (Q5.6) -> Y (Q5.4)

Truncation

Y = Q[11:2];

Round to nearest (Rounding)

t = Q + (1<<1);

Y = t[11:2];

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Signed Arithmetic

Signed adder = Unsigned adder

Signed multiplier != Unsigned multiplier

Method 1 (Bad QoR)

Method 2 (Good QoR)

Unsigned to Signed

$signed({1’b0, a})

4’sb1011 // signed constant

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input [7:0] a,b;output [15:0] z;

assign z = {{8{a[7]}, a[7:0]} * {{8[b[7]}, b[7:0]};

input signed [7:0] a,b;output signed [15:0] z;

assign z = a* b;

Constant real number in Verilog

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Same Q format for all numbers?

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Uniform fractional bit-widths

Use the same Qm.n format for all numbers

No binary point alignment is needed

Multiplication results (Q2m.2n) needs to be

rounded into Qm.n back

m=0 may be preferred for this reason

Non-uniform fractional bit-widths

Better area and power

Q0.n = Qn

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Fractional Fixed-Point Representation

Fractional number range is between 1 and -1

Multiplying a fraction by a fraction always results

in a fraction and will not produce an overflow (e.g.,

0.99X0.9999 less than 1)

Successive additions may cause overflow

Saturation addition

Adjust filter coefficients

RGB2YCbCR Color Converter

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RGB2YCbCR Color Converter

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2D Convolution

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2D Convolution

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2D Convolution

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Raster

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pixel_in pixel_out

Image Filter

Line buffers

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Reconfigurable Pipelined 2D Convolvers for Fast Digital Signal Processing, B. Bosi et al

Line buffers

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Reconfigurable Pipelined 2D Convolvers for Fast Digital Signal Processing, B. Bosi et al

A generic PxQ 2D Convolution hardware

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DESIGN AND IMPLEMENTATION OF A 2D CONVOLUTION CORE FOR VIDEO APPLICATIONS ON FPGAs, Benkrid and Belkacemi