lecture: integration of silicon photonics with electronics · lecture: integration of silicon...
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Lecture: Integration of silicon photonics with electronics
Prepared by Jean-Marc FEDELICEA-LETI
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Context
The goal is to give optical functionalities to electronics integrated circuit (EIC)The objectives are either:
Increase the performance of photonics with embedded electronic
Increase the data transmission speed between cores with photonics
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Minimum impact on EIC designer librairiesDevelopment of a specific designer CMOS libraries require a huge effort (€€). So integration of optical components requires minimum change of a design library
Wafer testability with high throughput Optical devices on a EIC chip have to be tested with the same procedures as electronic devices. So full wafer testability without any dicing, polishing, assembly
Lowest added process complexityThis is an issue related to yield, so cost (€)
Some goals
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Integration of Si Photonics on EIC ??
FE:Front end
Si substrate
TransistorsM1
Mn
Pads
BE: Back end
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Die flip-chip solution
Silicon substrateSiO2 BOX
Silicon substrateSiO2 BOX
SourcePD e=3µm
Die substrate
Photonic wafer fabrication
Flip chip bonding on CMOS dies or wafer
• Not a wafer level fabrication• Uncompatibility with microelectronics packaging• Could be a good solution for low volume
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KOTURA example
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Integration of photonics on CMOS
Option 2Combined front-end fabrication
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Combined fabrication
Micro-electronicsBulk Technologies (CMOS, BiCMOS, SiGe, etc…)SOI Technology evolution: thin Si upper layer ≈ 55nm on BOX≈145nm
PhotonicsSOI wafers with Si≈200 to 400nm on BOX> 1µm
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Which substrate for combined fabrication?
SOI photonicsAdapt electronics library to thicker box
Dedicated area for photonics and electronics
Cost ?
Buried thick BOX on a bulk substrate
Cost and quality?
photonics BOX
Si Substrate
Si upper layer
photonics BOX
photonics area
electronics BOX
SOI electronics area
Bulk electronics area
photonics BOX
photonics area
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Proprietary SOI CMOS 130nm technologyProprietary library for IC designFlip chip bonded lasers or external WDM lasersSurface gratings fiber couplersMUX and DEMUX with controlled MMI10Gb/s modulator based on lateral Si depletion20GHz Ge photodetectorsElectronic control of optical devices
Option 2: Luxtera approach
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Option 2: Combined fabrication( Luxtera)
• SOI ?• WG width and thickness?• Pitch of the grating?• Partial etching for the grating?
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Option 2: Combined fabrication( Luxtera)
The gray-scale gradient in the figure indicates that the doping density varies laterally from low doping at the junction to high doping at the contact region. This design is the result of a tradeoff between minimizing optical insertion loss due to the presence of free carriers overlapping the optical mode (desire for low doping density) and minimizing the series resistance of the diode (desire for high-doping density). LUXTERA
MODULATOR
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Option 2: Combined fabrication( Luxtera)
• Ge epitaxy in a CVD environment is, usually, naturally selective to oxide
• When it comes to choose the insertion point of the Ge epitaxy stepwithin a CMOS process, several factors must be considered: the temperature profile of the process, the possibility to contact the Ge device using the standard Si contact module, the salicide sensitivity to thermal treatments, the availability of a clean Si surface, the presence of dielectric films and their interaction on the selective growth of Ge.• All these requirements may differ among different technology nodes
(Luxtera)
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Lightwire
Integration of on optical modulator
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15Silicon Photonics –PhD course prepared within FP7-224312 Helios project
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MIT Eos1 65 nm test chip
Texas Instruments standard 65 nm bulk CMOS processFirst ever photonic chip in sub-100nm CMOSAutomated photonic device layoutMonolithic integration with electrical modulator drivers
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Ring modulator
Paperclips
Waveguide crossings
M-Z test structures
Digital driver
4 ring filter banks
Photo detector
Two-ring filter
One-ring filter
Vertical coupler grating
MIT Eos1 65 nm test chip
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Waveguide made of polysiliconSilicon substrate under waveguide etched away to provide optical cladding64 wavelengths per waveguide in opposite directions
SEM image of a poly silicon waveguideCross-sectional view of a photonic chip
MIT Eos1 65 nm test chip
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Option 1: Integration above metallization
Photonic layer at the last levels of metallizations with back-end fabrication
• 1A: Wafer bonding of PIC processed at high temperature on SOI• 1B: Back-end fabrication of PIC at low temperature
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Option 2B with low T°c technology
SourcePD
SourcePD
SiN or a:Si Waveguide formation with SiO2 claddingBonding InP dies
Fabrication of source and PDConnection with EIC through passivation layers
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SiNx waveguides at low temperature
Si3N4
Fabrication at 350°C, Cladding with SiO2
Devices @1.3µm Losses
Waveguide (0.4µm x 0.8µm) 2 dB/cm
Bend (R≈25µm) 0.02 dB/90°µbend
Y junction 1.1 dB
1 => 2 MMI 0.5 dB (∆E<0.2dB)
1 => 4 MMI 1.4dB (∆E<0.45dB)
1 to 16 distribution network ∆E<0.5dB
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Option 1: Integration above metallization
Photonic layer at the last levels of metallizations with back-end fabrication
• 1A: Wafer bonding of PIC processed at high temperature on SOI• 1B: Back-end fabrication of PIC at low temperature
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Electronic-Photonic Integration
CMOS wafer planarized Deposition of SiO2 layer for bonding
CMOSwafer
transistorsmetal interconnects
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Rib Silicon Photonic layer
SOI 400nm / 2000 nmLitho FC + transition Rib strip : Rib Waveguide definitionSi etching 180nm
FC
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Stripe Silicon Photonic layer
Litho Passive 220nm: AWG, RR, etc….: Stripe Waveguide definitionSi etching 220nm
FC AWG
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Modulator Processing
Lithos for implantationDifferent implantations
FC Modulator AWG
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Ge photodetector Processing
Cavity formationGe epitaxy in cavityP & N Implant
FC Modulator AWG Ge PD
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Planarization
SiO2 deposition 1µmPlanarization
FC Modulator AWG Ge PD
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Molecular wafer bonding
Alignement of the two wafers (+-2µm)Molecular bonding of photonic wafer on CMOS wafer
CMOSwafer
transistorsmetal interconnects
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31Silicon Photonics –PhD course prepared within FP7-224312 Helios project
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Substrate removal
Mechanical grindingSi chemical etching
CMOSwafer
transistorsmetal interconnects
FC Modulator AWG Ge PD
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InP heterostructure bonding
CMOSwafer
transistorsmetal interconnects
FC Modulator AWG Ge PD
bond small InP dice with herostructure on waferInP substrate removal of dice
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InP heterostructure process
CMOSwafer
transistorsmetal interconnects
FC Modulator AWG Ge PD
Process InP source (InP etching)Planarized with SiO2
InP source
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Vias formation
CMOSwafer
transistorsmetal interconnects
FC Modulator AWG Ge PD
Lithos for different depthsEtching SiO2
InP source
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Metal formation
CMOSwafer
transistorsmetal interconnects
FC Modulator AWG Ge PD
Metal depositionMetal etching
InP sourcePAD
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SOI wafer bonded on a CMOS wafer
Silicon rib waveguide
Germanium
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Monocristalline rib waveguide with Ge in cavity
Silicon rib waveguide
Ge cavity
Silicon
Metallisations
SiO2
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Photonic wafer metallic bonded on EIC wafer
Silicon substrateSiO2 BOX
Silicon substrateSiO2 BOX
Photonic wafer
SourcePD
Photonic functions with high temp technology Die to wafer source bonding
Planarized electrodes formationSubstrate removal Metallic bonding
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Wafer bonding Cu/Cu of CMOS with SOI photonics
-0,1 0,0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1,0 1,1-0,01
0,00
0,01
0,02
0,03
0,04
0,05
0,06
0,07
0,08
I(Ampere)
V(Vo
lt)
Process independantly SOI photonics wafer and CMOS waferFinish with Cu pad interfaceCu-Cu bond at low temperature the two wafersRemove the SOI photonics substrateContact on the electronics pad by the top surface is not easy
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Photonic wafer thinned bonded on EIC wafer with TSV
Photonic wafer
SourcePD
Die to wafer source bondingActive device fabrication
Bonding a handle wafer and thinning the PIC substrate
Bonding EIC with PICRemoval of the handle waferThrough Silicon Vias formation
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Option 1A approachs
MIT technologyConcept of BE technology with SiGe
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Integration of a photonic layer by IBM
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IBM 2
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IBM 3
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Integration HP Labs
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Integration of photonics on CMOS
BE: Back end FE:Front end
Option 2Combined front-end fabrication
Option 1Photonic layer at the last levels of metallizations with back-end fabrication
Option 3Backside fabrication
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Option 3: Low T°C fabrication on the back side
InGaAsPDa:Si Waveguide on backside of CMOS wafer Fab of InP components
Connection with CMOSthrough the substrate
Si SubstrateSi SubstrateSi Substrate
• Fabrication of the EIC• Protection of the Front side• Process of the Back side (needs double side polished)•Low temperature technology for photonics components
• a:Si wg• InP laser• InGaAs photodetectors• Vias through the Si substrate
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Option 3: Wafer bonding on the back side
• Fabrication of the EIC• Protection of the Front side• Fabrication of the PIC• Wafer bonding of an PIC on the rear side of an EIC• Removal of the Si substrate of the PIC• Vias through the Si substrate (TSV)
Si Substrate
Si SubstrateSi Substrate Si Substrate
Silicon Photonics –PhD course prepared within FP7-224312 Helios project
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Conclusion
No unique integration technology
Need of integration depends on the targeted
applications
Hybrid technology for small volume
Full integration for medium to large volume
Integration of exotic materials possible with AIC
Silicon Photonics –PhD course prepared within FP7-224312 Helios project