lecture no. 14 combinational functional devices svbitec.wordpress.com
TRANSCRIPT
Lecture No. 14
Combinational Functional Devices
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Digital Logic &Design
Vishal Jethva
Lecture 14
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Recap
Odd-Prime Number Detector Circuit Using Quine-McCluskey Method
Combinational Logic Implemented in SOP and POS form Design and Implementation Steps Timing Diagram Active High/Low inputs/outputs
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Odd-Parity Function
Input Output Input Output
D3 D2 D1 D0 P D3 D2 D1 D0 P
0 0 0 0 1 1 0 0 0 0
0 0 0 1 0 1 0 0 1 1
0 0 1 0 0 1 0 1 0 1
0 0 1 1 1 1 0 1 1 0
0 1 0 0 0 1 1 0 0 1
0 1 0 1 1 1 1 0 1 0
0 1 1 0 1 1 1 1 0 0
0 1 1 1 0 1 1 1 1 1
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SOP Expression SImplification
D3D2\D1D0
00 01 11 10
00 1 0 1 0
01 0 1 0 1
11 1 0 1 0
10 0 1 0 1
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Simplifying Expression
DCBADCBAABCDDCABDBCADCBACDBADCBA
)()()()( DCDCBACDDCABDCDCBACDDCBA
)()()()( DCDCBADCDCBACDDCABCDDCBA
))(())(( BABADCDCABBACDDC
))(())(( BADCBADC )( YXXYYX
)()( DCBA
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Odd-Parity Generator Circuit
A
DC
B P
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Operation of Odd-Parity circuit
A
B
C
D
P
t0 t1 t2 t3 t4 t5 t6 t7 t8
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XOR & XNOR Gates
XOR function
XNOR function
BABA
ABBA
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XOR Gate
A
BF
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XNOR Gate
A
BF
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Combinational Functional Devices
Comparators BCD to 7-Segment Parity Generator Circuit
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Half & Full Adders
Half Adder Full Adder
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Half & Full Adders
A
B
Cout
Inpu
t Bits
Out
put B
its
Half-Adder
A
B
Cin
CoutIn
put B
its
Out
put B
its
Full-Adder
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Half-Adder
Function Table Expression Logic Circuit
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Half-Adder Function Table
Input Output
A B Sum Carry Out
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
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Half-Adder Circuit
A
B
Cout
BABABASum ABCarryOut
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Full-Adder
Function Table Expression Logic Circuit
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Full-Adder Function Table
Input Output
A B Carry In (C)
Sum Carry Out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1svbitec.wordpress.comsvbitec.wordpress.com
Sum Expression
ABCCBACBACBASum
)()( BCCBACBCBASum
)()( CBACBASum
CBASum
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Carry Out Expression
ABCCABCBABCACarryOut
)()( CCABBABACCarryOut
ABBACCarryOut )(
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Full-Adder Circuit
A
B
Cout
C
CBASum ABBACCarryOut )(
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Full-Adder
Full-Adder = Half-Adder + Half-Adder
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Full-Adder based on Two Half-Adders
A
B
Cout
Half-Adder
A
B
Cout
Half-Adder
Cin
A
B
Cout
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Parallel Binary Adder
Multiple Single bit Full-Adder connected in Parallel
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4-bit Parallel Adder
ABC
in
Cou
t
ABC
in
Cou
t
ABC
in
Cou
t
ABC
in
Cou
t
A0B0A1B1A2B2A3B3
S0S1S2S3Cout
0
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Carry Propagation
Carry Ripple Look-Ahead Carry Circuits
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Look-Ahead Carry Circuit
A
B
Cout
Cin
P
G
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Sum & Carry Expressions
CPSum
GCPCarryOut
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Carry Expressions
0100112 CPPGPGC
0001 GPCC
100011112 )( GGPCPGPCC
0321003211322334 CPPPPGPPPGPPGPGC
nnn BAP nnn BAG
201001122223 )( GCPPGPGPGPCC
02100211223 CPPPGPPGPGC
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Look-Ahead Carry Generator
A0
B0
P0
G0
A1
B1
P1
G1
A2
B2
P2
G2
A3
B3
P3
G3
Look-AheadCarry
Generator
C0
P0
C0
S0
P1
C1
S1
P2
C2
S2P2
C2
S3
P3
C3
C4svbitec.wordpress.comsvbitec.wordpress.com
MSI-Adders
74LS83A 74LS283 16-pin ICs 4-bit A input 4-bit B input 4-bit Sum output 1-bit Carry in 1-bit Carry Out
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12-bit Parallel Adder
74LS283
Sum (8-11)
A (8-11) B (8-11)
74LS283
Sum (4-7)
B (4-7)
74LS283
Sum (0-3)
B (0-3)A (4-7) A (0-3)
C0=0C4C8C12
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