lecture notes on photonics and optoelectronics vol. 1, no

Cmos Ic Layout Design: 7- Segments Counter

Teen Soh Hong and Lee Sin Yin

Tunku Abdul Rahman University College

Email: [email protected], [email protected]

Abstract—This paper discusses the design of an IC

layout for 7-segment counter. The layout was designed by

using Electric VLSI Design System as Electronic Design

Automation (EDA) tool. In order to produce the layout,

the fabrication process of Integrated Circuit (IC) was

further explored to ensure the layout could be

successfully drawn. The complete layout of the counter

was designed based on the schematic circuit which

consists of a few JK flip-flops. The layout had undergone

Design Rule Check (DRC) set by the Electric VLSI

Design System to check for any design rule error. Both

layout and schematic circuit of the counter were then

simulated through Layout versus Schematic (LVS) to

ensure they were identical. The simulation outputs of the

counter indicated that result of the layout and schematic

circuit were not ideal due to noises occurred in JK flip-

flops.

Index Terms—7-segments counter, schematic circuit,

IC layout, electric VLSI design system, DRC, LVS,

simulation output

I. INTRODUCTION

Electronic devices have been widely used in many

different fields and the size of these devices had been

gradually reduced. For example, nowadays, the mobile

phones are small in size to enhance users mobility and

convenience. These are the contribution of integrated

circuit (IC) technology. With this technology, the size of

devices has been reduced to convenient sizes. Besides

that, mass production of IC had lowered the cost of

production and caused most electronic devices to be

affordable. Today, an IC is smaller than a coin and can

hold millions of transistors. Hence, further research in the

design of IC is important to enhance the production of a

more efficient and viable IC.

This paper discusses the design of a layout for 7-

segment counter using Electric VLSI Design System. It is

a free open source EDA system that provides service in

handling IC layout, schematic drawing, textual hardware

description language and other more features [1]. By

using this software, a micrometer sized IC can be easily

designed due to the availability of various features that

can be used to design and check the IC layout. Moreover,

Electric VLSI Design System also allows the schematic

and layout design to be done in a proper and easier

manner, thus saving a lot of time and reducing the

production cost of the IC chip.

Manuscript received June 26, 2013; revised August 19, 2013.

There are a few technologies for constructing

integrated circuits such as bipolar integrated technology,

NMOS technology and CMOS technology and these

different technologies can produce different types of

transistors. In this project, CMOS technology is used.

One of the reason CMOS is chosen over NMOS and

bipolar technology is because CMOS circuit dissipates

less power. CMOS dissipates power only during

switching and hence it has almost no static power

dissipation. This factor has allowed the integration of

more CMOS gates on an IC than in NMOS or bipolar

technology, thus CMOS has better performance.

Furthermore, the of CMOS circuits is much cheaper if

compared to other technologies [2].

II. LITERATURE REVIEW

A. 7-Segment Counter

Counter is a device that can be used to count

something that is countable, for example pulses, objects,

events, processes and etc. 7-segment counter is a counter

will keep counting and display the result in a form of 7-

segment display. A 4-bits up/down counter is shown in

Fig. 1.

Figure 1. Up/ down counter [4]

The segments in the 7-segments counter are identified

with letters ‘A’ to ‘G’, where ‘A’ is the segment on the

top of the segments then counting clockwise will be

followed by the next alphabet and so on. The segment

will end with the centre bar which is indicated by ‘G’ [3].

The structure of a 7-segments display is shown in Fig. 2.

Figure 2. The Structure of a 7-Segments display

Lecture Notes on Photonics and Optoelectronics Vol. 1, No. 2, December 2013

52©2013 Engineering and Technology Publishingdoi: 10.12720/lnpo.1.2.52-55

mailto:[email protected]

Therefore, by setting the required regions (from region

‘A’ to ‘G’) to be on, the values wanted can be displayed

on the 7-segment display.

B. IC Design

IC layouts are built from three basic components

which are the transistors, wires and vias. During the

design of the layouts, the design rule has to be considered.

Design rules govern the layout of individual components

and the interaction between those components. When

designing an IC, designers will tends to make the

components as small as possible so that they can put as

many functions as possible onto a single chip. However,

since the transistors and wires are extremely small, errors

may happen during fabrication process. Hence, design

rules are created and formulated to minimise problems

during fabrication process and helps to increase the yield

of correct chips to a suitable level. Thus, it is important to

follow the rules during designing of layout.

C. Physical Verification of Design

Physical verification is a process where an IC layout

design will be checked via EDA tools to ensure it meets

criteria and design rules. The verification process used in

this project involves DRC (Design Rule Check), LVS

(Layout Versus Schematic) and ERC (Electrical Rule

Check). It is a very important procedure in IC layout

design and cannot be treated lightly.

i) Design rule check (DRC) [2]

DRC is a verification process that determines whether

the physical layout of a chip layout satisfies the Design

Rules or not. It ensures that all the polygons and layers

meet the manufacturing process rules that define the

limits of a manufacturing design such as the width and

space rules. DRC is the first level of verification once the

layout has been implemented, thus the connectivity, and

guidelines rules will be checked as well. DRC will not

only check the designs that are created by the designers,

but also the design placed within the context in which it

is going to be used. Therefore, the possibility of errors in

the design will be greatly reduced and a high overall

yield and reliability of design will be achieved.

ii) Layout versus schematic (LVS)

LVS is a process to check if a particular IC layout

corresponds to the original schematic circuit of the design.

The schematic acts as the reference circuit and the layout

will be checked against it. In this process, the electrical

connectivity of all signals, including the input, output and

power signals to their corresponding devices are checked.

Besides that, the sizes of the device will also be checked

including the width and length of transistors, sizes of

resistors and capacitors. The LVS will also identify the

extra components and signals that have not been included

in the schematic, for example, floating nodes. In Electric

VLSI Design System, this type of checking is known as

Network Consistency Checking (NCC) as it is able to

compare any two circuits, which includes two layouts or

two schematics.

iii) Electrical rules check (ERC)

ERC usually used to check the errors in connectivity

or device connection. It is an optional choice of checking

and seldom used as an independent verification step.

ERC is usually used to check for any unconnected, partly

connected or extra devices. Also, it will check for any

disabled transistors, floating nodes and short circuits.

ERC is very useful in accelerating debugging problems

such as short circuits as it can execute more quickly.

III. METHODOLOGY

The schematic circuit of the 7-segments counter was

drawn and debugging process had been carried out to

ensure the design is error free. In this project, the layout

of 7-segments counter was designed using Electric VLSI

Design System.

Electric VLSI Design System was used because it

could provide a more powerful editing. By using this

EDA tool, the editor can show the entire network

whenever any part of it is selected during browsing of a

circuit. Also, the connectivity is combined with a layout

constraint system to offer powerful manipulation tools.

Other than that, the tools in Electric VLSI Design System

are smarter as the Design Rule checker will know when

the layout is connected and it will use different spacing

rules accordingly. Also, Electric VLSI Design System is

highly flexible and powerful as it can handle many

different types of circuit design such as MOS, Bipolar,

schematics, printed circuitry and more. Electric also do

presents a simpler design process to the user. When

doing schematics and layout at the same time, the normal

design iteration is to first get the layout to be design-rule

clean. When the design-rule is clean, only then the

software will compare it to the schematic LVS as the

extractor cannot run if the design rules are having errors.

Later, if problems are found during LVS checking, the

layout will have to be fixed and DRC will have to be

made clean again. However in Electric VLSI Design

System, it can extract the connectivity for LVS without

having perfect design rules. Therefore, designers will

have to first get the layout and schematics to match. Then,

the design rules can be cleaned up without having to lose

the LVS match. This feature had helped to save a lot of

time during the verification of designs. [5]

Besides that, LTspice IV simulation software was also

required in this project. It is a high performance SPICE

simulator that provides a schematic capture and

waveform viewer. It is used to simulate the outputs of

both schematic circuit and layout during DRC and LVS.

IV. FINDINGS

Figure 3. Modified counter


53©2013 Engineering and Technology Publishing

In this project, an up counter that can count from digit

0 to 9 was designed. But the system of an up counter

would fail to run after digit 9. Consequently, this

up/down counter had been modified to become an up

counter that can count up to 9 and loop back to continue

counting. The design of the schematic circuit for

modified counter is shown in Fig. 3.

A. Setting of Scales for Schematic and Layout Design

In order to draw the schematic circuit of the modified

counter using Electric VLSI Design System, some

settings are required. Firstly, the width of the NMOS and

PMOS transistors were set. The width of PMOS

transistor was set to be twice more than the width of the

NMOS transistor. This setting was used throughout the

design. This is because NMOS’s majority carrier is

electron while PMOS’s majority carrier is hole. The

mobility of holes is less than the electrons by

approximately two to three times. Therefore, the width of

a PMOS transistor will have to set larger in order to get

approximately equal fall and rise time.

The technology used to design the layout of the

counter was the MoCMOS technology. The layers

available to be used in the layout design were set to six.

Also, the scale of the layout design for MoCMOS

technology is 300 nanometers.

The schematic circuits and layouts of NOT, 2-input

NAND, 3-input NAND, 2-input AND, 3-input AND,

NOR and OR gates were drawn.

B. Design and Simulation of Schematic Circuit

The JK flip-flop was being designed after all the basic

logic gates mentioned above had been designed and

verified through the physical verification and simulation.

The connections of schematic of the JK flip-flop were

created using the icon of two 3-input NAND gates and

two 2- input NAND gates.

Next, the schematic of JK flip-flop was simulated

using the spice code as shown in Fig. 5. A signal of

continuous sine wave was injected into the JK flip-flop to

represent the clock.

The result waveform generated for the schematic

design of JK flip-flop is shown in Fig. 6.

By comparing the result with actual result found as

shown in Fig. 7, it demonstrated that there were

discrepancies between the simulation and theoretical

waveform. This might be caused by the spike created

when multiple signals are turning to high voltage or

dropping to low voltage at the same time.

Figure 4. Schematic and Icon view of JK Flip-flop

Figure 5. Spice code for JK Flip-flop

Figure 6. Simulation for JK Flip-flop (Schematic digram)

Figure 7. Actual waveform result of JK Flip-flop [6]

The design of JK flip-flop layout was being

implemented, as shown in Fig. 8.

Figure 8. Layout design of JK Flip-flop

The simulation output of the layout design is shown in

Fig. 9. The results showed that both schematic design and

layout of JK flip-flop are similar.



Figure 9: Simulation for JK Flip-flop (Layout design)

C. 7-Segments Counter Using JK Flip-flop

A 7-segment counter which count up to 9 and loop

back to 0 was created. The schematic circuit design

drawn is shown in Fig. 10.

Figure 10: Schematic and icon view of 7-Segments counter

Figure 11: Simulation for 7-Segments Counter (Schematic diagram)

Figure 12: Layout Design of 7-Segments Counter

In order to make the counter to increase by one count,

the input of J and K will have to supply with 5V voltage.

Therefore, these two inputs were connected to the power

source of 5V.

After the simulation spice code was run, the output

waveforms shown in Fig. 11 were generated. The

waveform satisfied the theoretical counter result as all the

outputs were fluctuated at the range of 5V.

The layout design of 7-segments counter is shown in

Fig. 12.

The simulation waveform can be seen in the Fig. 13.

Figure 13: Simulation for 7-Segments counter (Layout design)

By comparing both waveforms from schematic circuit

and layout design, both designs had simulated different

waveforms although there was no error found for all the

physical verification process. The waveform simulated

in schematic design did not showed ideal square pulses as

other outputs simulated from basic gates. While for the

layout design, the outputs of q1, q2 and q3, showed some

square pulses with spiked. However, output q0 showed

the signals remained at a level of more than 3.5V. As

there was no similar error faced when simulating simple

gates in this project, this error could also occur due to the

noises occurred in the basic gates.

V. CONCLUSION

In conclusion, Electric VLSI Design System is user

friendly software to be used in designing a 7-segments

counter layout. The output simulation waveforms for

both schematic circuit and layout were different from the

theoretical counter, due to the noises occurred in the

basic gates. In order to obtain the desired results, it is

recommended that it is necessary to design the gates

without noise.

REFERENCES

[1] Electric: VLSI design system. (May 2013). [Online]. Available:

http://java.net/projects/electric

[2] R. Behzad, “Design of analog CMOS integrated circuits,” McGraw-Hill Higher Education, New York, 2001.

[3] (May 2012). [Online]. Available: http://www.play-

hookey.com/digital/experiments/seven_seg_led.html [4] Synchronous counters. (May 2013) [Online]. Available:

http://www.web-

books.com/eLibrary/Engineering/Circuits/Digital/DIGI_11P3.htm [5] Static free software home of the electric VLSI design system.

(May 2013). [Online]. Available:

http://www.staticfreesoft.com/documentsUser.html [6] JK, RS, T Flip-flop design, Design practice-MyCAD. (May 2013).

[Online]. Available:

http://www.seloco.com/inc_mycad/Download_Files/JK_RS_T%20Flip-Flop%20Design.pdf



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