lecture06 2005 power

8/19/2019 Lecture06 2005 Power

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Lecture 6 Logic gates :

Power and Other LogicFamily

Pradondet Nilagupta

[email protected]

Department of Computer Engineering

Kasetsart University


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#

Acknowledgement

'his lecture note has (een summari)ed fromlecture note on *ntroduction to +,-* Design"

+,-* Circuit Design all over the orld. * can/t

remem(er here those slide come from.0oever" */d like to thank all professors ho

create such a good ork on those lecture

notes. 1ithout those lectures" this slide can/t

(e finished.


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2

Parasitics and Performance

Consider the folloinglayout3

1hat is the impact on

performance of

parasitics &t point a 4+DD rail56

&t point ( 4input56

&t Point c 4output56

b

a

c


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%


a 7 poer supplyconnections capacitance 7 no effect

on delay

resistance 7 increasesdelay 4see p. 285

minimi)e (y reducing

difffusion length

minimi)e using parallelvias

b

a

c


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8


( 7 gate input capacitance increases

delay on previous stage

4often transistor gates

dominate5 resistance increases

delay on previous stageb

a

c


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!


c 7 gate output resistance" capacitance

increase delay

9esistance :

capacitance ;near; tooutput causes additional

delay b

a

c


7/36<

Driving Large Loads

=ff7chip loads" long ires" etc. have high capacitance *ncreasing transistor si)e increases driving a(ility 4and

speed5" (ut in turn increases gate capacitance

-olution3 stages of progressively larger transistors

Use nopt > ln4C(ig?Cg5.

-cale (y a factor of α>e

Cbig

pullup: W p /Lp

pulldown: W n /Ln

pullup:αWp /Lp

pulldown: αWn /Ln

pullup:α

2

Wp /Lp

pulldown: α2Wn /Ln

n stages


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Summary: Static CMOS

&dvantages 0igh Noise Margins 4+=0>+DD" +=,>And5

No static poer consumption 4eBcept for leakage5

Compara(le rise and fall times 4ith proper si)ing5

9o(ust and easy to use

Disadvantages

,arge transistor counts 4#N transistors for N inputs5

,arger area

More parasitic loading 4# transistor gates on each input5

Pullup issues ,oer driving capa(ility of P transistors

-eries connections especially pro(lematic

-i)ing helps" (ut increases loading on gate inputs


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Alternatives to Static CMOS

-itch ,ogic nmos

Pseudo7nmos

Dynamic ,ogic

,o7Poer Aates


10/36$

Switch Logic

Key idea3 use transistors assitches

Concern3 sitches are

(idirectional

AND

A B

A

B

OR


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Switch Logic - Pass ransistors

Use n7transistor as sitches 'hreshold pro(lem'ransistor sitches off hen +gs F +t

+DD input 7G +DD7+t output

-pecial gate needed to restore

values

IN:VDD

A: VDD

OUT:VDD-Vtn


12/36#

Switch Logic - ransmission!ates

Complementary transistors 7 n and pNo threshold pro(lem

Cost3 eBtra transistor" eBtra control

inputNot a perfect conductorH

A

A’

A

A’


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Switch Logic "#am$le - %-& M'(

IN

IN1

IN2

SEL’

SEL

SEL

OUT


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Charge Sharing

Consider transmission gates in series Each node has parasitic capacitances

Pro(lems occur hen inputs change to redistri(ute

charge

-olution3 design netork so there is alays a path

from +DD or And to outputA B C

A’ B’ C’


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Aside: ransmission !ates inAnalog

'ransmission Aates orkith analog values" tooH

EBample3

+oltage7-caling D?&Converter

S0

S0’S1

S1’S2

S2’

S3

S3’

OUT

R

R

R


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)MOS Logic

Used (efore CM=- as idely availa(le Uses only n transistors

Normal n transistors in pull7don

netork

depletion7mode n transistor

4+t F $5 used for pull7up

;ratioed logic; reIuired

'radeoffs3

J -impler processing

J -maller gates7 higher poerH

7 &dditional design considerations

for ratioed logic

Passive Pullup Device:depletion Moden-transistor (Vt < 0)

OUT Pulldown

Network


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Pseudo-nmos Logic

-ame idea" as nmos" (ut use p7transistor for pullup

;ratioed logic; reIuired for proper

design 4more a(out this neBt5

'radeoffs3

J eer transistors 7G smaller gates"

esp. for large num(er of inputs

J less capacitative load on gates that

drive inputs

L

larger poer consumption L less noise margin 4+=, G $5

L additional design considerations

due to ratioed logic

Passive Pullup Device:P-Transistor

OUT Pulldown

Network


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*atioed Logic for Pseudo-nmos

&pproach3 &ssume +=U'>+=, >$.#8+DD &ssume pulldon transistor is on

EIuate currents in p" n transistors

-olve for ratio (eteen si)es of p" ntransistors to get these conditions

urther calculations necessary for

series connectionsIdn = Ipn

12

k' n WnLn

Vgs,n − Vtn( )2 = 12 k' pW

pLp

2 Vgs,p − Vtp( )Vds,p − Vds,p2[ ] (EQ 3 − 21)Wp

Lp

WnLn

≈ 3.9 (EQ 3 − 22) − Assu ming VDD = 3.3V

IdpOUT

Pulldown

Network

Idn


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DC+S Logic

DC+- 7 Differential Cascode +oltage-itch

Differential inputs" outputs

'o pulldon netorks

'radeoffsJ ,oer capacitative loading

than static CM=-

J No ratioed logic needed

J ,o static poer consumption7 More transistors

7 More signals to route (eteen gates

7 EBample3 ig. 2.# p. %

OUTPulldownNetwork

OUT’

OUT’PulldownNetwork

OUT

A

B

C

A’

B’

C’


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Pulldown

Network

CS

φ

φ

A

B

C

Dynamic Logic

Key idea3 'o7step operationprecharge 7 charge C- to logic

high

evaluate 7 conditionally

discharge C-

Control 7 precharge clock φ

Storage Node

StorageCapacitance

PrechargeSignal

Precharge Evaluate Precharge


21/36#

Domino Logic

Key idea3 dynamic gate J inverter Cascaded gates 7 monotonically

increasing

Pulldown

Network

CS

φ

φ

B

C

in4 x1 x2

x31

01

φ

in4

x1

x2

x3


22/36##

Domino Logic radeoffs

J eer transistors 7G smaller gatesJ ,oer poer consumption than pseudo7nmos

7 Clocking reIuired

7 ,ogic not complete 4&ND" =9" (ut no N='5


23/36#2

More echni,ues for SavingPower

9educe +DD 4tradeoff3 delay5 Multiple Poer -upplies

0igh +DD for fast logic

,o +DD for slo logic

4level translation an issue5

DC-, 7 ig. 2728" p. 88

cross7coupled outputs

partially disconnected pulldon netork

Dealing ith leakage currents 4p. 85

Multiple7'hreshold CM=- 4M'CM=-5 7 ig 272<

+aria(le7'hreshold CM=- 4+'CM=-5 7 ig 272


24/36#%

Delay in Long ires - Lum$ed *CModel

1hat is the delay in a long ire6

,umped 9C Model3

Delay time constant 4ignoring driving gate5

τ > 9 C > 49s , ? 15 4, 1 Cplate 5

> r c ,#

Pro(lem3 =verly Pessimistic

Lin out

R = Rs * L / W = r*L

(r = Rs / W - resistance per unit length )

C = L * W * Cplate = c*L

(c = W * Cplate - capacitance per unit length)

RC

in out


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#8

Delay in Long ires -Distri.uted *C Model

&lternative3 reak ire into small segments

&pproB. -olution 7 st moment of impulse response

*mportant3 delay still gros as sIuare of length

R1 = r∆L

in out

R2 = r∆L Rn = r∆L

Cn

c∆

L

C2

c∆

L

C1

c∆

L

τ(Vout ) = rc ∆L 2 N N 1

2

τ

(Vout )=

rcL2

2 for N →∞


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#!

Delay in Long ires -Conse,uences in design

Distri(uted 9C model3

Delay gros as sIuare of ,HChoose ire material that minimi)es r" c

reak ire into (uffered segments to optimi)e

delay

τ(Vout ) =rcL

2

2

in out

Lin out


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#<

"lmore Delay

Consider 97C ladder netork ith uneIual values

irst7order time constant at node N is

irst7order time constant and node I is

τN = Rii=1

N∑

C j j=i

N∑

= Cii=1

N∑

R j j=1

i∑

τ i = C 1 R1 + C 2 ( R1 + R2 ) + ... + C i ( R1 + R2 + ... + Ri )

R1

in

R2 Ri

CiC2C1

out

Rn

Cn

1 2 i n


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#

"lmore Delay A$$lications

1ire si)ing to minimi)e delayDelay prediction of compleB netorks

4as long as they take the form of a ladder5


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#

"lmore Delay /omework Pro.lem

1hat are the Elmore time constants τ" τ#" τ26R1100ž

in

R250ž

R3200ž

C390fFC2

70fFC1

50fF

1 2 3out


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2$

ire Si0ing

9ecall distri(uted model of ire3 multiple segments

note strong impact of 9" lesser impact of 9#" etc

*dea3 9educe overall delay (y tapering segments

Make -egment idest to reduce 9 4increases C5

Make -egment # less ide to reduce 9# 4increses C#5

etc.

τ i = C 1 R1 + C 2 ( R1 + R2 ) + ... + C i ( R1 + R2 + ... + Ri )

R1

in out

R2 Rn

CnC2C1


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2

ire Si0ing

*deal 9esult ire should taper eBponentially7 see EI. 27#$" p. !2 Ois83

More pragmatic approach3 step7tapered ire

[Fis95] J. Fishburn and C. Schevon, “Shaping a distributed-RC line to inii!e

"lore dela#$, IEEE Trans. on Circuits and Systems-I , %eceber &995, pp. &'('-&'((


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2#

1uffer 2nsertion

Key *dea3 reak long ire up into stages 4-ec. 2.


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22

ire Si0ing - )ew *esults

&lternative approach O&lpert$3 Com(ine (uffer insertion and

Untapered ires of 4small num(er of5 different idths

'heoretical result3 'apering gives at (est 2.8Q

improvement over this approach Practical result3 tapering generally not orthhile[)lpert'&] “*nterconnect S#nthesis +ithout +ire tapering$, IEEE Trans. CAD, ol. (', o. &, Januar# (''&,

pp. 9'-&'

in out


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2%

Delay in *C-rees

Many interconnection netorks are treesEBtracted 9C circuit modeling a gate output

Clock trees

R1

in

R2

C2

C1

1

2R3

C3

3

R4

C4

4

R5

C5

5

R6

C6

6

o1

o2


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28

Delay in *C-rees:Penfield-*u.enstein 1ounds

Key idea3 characteri)e time constants in terms of Path resistances (eteen nodes

Capacitance values at each node

R1

in

R2

C2

C1

1

2 R3

C3

3

R4

C4

4R5

C5

5R6

C6

6

o1

o2

Rko = R j ⇒ (R j ∈[path(in→ o)∩ path(k→ o)])


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Delay in *C-rees:Penfield-*u.enstein 1ounds

'ime constants 'p" 'Do" '9o 4eIn. 272$ 7 272%5 'a(le 27# 4p. !85 7 (ounds for time" voltage

lecture06 2005 power

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