lecture_1

Design principles for low-voltage low-power analog integrated circuits

© 2006

Wouter A. Serdijn

2© Wouter A. Serdijn

Overview

� Design considerations

� Dynamic Translinear (DTL) circuits

� Switched MOSFET (SM) circuits

� Properties of DTL and SM circuits


Today’s problem

� Design strategies for the reduction of stochastic errors and systematic errors are normally not consistent with design strategies which take into account

� power dissipation,

� voltage range and

� current range.

� ⇒ The combination of transfer quality, low voltage and low power must be considered during the whole design process.


Today’s challenge

Etr,min=8kT

S/N [dB]

Pmin/f per pole [J]Etr [J]

analog:Pmin=8f kTS/N

digital:P = m f Etr + Pstat

30 60 90 120

10-18

10-15

10-12

10-9

AGC: 1V, 4µW, 10kHz, 62dB

2500 x


Considerations

� the system’s input and output signals,

� the signal processing inside the system,

� the circuit topology,

� the parasitics and

� the power supply.


Source and load quantities

Example (I): a piezo-electric pressure transducer

� Since charge is linearly related to current

(i = dq/dt), the output current of the sensor must bechosen as the electrical input quantity of the amplifier.

� The result is a charge amplifier.

is

Cs

Cf

ZL


Source and load quantities

Example (II): an electret microphone

• Since dC << C, none of both methods is (theoretically) preferred above the other. Current sensing is less disturbed bycable capacitances and is therefore preferred in practice

• voltage sensing • current sensing; virtualground

CC

CUUu

UUCCCU

QQ

δδδ

δδ

+=−=

++=

=

0micro

00

activequiescent

))((

0 0 active

00

0out

amplifier

/ /

/

Charge amplifier yields:

U Q C Q C

Q QQ C

C C

U Cu

C

δδ

δ

= =

+=

+

=


Signal processing inside the system

Which electrical quantities are best suited for a particularsignal-processing function inside the system?

� addition/subtraction ⇒ currents

� distribution ⇒ voltages

� desired non-linear transfer of devices ⇒ interplay of current and voltages


Accurate transfer (I): direct feedback

H

Tf

vS ZS ZL vL

+

-

A

H

Tf

iS ZS ZL

iL

B

H

Tf

vS ZS ZL

iL

C

H

Tf

iS ZS ZL vL

+

-

D

Figure 1. Four basic direct negative-feedback amplifiers:

a voltage amplifier (A), a current amplifier (B), a transconductance amplifier (C)

and a transimpedance amplifier (D)


Example

iS ZS ZL

R1

R2

iL

Tf

Q1 Q2

H

Figure 2. Possible embodiment of a direct-feedback current amplifier.

Transistors Q1 and Q2 perform the nullor function.

The feedback network is implemented by resistors R1 and R2.


Accurate transfer (II) at low supply voltage: indirect feedback (I)

T1 Tr

T2

Tf

vS ZS

+

-

ZL vL

Figure 3. A voltage amplifier with negative feedback and

indirect voltage comparison


Indirect feedback (II)

ZL

iLiS ZSTr T1

T2

Tf

Figure 4. A current amplifier with negative feedback and

indirect current sensing


Indirect feedback (III)

vS ZS ZL

iLT1 Tr T3

T4

Tf

T2

Figure 5. A transconductance amplifier with negative feedback and

indirect current sensing and indirect voltage comparison


Example

R1R2

T2

T1 ZL

iLZSiS Tr

Tf

Figure 6. Possible implementation of the indirect-feedback current amplifier.

Two cascaded transistors inside Tr perform the nullor function.

The feedback network is implemented by the resistive divider (R1 and R2).

The indirect outputs are provided by T1 and T2.


Noise

us

un,eq

Zs

in,i

un,i

is

in,eq

Zs

in,i

un,i

snneqn

snneqn

Zuii

Ziuu

/,

,

+=

+=

dominates :||

dominates :0||

ns

ns

iZ

uZ

∞→↓

any active

device

DCn

DCn

IIi

IIu

,

, 11

∝∝ −−

⇒ preference for the choice of current as the information-carrying quantity.


Circuit topology (I)

� Indirect voltage comparison ⇒ doubled power density spectrum of the equivalent noise voltage at the input.

� Indirect current sensing ⇒ doubled power density spectrum of the noise current at the output.

� If noise at the input is more important than the noise at the output (e.g., in an LNA) ⇒ preference for the choice of current as the information-carrying quantity.

un,eq

Zs

un,eq,i

Zs,i

us

us,i i

n1in2

ZL1 ZL2


Circuit topology (II)

� When the circuits are voltage-driven, i.e., from a low-impedance source, using indirect voltage comparison, the equivalent input noise voltage is predominantly the result of the input noise voltage of both input stages. For bipolar transistors and CMOS transistors in weak inversion, this input noise voltage is inversely proportional to the bias (collector or drain) current, and thus, in order to obtain a low input noise voltage, these bias currents must be rather large.

� When the circuits are current-driven, i.e., from a high-impedance source, using indirect current sensing, the equivalent input noise current is predominantly the result of the input noise current of only one input stage. For bipolar transistors, this input noise current is proportional tothe bias (collector) current, and thus, in order to obtain a low input noisecurrent, this bias current must be rather small.

⇒ preference for the choice of current as the information-carrying quantity.


Circuit topology (III)

� Another disadvantage of indirect voltage comparison is that, in order to compensate each other, the non-linearities of the twoinput stages must be symmetrical or opposite, because the sumof their output currents must be nullified by the nullor.

� In practice, this requires either two balanced input stages or twocomplementary stages in a complementary IC process. The useof two balanced input stages, since their input noise voltages are placed in series, again doubles the power density spectrum of the equivalent input noise voltage. A complementary IC process is often not available and, moreover, exact complementarity cannever be accomplished.

� Indirect feedback at the output, however, calls for two identicaloutput stages, to compensate for the non-linearities. These caneasily be made in any ordinary IC process.

� For this reason there again may be a preference for currentsensing and thus for current as the information-carrying quantity.


Parasitics

� Parasitic admittances ⇒ terminate the signal path witha low impedance. No voltage ⇒ no current

� Parasitic impedances ⇒ terminate the signal path witha high impedance. No current ⇒ no voltage

ZL

ZS

iS

Zimp

Zadm


0.0us 0.5us 1.0us 1.5us 2.0us

Time

I(Cideal) I(Dcapac)

8.0uA

4.0uA

0.0uA

-4.0uA

-8.0uA

Example of a parasitic admittance: a junction capacitance


� Parasitic admittances� node capacitances

� the transistors’ junction capacitances: (non-linear) voltage dependency

� Parasitic impedances� branch inductances and resistances,

� the transistors’ bulk resistances

� In low-power IC’s, the admittances have more influence on the signal behavior than the parasitic impedances ⇒ terminate the signal paths with low impedances as much as possible ⇒choose current as the information-carrying quantity.

ZL

ZS

iS

Zimp

Zadm

Parasitics, cont’d


Power supply

� In practice, the power supply is a voltage source(battery), giving a limitation in voltage.

� The limitation in current is only indirectly given by a limitation in the energy of the battery and might beless restricting than that of the voltage.

� This favors the choice of current as the information-carrying quantity.


Design principles, summary

In Low-Voltage Low-Power Analog Integrated Circuits, current is the preferred information-carrying quantity, since

1. Noise contribution of active devices is minimized at low bias currents

2. Indirect feedback is readily implementedi. No doubled noise power at the input

ii. Only equivalent devices required

3. The effects of parasitic admittances is reduced

4. The current is only indirectly limited by the power supply


Application:integrators in filters (I)

ii

C +

-OA

Rio

1 n

Q1 Q2

i’o

i

i

n

j RC

o

i

=ω


Application:integrators in filters (II)

ii

CA RA RBCB

io

s=2 s=2

VCC+

-VF


Application:a controlled microphone preamplifier (I)

R

current

mirror

viii

m n

ioi’o i’’o

Q1 Q3 Q2

Rv

i

R

m

Gi

v

n

R

i

i

i

o

i

= =

= =


Application:a controlled microphone preamplifier (II)

R

RX

10

10 10

R

vi

RE RE

RE RERE

RC

RC

RC

to offset filter

to highpass filter

VCC

VCdummy amplifier

bias circuit

bias circuit

RE RECcomp


Application:an automatic gain control (I)

controlledcurrent

amplifieriS

VCVC C

Irel

Iatt

comp

IK

iLiL

IX


Application:an automatic gain control (II)

iS

VCC

+

-

iL

1µ

R4

V1

Ccomp

2

2 2

R2R1

10

2

5

V2

R3C

Irelcomparator + switchCvoltage followervoltage-controlled type ’1’ symmetrical current mirror


Overview (cont’d)






Mathematical foundation

Electronics design =

mapping of a set of mathematical functions

on silicon

Exponential mapping

e e ea b a b⋅ = +

)()( )( txtxe

dt

tdxe

dt

d⋅=Dynamic translinear:

Static translinear:


The bipolar transistor

Barrie Gilbert: “Bipolar transistors are nice and friendly devices.”

1,0E-12

1,0E-11

1,0E-10

1,0E-09

1,0E-08

1,0E-07

1,0E-06

1,0E-05

1,0E-04

1,0E-03

2,0E-01 3,0E-01 4,0E-01 5,0E-01 6,0E-01 7,0E-01 8,0E-01 9,0E-01

Base-emitter voltage

Co

llecto

r curr

ent

9 decades = 180 dB

(2 µm x 4 µm)DIMES-02 NPN transistor


Static translinear principle

I1 I2 I3 I4

Kirchhoff:

Equal number of transistors in

both directions of the loop

V V V VBE BE BE BE1 3 2 4+ = +

gI

Um

C

T

= → transconductance linear with collector current

⇒ translinear

I I I I1 3 2 4=


Dynamic translinear principle

Vcap

+

-

Vconst+ -

VBE

+

-

Icap

ICcapacitance current:

= CdVBE

dtIcap

= CVT

IC

IC

dynamic translinear principle:

= IC IcapCVT IC

VT =kTq

= thermal voltage

IC =ddt

IC

A time derivative can be mapped on products of currents

⇒ translinear principle


Synthesis procedure

Dimension-less

polynomial

Current-mode

polynomial

Translinearloop

equations

Prototypecircuit

Dimension-less

polynomialdifferentialequation

Translineardifferentialequation

Static translinear circuits

Dynamic translinear circuits

Current-mode

polynomial

Translinearloop

equations

Prototypecircuit


Overview (cont’d)






Switched MOSFET principle is basically an “active” SI technique


Overview (cont’d)






Quality aspects of DTL and SM circuits

� Signal-to-noise ratio and dynamic range

� Bandwidth

� Low power

� Low voltage

� Controllability

� Integratability

Comparison with MOSFET-C, gm-C, SC and SI


Quality aspects: signal-to-noise ratio and dynamic range

� The fundamental limit of DTL circuits, SNRDTL,max = CUT/q = CUT2/kT, is

always smaller than the fundamental limit of linear – thus also SM –circuits, SNRlin,max = CVDD

2/4kT

� Due to out-of-band signals, the SNR of DTL and SM circuits deteriorates. Therefore, DTL and SM filters are better suited for shaping than for selection.

� Class-AB operation extends the dynamic range of both DTL and SM circuits at the upper side

Quality aspect DTL SM linear

SNR − 0 +

DR − (class A)

++ (class AB)

0 (class A)

++ (class AB)

+


Quality aspect: bandwidth

� In DTL and SM circuits, the voltage excursions are small ⇒ effects of parasitic capacitances are reduced ⇒ relatively (to fT or fUG) wide bandwidth operation

Quality aspect DTL and SI SM, SC and

MOSFET-C

gm-C

Bandwidth + − ++


Quality aspect: low power

� A high functional density

� No resistors ⇒ especially interesting for ultra low power

Q1

Q2

Q7

Iin

Q3

Io

T4

Io

Q8

Q5

Io

Q6

An RMS-DC converter: squaring, square-rooting and lowpass filtering

in a six-transistor dynamic-translinear core


Quality aspect: low voltage

� In DTL and SM circuits, the voltage excursions are small ⇒beneficial in a low-voltage environment

� The supply voltage of DTL and SM circuits must be larger than one junction voltage and two current-source voltage drops ⇒1V

Quality aspect DTL and SM MOSFET-C,

SC and SI

gm-C

Low voltage + − +


Quality aspect: controllability

� Due to their indirect negative feedback, DTL and SM circuits areeasily controlled by currents or MOCD’s, respectively, over a wide range of parameters

� Good designability

� Standard cells

� Programmable building blocks


Quality aspect: integratability

� In DTL and SM circuits, only three types of components are required:

� Well-matched (in case of DTL: purely-exponential) transistors

� Large-gain, high-fT transistors

� Capacitors

� Thus

� Possible to implement in (almost) any IC process

Q1 Q2 Q3

C2

Q35Q34

Q4

Q36 Q37

Q5

+0.2V

Q38

G

Q6 Q7

Q39 Q40

Q8 Q9

Q11

Q25

Q26 Q27

+1V

Q41 Q42

Q12

Q28

Q43

Q44 Q45

Q46 Q48 Q49

Q47

Ibias

Q29

2G

Q30

Q50

Q13 Q14

Q51

Q16Q15

C1

Q31

Q52 Q53

Q17

Q54

Q18 Q19

Q55 Q56

Q20

Q23

Q32

2G

G

Q21

Q33

Q57

Q22

Q10

Io+I2

Q24

Io−I1

2 2 2 2


DTL phaselock demodulator

• fc = 100 kHz:

• Supply voltage: 1.5 V – 5 V

• Current consumption: 40 µA

• Hold-in range: 40 kHz – 150 kHz

• Lock-in range: 55 kHz – 150 kHz

• ∆f = 40 kHz (!), fm = 1 kHz, THD < 1 %

• SNR (B = 10 kHz) = 57 dB

QN6B QN54

cap3

QN56 QN57 QN51

QN58

QN53QN59 QN52

QN6A QN69

IO1

QP65

QP64 QP63 QP62 QP61

QN75 QN76

QN77 QN78

QN65

QN63

QN61IO2

QN67 QN68

QN66

Iin

IO2

QN64

VCC

+

-

QP48

QN47

QN46

QP40

QN8

QN1 cap2

QN8

QN3

QN9

QN4QN6QN7QN5

QP1

QN10

QP41

QP42

QP2

QN11

QN18

cap1

QP3

QP43

QN12 QN13

QN14

QN19

QP45

QP44

QN23 QN24

QN48

QN21

QN62

QN22

QP21 QP22 QP46

QP47

QN28

QN27

QN26

QN25


SM circulating 4-tap FIR filter

VDD

CK

VDD

VDDVDD VDD

ck2M VB

+

M VB

+

M VB

+

ck3

ck1

M VB

+

ck4

MM M M

R

Vin

VDD

R

+

M

+VB

iO

VB

VB

iin

VB

CK

h1 h2h3h4

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4-25

-20

-15

-10

-5

0

Relative frequency (f/fCK)

dB

Theoretical

Simulated

*********Measured

1

2

1 <3F 15 0B 06>1 <3F 15 0B 06>

2 <3F 36 2E 27>2 <3F 36 2E 27>


Signal-to-noise ratio versus dynamic range

� The (maximal) signal-to-noise ratio (SNR) equals the (maximal) ratio of the signal power and the noise power at the same time

� The dynamic range (DR) equals the ratio of the maximal signal power and the noise power in the absence of any signals

� The maximal signal power is given by an application-specific specification of the distortion level


Noise

� Noise in linear circuits:

� Is wide-sense stationary

� Can be represented by independent noise sources

� Can be transformed independently of the signal

� Noise in non-linear circuits:

� Is non-stationary

� Must be modeled by signal-dependent noise sources

� Noise << signal ⇒ linear time-varying approximation


Non-stationary noise

� Multiplication of currents ⇒ signal × noise intermodulation (aliasing)

v5 v6

i2 i3v7 v8

i1 i4

I1 I2 I3 I4

+++⋅++=++

TU

vvvviIiIiIiI 876544223311 exp))(())((

� Noise level increases with the signal power

� Saturation of the SNR


Noise in translinear integrators (I)

÷ ∫ F

F’dF(v)/dv

x(t) = dy(t)/dt y(t) = F(v(t))v(t)dv(t)/dt

x tdy t

dt

dy t

dv t

dv t

dtv t

dv t

dt

dFdv( )

( ) ( )

( )

( )[ ( )]

( )= = ⋅ = ⋅

general block diagram of a translinear integrator


Noise in translinear integrators (II)

÷ ∫

F’

F

+

+ + +

ε3(t)

x(t) y(t)

ε4(t)ε2(t)ε1(t)

a a/b

v(t)

dv/dt

y’(t)

b

The translinear integrator including its (additive) noise sources

==

+⋅+⋅++=

∫−

t

xxxy

dxFdv

dF

txG

txtxG

tStxGE

tStxGE

tStStS

tS

ττ

ωωωωωω εεε

ε

)(),(

)(),(

)()],([

)()],([

)()(),(

),(

1

2

1

2

2

2

2

2

1

22 432

1

⇒ Signal × noise intermodulation


Dynamic translinear noise

+

-

Io

CIin

Io

+

-

Iout

•SNRQ ~ IC

•Q2 and Q3 determine SNRmax

20

40

60

80

0.01 0.1 1 10

SN

R [

dB

]

m

12

2

2

⋅⋅

I

qII

CU

o

o

o

T

Noise bandwidthNoise power

spectral density

Collector

current

power

= CU

qT


Noise in class AB

� Signal >> bias current ⇒ noise behavior strongly non-linear ⇒ DR > SNRmax

� Harmonic decomposition into two class-AB signals requires a good matching of both signal paths to prevent distortion

current

splitter

Iin1

Iin2

F

F

IinIout

+

-

Iout1

Iout2

Iin Io

C 2Io

Iout

Q1 Q3Q2 Q4


Photograph

Breadboard realization.

For biasing purposes the integrator is enclosed in a unity-feedback configuration


Experimental results (I)


Experimental results (II)

Quantity Value Comment

Cutoff frequency 1.6 kHz C = 100 nF, IF = 26

nA, room temperature

Maximum SNR 63 dB for 1-kHz, 400-nA

(RMS) input signal

and 2 % output THD

Dynamic range 76 dB ditto

Supply voltage 3.3 V

Quiescent current 310 nA


Bandwidth

� Bandwidth of linear circuits:

� Independent of the signal

� Eigenvalues are equivalent to poles

� Stability and frequency behavior are equivalent

� Bandwidth of non-linear circuits

� Depends on the signal

� Eigenvalues and poles are not equivalent

� Stability and frequency behavior are not equivalent


Quality aspect: bandwidth (I)

2Io

Iin Io

Iout

2Io

Iin Io

Iout

IC U

I

I I I I

I

CU

II Iin

par T

O

in out out in

in

C

T

O

out out

par

+−

= +

� ��

additional non-linear term resulting from

� ��


Quality aspects of dynamic translinear circuits in general

Quality aspect ranking comment

SNR/CNR − for large input currents the SNR saturates

DR ++ due to companding the DR can be very high

Linearity + exponential over a wide range of currents

Bandwidth + high functional density

Low power + high functional density

Low voltage ++ minimum voltage loss over the devices

Controllability ++ all parameters are current-controlled

Integratability ++ only transistors and capacitors are required


Application areas

� Filters [almost every conference, workshop or colloquium] for shaping, not for selection. E.g., a reconstruction filter

� RMS-DC converter [ESSCIRC’96, JSSC’97]

� Oscillator [ESSCIRC’97, JSSC’98]

� Phase detector [Payne et al., El. Lett. 1997]

� Infra-red front-end (amplifier and AGC function)

� QPSK demodulator (quadrature oscillator, mixing and filtering of I and Q) [ISCAS’99]

� Subminiature hearing-aid adapter [ISCAS’00]

� Artificial dendrite (DTL Hodgkin-Huxley)


Thank you for your attention!


(Second-order) PLL design

d2z

dτ12 + wf(z)

dzdτ1

+ w2z = 0

oscillator

dwdτ2

- adydτ2

- y = 0

loop filter phase detector

y - x·sgn(z) = 0

y

zw

x

FM in

demod.out


Transformations (I)

wI

I

xI

I

yI

I

zI

I

F

O

in

O

D

O

osc

O

=

=

=

=

1

1

1

1


Transformations (II)

� Time (t) is inversely proportional to current IO1� IO1 must be proportional to the absolute temperature (PTAT) to eliminate the influence of the temperature on the PLL

d

d

CV

I

d

dti

i T

Oτ=

1


Transformations (I + II)

C V I C V I f I I I I I

C V I aC V I I I

I I I

T osc T F osc F osc F osc

T F T D D O

D in osc

1

2 2

1

2

2 2 1

0

0

0

�� ( , ) �

� �

sgn( )

+ + =

− − =− =


PLL properties

� the ‘CCO gain factor’

� the phase detector gain

� the loop gain

� the natural frequency of the loop,

� the damping factor

� ...

K V CTosc = 1 1/

K Id = 4 in / π

K aK Kd= osc

ωn

osc d O

T

K K I

V C= 1

2

ζω

= n T

O

aV C

I

2

1


Definition of the capacitance currents

� Each capacitance current reduces the order of the differential equation by one, until finally a set of current-mode multivariant polynomials results.

� Result:

FI I I I I I I I I I I I I

I I aI I I

I I I

cap F cap cap F F osc F cap F osc F osc

cap F D D O

D in osc

2 1 2 2

3 1

0

0

0

+ + + − + − =

− − =

− =

( )( ) [ ( ) ]

( )

sgn( )


Translinear decomposition (I)

� Aim: always positive collector or drain currents

� Often: parametric decomposition, i.e. introduction of ‘intermediate’ currents

� F must be a non-linear time-invariant odd-symmetry function of Iosc and IF, whose derivative f with respect to Iosc is negative for small values of Iosc and positive for large values of Iosc. A suitable choice is

F IGI I

I Iosc

osc F

osc F

= −+

22 2

2 2


Translinear decomposition (II)

oscillator:

loop filter:

phase detector:

( ) ( )( )

( ) ( )( )

( , )

[( ) ] ( )( )

sgn( )

sgn( )

I I I I I I I I

I I I I I I I

I I F I I

a I I I I aI I I

II

I I

II

I I

F P Q F F cap osc F

F P F F cap Q F

P osc osc F

D F O F D cap O

O

in

osc R

O

in

osc

+ − = + +

+ = + +

= −

− + = − +

+

=

−

=

1

2

1 3 1

2

2

2

1

2

2 S

D R SI I I= −


Implementation of Ip(F)

IF-IOSCIF+IOSC

GIF

IP

VCC


Possible biasing arrangement

cap3 IO1

QN54

QN53 QN52

a.ID QN51

VDC

IO2+Iin

QN75 QN76

QN78QN77

-

+

VDC

-

+QN65

IO1

QP63

QP64QN66

QN68QN67

IO2-Iin

VDC+

-

QN1 IF IF cap2 QN4

QN2 QN3

IF

QN11

IF

QN12

IF cap1

QN13

QN14QN5 QN21

QN22

QN23 QN24 QN25

G.IF QN26

IF2IF QP24 QP22IF

VCC

+

-

2IF

QN27

QP1QP2

QP3IF

IQ+IF

IP

Iosc+IF

ID


Design example: the PLL as an FM detector

� fc = 100 kHz

� ∆f = 40 kHz� ζ = 0.9 (pull-in time and noise bandwidth), C1 = C2= 100 pF, C3 = 1 nF

� Semicustom version (SIC2A) of 2-µ, bipolar IC process (DIMES-02, hfe,NPN = 100, fT,NPN = 7 GHz, hfe,LPNP = 80, fT,LPNP = 40 MHz), G = 5/4 by design

� Supply voltage: 2 V


Circuit diagram

QN6B QN54

cap3

QN56 QN57 QN51

QN58

QN53QN59 QN52

QN6A QN69

IO1

QP65

QP64 QP63 QP62 QP61

QN75 QN76

QN77 QN78

QN65

QN63

QN61IO2

QN67 QN68

QN66

Iin

IO2

QN64

VCC

+

-

QP48

QN47

QN46

QP40

QN8

QN1 cap2

QN8

QN3

QN9

QN4QN6QN7QN5

QP1

QN10

QP41

QP42

QP2

QN11

QN18

cap1

QP3

QP43

QN12 QN13

QN14

QN19

QP45

QP44

QN23 QN24

QN48

QN21

QN62

QN22

QP21 QP22 QP46

QP47

QN28

QN27

QN26

QN25

lecture_1

Documents